Title of Invention

DRIVE CIRCUIT WITH A TOP LEVEL SHIFTER FOR TRANSMISSION OF AN INPUT SIGNAL, AND AN ASSOCIATED METHOD

Abstract

The invention describes a drive circuit in power-electronic systems having a half-bridge circuit formed by two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged connected in series. The drive circuit has a TOP level shifter for transmitting an input signal from drive logic to a TOP driver. In this case, the TOP level shifter is designed as an arrangement of an UP and a DOWN level shifter path, as well as a downstream signal evaluation circuit. In the associated method for transmission of this input signal, the signal evaluation circuit passes an output signal to the TOP driver when either the UP or the DOWN, or both level shifter paths emit a sign-al to the respectively associates input of the signal evaluation circuit.

Full Text

FORM 2 THE PATENT ACT 1970 (39 of 1970) The Patents Rules, 2003 COMPLETE SPECIFICATION (See Section 10, and rule 13) 1. TITLE OF INVENTION DRIVE CIRCUIT WITH A TOP LEVEL SHIFTER FOR TRANSMISSION OF AN INPUT SIGNAL, AND AN ASSOCIATED METHOD 2. APPLICANT(S) a) Name b) Nationality c) Address SEMIKRON ELEKTRONIK GMBH & CO. KG GERMAN Company POSTFACH 82 0251, 90253 NUERNBERG, GERMANY 3. PREAMBLE TO THE DESCRIPTION The following specification particularly describes the invention and the manner in which it is to be performed : - Description The invention describes a drive circuit with a level shifter, and an associated method for transmission of an input signal from drive logic to a driver. Drive circuits such as these are required in power-electronic systems in order to drive power semiconductor switches which are arranged as individual switches or in a bridge circuit. Bridge circuits such as these are known as single-phase, two-phase or three-phase bridge circuits, with the single-phase so-called half-bridge representing a basic module of a multiplicity of power- electronic circuits. Two power switches, a first so-called TOP switch and a second so-called EOT switch, are arranged connected in series in a half-bridge circuit. In general, a half-bridge such as this is connected to form a direct-current intermediate circuit. The output, typically the alternating-voltage connection of the half-bridge, is generally connected to a load. In general, the drive circuit comprises a plurality of circuit elements or functional blocks. The control signal is preprocessed in a first circuit element, the drive logic, and is supplied via further components to the driver circuits and finally to the control input of the respective power switch. For relatively high intermediate-circuit voltages, for example of more than 100 V, the drive logic is generally DC-isolated from the driver circuits since the associated power switches are at different potentials, so that DC isolation is essential. This isolation applies at least to the TOP switch although, for relatively high power levels, it is also applicable to the EOT switch, because of the earth potential possibly being dragged during switching. By way of example, such isolation may be provided by pulse transformers, by optocouplers or optical waveguides (galvanic isolation) or with the aid of integrated circuit technology using an HVIC (High Voltage Integrated Circuit). The latter variant is used increasingly frequently because of various advantages, such as small dimensions, low price and long life. At the same time, HVICs offer the capability to integrate a high-voltage component with a breakdown voltage that is greater than or equal to the intermediate-circuit voltage which can be used in circuits for signal level conversion, in so-called level shifters. A lateral high-voltage MOSFET is generally used for this purpose. The described level shifter is part of the drive circuit and is preferably in the form of an integrated circuit arrangement. It is used to transmit a signal from a circuit part at a defined reference-earth potential to a circuit part at a reference-earth potential which is higher or lower at times, or vice-versa. An arrangement such as this is required for an integrated and DC-isolated drive for power semiconductors. Two fundamental isolation technologies are known in order to form level shifters for HVICs. SOI (Silicon on Insulator) technologies on the one hand and pn-isolated technologies (Junction Isolation) on the other hand. SOI technology offers dielectric isolation of components and component groups, but is available at the moment only up to a. withstand voltage of 800 V. SOI substrate wafers are considerably more expensive than standard substrates, although the costs are compensated for by a number of advantages and considerable process simplifications which result from the dielectric isolation. In the case of pn-isolated technologies, the reverse voltage is blocked by a reverse-biased pn junction. This technology is available for up to 1200 V at the moment. However, production is highly complex and therefore costly. Furthermore, there are technical problems, for example with leakage currents and latch- up effects, inter alia at relatively high temperatures, for example at an operating temperature of more than 125°C, and when the earth potential is dragged during first dynamic processes. In integrated drive circuits according to the prior art, level shifter transmission of the driver signals from the drive logic to the TOP driver is known. This is necessary since the TOP driver, in contrast to a BOT driver, is at a higher reference-earth potential, on a . phase basis. According to the prior art, the signal transmission from the drive side to the TOP driver takes place by means of pulsed (dynamic) and differential transmission, that is to say switch-on and switch-off pulses are produced on the drive side from the signal to be transmitted, and are transmitted via the respective level shifter to the TOP driver. This type of transmission is distinguished by a high level of transmission reliability and low power consumption. Various integrated level shifter topologies are known. The simplest topology comprises an HV transistor with an appropriate blocking capability and a resistor, connected in series. When a signal is passed to the gate of the HV transistor, it switches on. The parallel current produced in this way through the level shifter causes a voltage drop across the resistor, and this can be detected as a signal by an evaluation circuit. DE 101 52 930 Al discloses an upgraded level shifter topology, in which the drive signal is transmitted in steps by means of n-1 intermediate potentials by means of n known level shifters which are connected identically in cascade. This makes it possible to use transistors which have only the n-th part of the required blocking capability of the entire level shifter. If transistors with the required blocking capability are available, the blocking capability of the level shifter can be increased by the factor n. DE 10 2006 037 336, which was not published prior to this, discloses a level shifter in the form of a series circuit formed by n series-connected HV transistors. This topology has the advantage over DE 101 52 930 Al on the one hand that the power consumption has reduced and on the other hand that the circuit complexity is reduced. This results in less space being required, and therefore also in reduced costs. All the known topologies have the common feature that, with a complementary level shifter design signals can also be transmitted from a circuit part with a high reference-earth potential to a circuit part with a low reference-earth potential. This characteristic can be used to transmit signals back from the TOP driver to the drive logic. According to the prior art, in the case of integrated drive circuits, the drive logic (on the primary side) and the BOT driver (on the secondary side) are at the same reference-earth potential, or at reference-earth potentials which differ from one another by only a few volts, so that there is no need to transmit signals via level shifters. In this case, the connections for the reference-earth potential on the primary side and on the secondary side are generally externally shorted. However, module-internal and system-internal inductances, for example line inductances, can result in the reference-earth potential of the EOT drivers being dragged severely in the positive or negative direction during switching of the power component. This occurs particularly severely in medium-power and high- power systems in which heavy currents, for example of more than 50 A are switched. The potential difference can in this case assume values which are higher than the blocking voltage of the gate oxide of the transistors being used, for example more than 20 V. Junction isolation technologies have the disadvantage that parasitic thyristor structures can be triggered, so-called latch-up, in the negative direction if the reference-earth potential is dragged in a corresponding manner. This leads to loss of function and possibly to destruction of the components affected. SOI technologies are not subject to this restriction, caused by the dielectric isolation of the components, so that it is possible to implement level shifter circuitry which ensures reliable signal transmission even if the reference-earth potential on the secondary side becomes negative briefly or permanently. 10 2006 050 913, which was not published prior to this, discloses a level shifter such as this for BOT drivers using SOI technology in the form of an UP and DOWN level shifter path. However, this drive circuit is not adequate for a bridge topology, since the reference- earth potential of the TOP driver on the secondary side may also be more negative in the reference-earth potential on the primary side. The invention is based on the object of providing a drive circuit, preferably in the form of an at least partially monolithicaliy integrated circuit, in which signals can be transmitted between circuit parts whose reference-earth potential difference is greater than the withstand voltage of the gate oxide of the transistors being used. According to the invention, the object is achieved by the measures of the features in Claims 1 and 8. Preferred embodiments are described in the dependent claims. The inventive idea is based on a drive circuit having a level shifter for preferably unidirectional transmission of a signal from a first circuit part first reference-earth potential, for example the primary side of an integrated gate driver, to a second circuit part with a second potential, for example the TOP secondary side of an integrated gate driver. According to the invention, this drive circuit is developed by having a TOP level shifter for DC- isolating transmission of this input signal. The TOP level shifter itself is in the form of an arrangement of two independently operating transmission paths, the UP and the DOWN level shifter path, as well as a downstream signal evaluation circuit. The UP level shifter transmits the applied level signal from the primary side to the secondary side when the reference-earth potential on the secondary side is equal to or greater than the reference-earth potential on the primary side. The DOWN level shifter transmits the applied input signal from the primary side to the secondary side when the reference-earth potential on the secondary side is equal to or less than the reference-earth potential on the primary side. At least one valid signal is therefore transmitted both when the reference-earth potential on the secondary side is higher than that on the primary side and when the reference-earth potential on the secondary side is lower than that on the primary side. The signal evaluation circuit detects the signals of the outputs of the UP and DOWN level shifters, and reconstructs the transmitted signal on the secondary side. The method according to the invention for transmission of an input signal from the drive logic to a TOP driver within a drive circuit with a TOP level shifter is characterized in that the signal evaluation circuit passes an output signal to the TOP driver when either the UP or the DOWN or both level shifter paths emit a signal to the respectively associated input of the signal evaluation circuit. The solution according to the invention will be explained in more detail with reference to Figures 1 to 4 . Figure 1 shows a block diagram of a monolithically integrated drive circuit according to the prior art. Figure 2 shows a block diagram of a monolithically integrated drive circuit according to the invention with a TOP level shifter. Figure 3 shows the basic circuit of a TOP level shifter for a drive circuit according to the invention. Figure 4 shows simulation results for the method according to the invention. Figure 1 shows a monolithicaliy integrated drive circuit (10) according to the prior art with a half-bridge circuit (70). This half-bridge circuit (70) according to the prior art has a TOP power switch (72) and a BOT power switch (74), which in this case are each in the form of an IGBT with a back-to-back parallel-connected diode. The BOT switch (74) is at the reference-earth potential (gnd_sec) on the secondary side, which is virtually the same as the reference- earth potential (gnd_pri) on the primary side in applications with low line inductances. The reference- earth potential (gnd_pri) on the primary side is the reference-earth potential for the drive circuit (10). The drive circuit (10) itself has drive logic (20) , a TOP level shifter (30) with a downstream TOP driver (40), as well as a BOT level shifter (50) with a downstream BOT driver (60), The reference-earth potential of the BOT driver (60) may in this case be higher than, equal to or less than the reference-earth potential of the drive logic (20). Figure 2 shows a monolithicaliy integrated drive circuit according to the invention with a TOP level shifter (80) which forms the development according to the invention of the prior art as shown in Figure 1. The TOP switch (72) is at the reference-earth potential (gnd_hs) on the secondary side which, particularly in applications with high line inductances may, on a phase basis, be not only more positive but also more negative, than the reference-earth potential (gnd pri) on the primary side. In this case, the TOP level shifter (80) comprises a pulse-generating circuit (82), an UP level shifter path (84), a DOWN level shifter path (86) and a signal evaluation circuit (88) downstream from them. The pulse-generating circuit (82) in each case produces a direct, non-inverted signal and an inverted signal to the UP level shifter path (84), as well as the signals inverted with respect to this, via an inverter, to the DOWN level shifter path (86). The output from the signal evaluation circuit (88) is passed to the input of the TOP driver stage (40). Figure 3 shows a TOP level shifter (80) for a drive circuit according to the invention, in detail. In this context. Figure 4 shows the simulation results for the method according to the invention. The TOP level shifter (80) in this case has two complementary parts, the UP level shifter path (84) and the DOWN level shifter path (86) . Their design and, method of operation are in principle the same, although respectively complementary transistors are used, in each case, that is to say n-channel transistors in the UP level shifter path, with p-channel transistors in the DOWN level shifter path, and vice-versa. Connections to the supply voltage vdd_hs in the UP level shifter path (84) are connected to the corresponding reference- earth potential gnd_hs in the DOWN level shifter path (86), and vice-versa. The reference-earth potential gnd_hs is in this case equal to the potential at the output of the half bridge (70). The design of the UP and DOWN level shifter paths will be explained in the following text. The UP level shifter path (84) is itself formed from two branch elements with the respective switching transistors Ml and M2, the respective high-voltage transistors HV1 and HV2, each of the n-channel type, the respective diodes Dl and D2 as well as the respective resistors Rl and R5, as well as R2 and R6. These components in the respective branch elements are connected in series. The source connections of the respective switching transistors Ml and M2 are connected to the reference-earth potential (gnd_pri) on the primary side via the respective resistors Rl and R2. The respective gates of Ml and M2 are connected to the ON (non-inverted) and OFF (inverted) outputs of the pulse-generating circuit (82) and represent the control inputs of the UP level shifter path. The gates of HV1 and HV2 are connected to the supply voltage (vdd_pri) on the primary side. The drain connections of HV1 and HV2, respectively, are connected to the respective cathodes of the diodes Dl and D2. The anodes of the respective diodes Dl and D2 are connected to the respective resistors R5 and R6, R5 and R6 are also connected to the supply voltage vdd_hs. The anodes of Dl and D2, respectively, form the outputs ON p and OFF_p, respectively, of the UP level shifter path (84) and are connected to the signal evaluation circuit (88). The DOWN level shifter path (86) analogously comprises two path elements with the respective switching transistors Mil and M12, the respective transistors M13 and M14 which preferably have a higher withstand voltage and are of the p-channel type, the respective diodes Dll and D12 as well as the respective resistors Rll and R15 as well as R12 and R16. These components in the respective branch element are connected in series. The source connections of the respective switching transistors Mil and M12 are connected via the respective resistors Rll and R12 to the supply voltage (vdd_pri) on the primary side. The gates of Mil and M 12, respectively, are connected via the respective inverters INV1 and INV2 to the ON and OFF outputs, respectively, of the pulse-generating circuit (82), and represent the control inputs for the DOWN level shifter path. The gates of M13 and M14 are connected to the reference-earth potential (gnd_pri) on the primary side. The drain connections of M13 and M14, respectively, are connected to the respective anodes of the diodes Dll and D12. The cathodes of the respective diodes Dll and D12 are connected to the respective resistors R15 and R16. R15 and R16 are also connected to the reference potential gnd_hs on the secondar.y side. The cathodes of Dll and D12, respectively, form the respective outputs ON_n and OFF_n of the DOWN level shifter path (86), and are connected to the signal evaluation circuit (88). The zener diodes Zl and Z2 connected to the respective resistors R5 and R6, as well as 211 and Z12 connected to R15 and R16, limit the voltages at the respective outputs ON-p and OFF_p, as well as ON-n and OFF_n. The resistors R3 and R4 in the UP level shifter path (84) are connected to the operating voltage connection (vdd_pri) on the primary side, and are each connected to the source of the respective transistors HVl and HV2. When the primary side is in an undefined state, the transistors HVl and HV2 are therefore always switched off. The resistors R13 and R14 carry out the analogous function to the respective transistors M13 and M14 in the DOWN level shifter path (86). The maximum permissible positive voltage difference between the reference-earth potential on the primary side and that on the secondary side is governed by the drain-source withstand voltage of the transistors HVl and HV2, and for negative voltage differences it is governed by the drain-source withstand voltage of the transistors M13 and M14. Signals are transmitted via the UP level shifter path (84) only when the reference-earth potential (gnd_hs) on the secondary side is higher than, just as high as or slightly lower than the reference-earth potential (gnd_pri) on the primary side. The method of operation of the UP level shifter path (84) will be described for this situation in the following text. The corresponding signal waveforms of the inputs and outputs on the respective nodes are illustrated for the corresponding situation in Figure 4, column 2 (gnd_hs=OV) and column 3 (gnd_hs=600V), respectively. A control signal U ON, which is generated by the pulse-generating circuit (82) from a positive flank of the input signal U_IN, for example a square-wave pulse, is passed to the gate of the switching transistor Ml. A control signal U_OFF, which is generated by the pulse-generating circuit (82) from a negative flank of the input signal U_IN), for example a square-wave pulse, is passed to the gate of the switching transistor M2. The control signals in each case cause one of the transistors Ml or M2 to be switched on. When Ml is switched on, the transistor HV1 is likewise opened, and when M2 is switched on, HV2 is opened (cascode principle). On switching on, a parallel current I par flows through the level shifter path. The magnitude of the parallel current Ipar is governed mainly by the respective resistors Rl and R5, as well as R2 and R6. The voltage drops U_ON_p across the resistor R5 and U_OFF p across R6 are proportional to the parallel current Ipar, and represent the respective input signals for the signal evaluation circuit (88). In summary, the digital input signal (U_IN) is therefore converted to current signals, and is thus transmitted via the level shifter. The connected signal evaluation circuit (88) converts the transmitted signal back to a digital signal U_OUT, which is passed to the driver (40) for the TOP switch. If the difference between the reference potential (gnd_hs) on the secondary side and that on the primary side is less than a specific value, for example a few volts, then the predetermined switch-on threshold, which is predetermined in the signal evaluation circuit (88) by a signal value detection circuit, for example a comparator or Schmitt trigger, is not reached. In this case, the input voltage U_IN is not transmitted via the UP level shifter. The output voltage from the UP level shifter then corresponds to the switched-off state (U_ON_p=HIGH). If the potential on the secondary side falls to such an extent that the drain-bulk diodes of the transistors Ml, M2, HV1 and HV2 become forward- biased, that is to say the supply potential (vdd_sec) on the secondary side falls below the reference-earth potential (gnd_pri) on the primary side, then the diodes Dl and D2 block any current flow through both path elements. Signals are transmitted analogously via the DOWN level shifter path (86) only when the reference-earth potential (gnd hs) on the secondary side is less than, just as high as or slightly higher than the reference-earth potential (gnd_pri) on the primary side. The corresponding signal waveforms at the inputs and outputs and the respective nodes are illustrated for a corresponding situation in Figure 4, column 1 (gnd_hs=-15V) and column 2 (gnd_hs=0V) , respectively. A control signal U_ON, which is generated by the pulse-generating circuit (82) from a positive flank of the input signal U_IN, is passed in inverted form to the gate of the p-channel switching transistor Mil. A control signal U_OFF which is generated by the pulse-generating circuit (82) from the negative flank of , the input signal U_IN, is passed in inverted form to the gate of the p-channei switching transistor M12. The control signals in each case cause one of the transistors Mil or M12 to switch on. When Mil is switched on, the p-channel transistor M13 is likewise opened, and M14 isopened when M12 is switched on (cascode principle). On switching on, a parallel current Ipar flows through the level shifter path. The magnitude of the parallel current Ipar is governed mainly by the resistors Rll and R15, as well as R12 and R16. The voltage drops U_ON_n across the resistor R15 and U_OFF_n across R16 are proportional to the parallel current Ipar and represent the respective input signals for the signal evaluation circuit (88). It is therefore also possible to reliably transmit a signal U_IN in these potential conditions between the reference-earth potential (grd_hs) on the secondary side and the reference-earth potential gnd_pri on the primary side, with this signal U_IN being passed as the output signal U_OUT to the driver (40) for the TOP switch. If the difference between the reference-earth potential (gnd_hs) on the secondary side and that on the primary side (gnd_pri) is above a specific value, for example a few volts, then the predetermined switch-on threshold, which is predetermined in the signal evaluation circuit (88) by a signal value detection circuit, for example a comparator or Schmitt trigger, is not reached. In this case, the input voltage U_IN is not transmitted via the DOWN level shifter. The output voltage from the DOWN level shifter then corresponds to the switched-off state (U_ON_n=LOW) . If the potential on the secondary side rises, the reference-earth potential (gnd_hs) on the secondary side rises above the potential of the supply voltage (vdd pri) on the primary side, then the diodes Dll and D12 block any current flow through both path elements. If the difference between the reference-earth potential (gnd_hs) on the secondary side is within the region of a few volts above or below the reference-earth potential (gnd_ri) on the primary side, then both the UP level shifter path (84) and the DOWN level shifter path (86) transmit valid signals from the primary side to the secondary side (see Figure 4, column 2 (gnd_hs=0V) ) . This overlapping range ensures reliable similar transmission even taking into account scatters in the transmission thresholds in different examples of the same circuitry, technology-dependent fluctuations in component parameters, and rapid changes in the reference-earth potential on the secondary side. This increases the reliability of the level shifter (80). The signal evaluation circuit (88) produces a valid drive signal (U_OUT) for the TOP driver (40) when a signal is transmitted either via the UP level shifter path (84) (see Figure 4, column 3 (gnd_hs=600V)) or the DOWN level shifter path (86) (see Figure 4, column 1 (gnd_hs =-15V)), or via both level shifter paths (see Figure 4, column 2 (gnd_hs=0V)) at the same time (OR logic operation). Figure 4 shows the transient transfer function of the level shifter (80) as shown in Figure 3 during a simulation, for a negative reference-earth potential on the secondary side (gnd_hs=-15V, column 1), for the same reference-earth potential on the primary side and secondary side (gnd_hs=OV, column 2), and for a positive reference-earth potential on the secondary side (gnd_hs=600V, column 3) . The reference-earth potential (gnd_pri) on the primary side is in this case the actual earth potential (0V) . The same square-wave drive signal U_IN has been passed to the input IN in both cases. As can be seen from the figure, if the reference-earth potentials on the primary side and secondary side are the same (column 2) , a transmitted signal appears both at the outputs of the UP level shifter (U_ON_p, U_OFF_p) and of the outputs of the DOWN level shifter (U_ON_n, U_OFF_n) while, in contrast, if the reference-earth potential is negative only at the output of the DOWN level shifter (column 1; U_ON_n, U OFF_n) if the reference-earth potential is positive only at the output of the UP level shifter (column 3; U_ON_p, U_OFF_p) a transmitted signal appears and the output of the corresponding complementary level shifter path locks in the switched- off state. In ail three cases, the signal evaluation circuit identifies the fact that at least one signal has been transmitted via the UP level shifter path and, or the DOWN level shifter path, and emits a valid output signal U_OUT. The level shifter (80) therefore has the desired response. WE CLAIM: 1. Drive circuit (10) with a TOP level shifter (80) for transmission of an input signal (IN) from drive logic (20) to a TOP driver (40) , with the TOP level shifter (80) being designed as an arrangement of a pulse generating circuit (82), of an UP (84) and of a DOWN (86) level shifter path and of a downstream signal evaluation circuit (88). 2. Drive circuit according to Claim 1, in which, within the TOP level shifter (80), the UP level shifter path (84) is designed to be essentially complementary to the DOWN level shifter path (86). 3. Drive circuit according to Claim 1, in which the outputs (ON_p, OFF_p) of the UP level shifter path (84) and the outputs (ON_n, OFF_n) of the DOWN level shifter path (86) are connected to the inputs of the signal evaluation circuit (88), and the output of the signal evaluation circuit (OUT) forms the input signal for the TOP driver (40). 4. Drive circuit according to Claim 1, in which the drive logic (20), the TOP level shifter (80) and the TOP driver (40) are monolithically integrated. 5. Drive circuit according to Claim 1, in which the UP level shifter path (84) is formed from two path elements which are themselves formed from the series arrangement of in each case two n- channel transistors Ml, HVl and M2, HV2, respectively, connected in cascode, in each case one diode Dl and D2 and in each case two resistors Rl, R5 and R2, R6, with the source connections of the respective switching transistors Ml and M2 being connected via the respective resistors Rl and R2 to the reference-earth potential on the primary side (gndjpri) with the gates of the Ml and M2 respectively being connected as control inputs of the UP level shifter path to the ON and OFF output, respectively, of the pulse generating circuit (82), with the gates of HV1 and HV2 being connected to the supply voltage (vdd pri) on the primary side, with the drain connections of HV1 and HV2, respectively, being connected to the cathodes of the respective diodes Dl and D2, and with the anodes of Dl and D2, respectively, on the one hand once again forming the outputs ON_p and OFF_p, respectively, of the UP level shifter path (84) to the signal evaluation circuit (88), and on the other hand being connected via the respective resistors R5 and R6 to the supply voltage vdd_hs. 6. The drive circuit as claimed in Claim 1, in which the DOWN level shifter path (86) is formed from two path elements whi.ch are themselves formed from the series arrangement of in each case two p-channel transistors Mil, M13 and M12, M14, respectively, connected in cascode, in each case one diode Dll and D12, respectively, and in each case two resistors Rl, R15 and R12, R16, respectively, with the source connections of the switching transistors Mil and M12, respectively, being connected via the respective resistors Rll and R12 to the supply voltage (vdd_pri) on the primary side, with the gates of Mil and M12, respectively, being connected as control inputs of the DOWN level shifter path to the inverted ON and inverted OFF or outputs, respectively, of the pulse generator circuit (82), with the gates of Ml 3 and Ml 4 being connected to the reference-earth potential (gnd_pri) on the primary side, with the drain connections of Ml 3 and Ml 4, respectively, being connected to the anodes of the respective diodes Dll and D12, and with the cathodes of Dll and D12, respectively, once again on the one hand forming the outputs ON_n and OFF_n, respectively, of the DOWN level shifter path (86) to the signal evaluation circuit (88), and on the other hand being connected via the respective resistors R15 and R16 to the reference-earth potential gnd_hs. 7. Drive circuit according to Claim 1, in which the reference-earth potential of a TOP driver (gnd_hs) can fluctuate up to the magnitude of the maximum possible withstand voltage of the UP and DOWN level shifter paths (84, 86) about the reference-earth potential of the drive logic (gnd_pri), without loss of function occurring. 8. Method for transmission of an input signal (U_IN) from the drive logic (20) to a TOP driver (40) within a drive circuit (10) with a TOP level shifter (80) according to Claim 1, in which the signal evaluation circuit (88) passes an output signal (U__OUT) to' the TOP driver (40) when either the UP (84) or the DOWN (86) or both level shifter paths emit valid control signals (U_ON_p/U_OFF_p, U_ON_n/U_OFF_n) to the respective associated input of the signal evaluation circuit (88). 9. Method according to Claim 8, in which the UP level shifter path (84) emits valid control signals to the associated inputs of the signal evaluation circuit (88) when the reference-earth potential (gnd_hs) on the secondary side is virtually the same as or higher than the reference-earth potential (gnd Jpri) on the primary side, and the DOWN level shifter path (86) emits valid control signals to the associated inputs of the signal evaluation circuit (88) when the reference-earth potential (gnd_hs) on the secondary side is virtually the same as or lower than the reference-earth potential (gnd_pri) on the primary side. ABSTRACT The invention describes a drive circuit in power-electronic systems having a half-bridge circuit formed by two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged connected in series. The drive circuit has a TOP level shifter for transmitting an input signal from drive logic to a TOP driver. In this case, the TOP level shifter is designed as an arrangement of an UP and a DOWN level shifter path, as well as a downstream signal evaluation circuit. In the associated method for transmission of this input signal, the signal evaluation circuit passes an output signal to the TOP driver when either the UP or the DOWN, or both, level shifter paths emit a sign-al to the respectively associated input of the signal evaluation circuit. To, The Controller of Patents, The Patent office Mumbi (Fie. 2)

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