Title of Invention

A CIRCUIT TO REDUCE STRAY INDUCTANCE AND A 3-PHASE CONVERTER THEREOF

Abstract

The present invention relates to a novel circuit, method and three-phase multi-layer Voltage Source Converter / Inverter (VSC/VSI) with multi-layer, sandwich bus-plates to converter to minimize the stray inductance of the interconnections and which will enable the converter to be operated at higher switching frequencies without any dissipating snubber. A capacitor resistor network is also proposed which has negligible losses to snub the voltage spikes generated due to minimum stray inductance, if any in the new three-phase multi-layer Voltage Source Converter / Inverter.

Full Text

Field of the Invention: The present invention relates to a novel three-phase multi-layer Voltage Source Converter / Inverter (VSC/VSI) with multi-layer, sandwich bus-plates to converter to minimize the stray inductance of the interconnections and which will enable the converter to be operated at higher switching frequencies without any dissipating snubber. A capacitor resistor network is also proposed which has negligible losses to snub the voltage spikes generated due to minimum stray inductance, if any in the new three-phase multi-layer Voltage Source Converter / Inverter. The switching devices with optimum voltage rating can be used without voltage de-rating. Background and Prior Art Description: The conventional switching converter layouts are switching devices interconnected with current carrying cables, which is generally referred as wire-bond technology. These layouts are successful in applications with switching frequencies in the order of 1 KHz whereas in modern power electronic systems like active filters switching requirement is more than 8 KHz. With the modern switching devices like IGBTs the switching frequency can be increased to higher values in the order of 10-20 KHz, for converters with a few hundreds of amperes. Moreover, the switching Turn ON and Turn OFF time of IGBT are very short compared to old generation devices like thyristors, GTOs etc. This property introduces higher voltage spikes due to rapid fall of currents in the presence of stray inductance associated with the wired interconnections in the converter. Dissipating snubbers are required to relieve the switching devices from the voltage stress. Design of such snubber is difficult task and it causes poor converter efficiency. Higher voltage de-rating of switching devices is a common practice to tackle the voltage stress problem. This will result in an un-economical and bulky converter construction. Especially, in multi-level converter topology, the interconnections between various power semiconductors are more complex. Summary of the Invention: The present invention provides a symmetrical structure for power electronic converters, which combines the features of reliable interconnection and effective insulation with minimum mechanical strain on IGBT modules. The bus-plates with large surface area, aid the cooling of the converter assembly. This technology also ensures reliable electrical connection between different terminals of the converter arm and the layout is easy for assembly for servicing. This architecture can be conveniently extended for higher level; of multi-level converter implementation. Brief Description of the Accompanying Drawings: In the drawings accompanying the specification, Fig. 1 represents a block schematic diagram of the active filter showing power hardware, feed block requirements and different digital converts. Fig. 2 represents a detailed electrical schematic (circuit) diagram of the phase leg of a three level converter in accordance with a first embodiment of the present invention. Fig. 3 represents the arrangement of the heat sink, DC bus capacitor and switching devices of the stack. Fig. 4 represents the exploded view of the multi-layer bus plates of the converter phase leg. Fig. 5 represents the isometric view of the fully assembled phase leg. Fig. 6 represents the 3-phase converter stack which is comprises of the individual phase legs interconnected to each other. Fig. 7 is a photograph of the fully assembled converter phase leg. Fig. 8 represents the dual IGBT module showing all terminals. Fig. 9 represents the interconnections in Block 1 in the layout shown in Fig. 3. Fig. 10 represents the interconnections in Block 2 in the layout shown in Fig. 3. Fig. 11 represents the switching waveforms of complementary switches of the converter phase leg. The waveforms show minimum voltage spikes due to leakage inductance. Fig 12 represents the capacitors in the 3-Ievel converter Objects of the present invention: The main object of the present invention is to develop to a circuit to reduce stray inductance and/or to dissipate heat comprising multi-layered conductive bus-plates Yet another main object of the present invention is to develop a method to reduce stray inductance and/or to dissipate heat. Still another object of the present invention is to interconnecting components using multi-layered conductive bus-plates wherein the plates are insulated from each other. Still another main object of the present invention is to develop a stacked 3-phase converter with reduced stray inductance and/or for heat dissipation comprising multi-layered conductive bus-plates. Statement of the present Invention: The present invention is related to a circuit to reduce stray inductance and/or to dissipate heat comprising multi-layered conductive bus-plates; a method to reduce stray inductance and/or to dissipate heat, said method comprising step of interconnecting components using multi-layered conductive bus-plates wherein the plates are insulated from each other; and a stacked 3-phase converter with reduced stray inductance and/or for heat dissipation comprising multi-layered conductive bus-plates. Detailed Description of the Present Invention: The present invention is related to a circuit to reduce stray inductance and/or to dissipate heat comprising multi-layered conductive bus-plates. Yet another embodiment of the present invention is the plates interconnect components of the circuit. Still another embodiment of the present invention is the plates are insulated from each other using glass epoxy film of about 0.6mm thickness. Still another embodiment of the present invention is the plates are nickel coated copper plates. Still another embodiment of the present invention is the plates are selected on the basis of their voltage gradient. Another main embodiment of the present invention is a method to reduce stray inductance and/or to dissipate heat, said method comprising step of interconnecting components using multi-layered conductive bus-plates wherein the plates are insulated from each other. Still another embodiment of the present invention is the plates using glass epoxy film of about 0.6mm thickness. Still another embodiment of the present invention is arranging the plates to minimizing the voltage difference among adjacent bus plates. Still another embodiment of the present invention is provides low inductance of the interconnections. Still another embodiment of the present invention is the plates provide distributed capacitance. Still another embodiment of the present invention is large exposed area of conducting plates provides for dissipation of heat. Another main embodiment of the preset invention is a stacked 3-phase converter with reduced stray inductance and/or for heat dissipation comprising multi-layered conductive bus-plates. Yet another embodiment of the present invention is the plates interconnect components of the circuit. Still another embodiment of the present invention is the plates are insulated from each other using glass epoxy film of about 0.6mm thickness. Still another embodiment of the present invention is the plates are selected on the basis of their voltage gradient. Still another embodiment of the present invention is interconnecting positive, negative and middle bus plates of capacitor bank of each layer using bus bars. Still another embodiment of the present invention is the plates are nickel coated copper plates. Still another embodiment of the present invention is the gate driver is placed near IGBT to get improved noise immunity. Still another embodiment of the present invention is the gate signal from the gate driver PCB is connected to IGBT module using twisted insulated wires to minimize noise coupling. Still another embodiment of the present invention is the capacitor (cpl, cp2), resistor (Rs) network provide across IGBT to avoid voltage spikes. In the present invention, there is provided a novel three phase converter wherein each phase leg of the three phase converter is integrated as a stack, which contains IGBT modules mounted on the heat sink, gate drivers, fans for forced air cooling, thermistors mounted on the heat sink near the device (fro temperature sensing), one third of capacitors of the DC capacitor bank and the inter-connection sandwich bus plates. The positive, negative and middle bus plates of the other two stacks with bus bars to form the entire three phase converter module. IGBT modules are mounted on the heat sink after applying a thin layer of heat sink compound between the module and the heat sink surface, with the help of mounting screws and spring washers. Heat sink compound is applied for better heat transfer from device to heat sink and is not essential part of the invention. The interconnection between different elements (capacitors and IGBT modules) in the power circuit is achieved by multiple layers of copper bus plates, made of nickel coated copper plates of thickness 1.5 mm to 3 mm. These copper plates are optionally epoxy coated for insulation in the exposed area. Gloss epoxy film of about 0.6 mm thickness is provided between different bus plates for inter layer insulation between bus plates of differential potential. The Copper plates between the layers serve as interconnects. In this assembly there are six layers of copper bus plates. Figure 2 shows the electrical connections in a phase leg of the converter. Different bus plates are arranged by considering the voltage gradient, to minimize the voltage between the near by bus plates. The geometry of the bus plates allows uniform current distribution and proper current sharing between parallel IGBT switches. Different bus plates and their electrical significance are described below: Positive bus plate: Interconnects positive terminals of capacitors CI and C2 and Collector 1 (Col-1) of IGBT modules in block 1. Capacitor interconnecting bus plate 1: Connects negative terminals of CI and C2 with positive terminals of C3 and C4. IGBT interconnection bus plate 1: Interconnects Col-1 of IGBT modules in Block 2 and Col-2 / Em-1 of IGBT modules in Block 1. Middle bus plate: Interconnects negative terminals of the capacitors C3 and C4, positive terminals of the capacitors C5 and C6, Em-2 of IGBT modules in Block 1 and Col-1 of IGBT modules in Block 3. AC load bus plate: Interconnects Col-2 / Em-1 of IGBT modules in Block 2 and is brought out for tapping. IGBT interconnecting bus plate 2: Interconnects Em-2 of IGBT modules in Block 2 and Col-2 / Em-1 of IGBT modules in Block 3. Capacitor interconnecting bus plate 2: Connects negative terminals of C5 and C6 with positive terminals of C7 and C8. Negative bus plate: Interconnects negative terminals of the capacitors C7 and C8 and Em-2 of IGBT modules in Block-3. The capacitor equalizing resistors are assembled on a PCB and mounted on the capacitors as shown in Fig. 4 and Fig. 7. The pole capacitors are mounted on the unit in a similar way. Referring to the schematic diagram of the 3-Level converter (fig 2), the inter connections required are shown in different colours. In the three dimensional multilayer arrangement it is required to have 8 bus bars. In the arrangement under consideration the following busbars are in the same plane in the converter phase arm arrangement (Refer Fig 4 of the original document) Capacitor interconnecting plate 1 Capacitor interconnecting plate 2 AC load bus plate This results in a compact converter circuit with 3-dimensional interconnections. The bus bars will be arranged one over the other. The terminals of the components like capacitors and IGBTs are in the plane of the first busbars (bottom most). To establish a connection from top bus bar to the component terminals vias are provided where a plated copper screw is connecting the top bus with the component terminal and enough clearance is provided for the holes on the bottom plates through which the screw passes. This method is somewhat similar in the vias of the multi layer printed circuit boards. From the above explanation it is clear that the converter now has minimum path lengths for all interconnections unlike in wire-connected arrangement. Moreover the circuit has symmetry and all forward and return current paths are more or less of similar lengths. The distributed capacitance of the multilayer bus plates with insulation sheets in between also compensates the stray inductance. This results in considerable reduction of stray inductance. It is possible to achieve a good multi layer bus arrangement for 2-level inverter with two layers of bus plates. This is because of the reduced complexity of interconnections in 2-level inverter. Implementing a three level inverter with discrete switches using the conventional wirebond-2 dimensional wiring will not suit operation at switching frequencies of 10 or 20 kHz. This is primarily due to the stray inductance of the interconnecting path, which introduces large voltage spikes across the devices when it is switching. This can damage the switching devices. Dissipative snubbers are the conventional solution to this problem. But design and realization of suitable snubber is a difficult task The multilayer bus bar architecture is superior in converter applications due to • Low inductance of the interconnections • Distributed capacitance of the sandwich bus plates • Improved thermal characteristics The busbars in the 3-Level inverter is arranged such that the stray inductance is minimum by ensuring optimum and symmetric current paths. The bus plates stacked one over the other with insulator in between. This introduces distributed capacitance which eventually compensates the stray inductance of the current path. The bus plates with large exposed area helps in conduct away the heat energy dissipated in the switching device. This improves the efficiency of the cooling arrangement. Large dissipative snubbers are not required in this arrangement to absorb the energy associated with the switching voltage spikes. The driver PCBs (FIG 7) for IGBT modules are also integrated to this stack. They are mounted very near to their respective gate emitter terminals of the IGBT modules with the purpose of minimizing the effects due to parasitic inductance between the drivers' output stage and the IGBT modules using twisted insulated wires to minimize noise coupling. The cooling fans (FIG 7) for forced air cooling are integrated with the phase leg stack. A duct is designed and integrated with the cooling system to contain the air flow. Thermostats are embedded on the heat sink for over temperature protection. A fully assembled converter arm is shown in Fig. 7. Brief Description of the Interconnections in Block 1 and Block 3: As can be noticed from Fig. 9, one of the IGBT switches in this block is not used (corresponding gate emitter are shorted) and the anti-parallel diode of that switch is used as the clam diode of the converter. An arrangement somewhat similar to this is used for realizing Block 3. Two diodes are connected in parallel to build Block 1 and Block 3 to achieve the required current rating for a 500 KVAR active filter tried to 3-phase system with a line-to-line voltage of 830V. Brief Description of the Interconnections in Block 2: As can be seen from figure 10, both switches of dual IGBT modules are used in Block 2. Three IGBT modules are connected in parallel so as to meet the current rating. In the three level converter, the switching strategy adopted causes the middle switches (S2 and S3 in Fig. 2) conduct for more time when compared with other two switches namely SI and D4, hence more IGBTs are paralleled to meet the requirement. Resistor capacitor network across IGBT terminals Resistor capacitor network is provided across IGBT terminals (Cpi, CP2 and Rs in Fig. 2) to mitigate hazardous voltage spikes across the device, which occur during device transitions. High voltage rated capacitors are connected across top and bottom switches (SI and S4 respectively in Fig. 2) and a resistance is connected across collector of second switch (S2) and emitter of third switch (S3) with suitably designed values. Even if there is mention of capacitors as snubber capacitors, it is not comparable with the capacitors in conventional dissipative snubbers. A terminology pole capacitor may be used instead of snubber capacitor, which is a DC capacitor (0.22 DF, 1000 Volts, Poly propylene capacitor in the converter referred in the original document) mounted directly on the terminals of the dual IGBT as shown in fig 10 of the original document. With this minimum capacitor the commutation of the IGBT is performed at higher switching frequencies with minimum voltage spikes. This capacitor supports the high frequency currents during the switching of the device. The capacitor provides a low impedance path for the high frequency leakage voltage spike that may occur during switching. Similarly the resistor across middle switches of the converter are also not the resistors in the conventional snubber circuit. These resistors ensures the operation of clamp diodes when either top two switches or bottom two switches are ON. This ensures equal voltage sharing of the pair of switches (either bottom or top) which are in OFF state. CI- C8 are the capacitors in the DC bus. Fig 2 shows the component arrangement in one arm of the 3- Level inverter. The 3-Phase inverter has a total DC bus capacitance of 7050 |iF with a voltage rating of 2000Volts, The bus capacitor arrangement is shown in figure 12. Each capacitor is 4700 fxF with a voltage rating of 500 Volts. The number of parallel paths is in accordance with the total ripple current requirement of the inverter. Each phase leg of the inverter is constructed as a module and the capacitors are equally distributed in each phase leg. This means that there will be a total of 8 capacitors in each phase leg ie C1-C8 in R phase, i.e. in one parallel path of capacitor bank there are 4 capacitors connected in series. The capacitor voltage sharing is based on its equivalent series resistance (ESR). To ensure a perfect voltage balancing of capacitors bleeder resistors of equal values are put across each capacitor. Fig 1 shows the block schematic diagram of the 3- phase active filter. This active filter compensates for the reactive and harmonic currents drawn by the load so as to keep the grid at unity power factor with minimum THD in the current waveform. The active filter is realized with a current controlled voltage source inverter connected to grid through a series choke. The voltage source inverter is build with Insulated Gate bipolar Transistors (IGBT). Since the system is a current controlled one it requires both inverter and load currents to be sensed and fed to Controller Unit, which is a Digital Signal Processor based hardware. The inverter has a DC capacitor bank and the DC bus voltage also need to be sensed. The gate driver transmits the gate trigger signal from the digital hardware to the power hardware (IGBT inverter). Forced air-cooling is used for cooling the converter stack. The system has protective components like fuses and contactor. Fig 6 shows the complete converter stack arrangement of the 3-phase inverter. 3-Phase inverter has 3-phase legs realized with IGBTs. This is clear from fig 2. The DC bus capacitors are distributed equally on each of the three phase legs. The positive bus, negative bus and the middle bus of the capacitor bank of all the phase legs are interconnected. The interconnection of each phase leg is shown in fig 6. Only negative and middle bus interconnections are visible and the positive bus interconnection is on the opposite side. The positive plate is visible in Fig 7 (item 12) of the original document. The heatsinks, sandwich bus arrangement, bleeder resistors etc are also visible. Fig 11 shows the switching waveforms across the devices switching at 10 kHz. The waveforms show no spike or undershoot as the stray inductance is very small with the multi layer bus architecture. We claim: 1. A circuit to reduce stray inductance and/or to dissipate heat comprising multi-layered conductive bus-plates. 2. The circuit as claimed in claim 1, wherein the plates interconnect components of the circuit. 3. The circuit as claimed in claim 1, wherein the plates are insulated from each other using glass epoxy film of about 0.6mm thickness. 4. The circuit as claimed in claim 1, wherein the plates are nickel coated copper plates. 5. The circuit as claimed in claim 1, wherein the plates are selected on the basis of their voltage gradient. 6. A method to reduce stray inductance and/or to dissipate heat, said method comprising step of interconnecting components using multi-layered conductive bus-plates wherein the plates are insulated from each other. 7. The method as claimed in claim 6, wherein insulating the plates using glass epoxy film of about 0.6mm thickness. 8. The method as claimed in claim 6, wherein arranging the plates to minimizing the voltage difference among adjacent bus plates. 9. The method as claimed in claim 6 provides low inductance of the interconnections. 10. The method as claimed in claim 6, wherein the plates provide distributed capacitance. 11. The method as claimed in claim 6, wherein large exposed area of conducting plates provides for dissipation of heat. 12. A stacked 3-phase converter with reduced stray inductance and/or for heat dissipation comprising multi-layered conductive bus-plates. 13. The converter as claimed in claim 12, wherein the plates interconnect components of the circuit. 14. The converter as claimed in claim 12, wherein the plates are insulated from each other using glass epoxy film of about 0.6mm thickness, 15. The converter as claimed in claim 12, wherein the plates are selected on the basis of their voltage gradient. 16. The converter as claimed in claim 12, wherein interconnecting positive, negative and middle bus plates of capacitor bank of each layer using bus bars. 17. The converter as claimed in claim 12, wherein the plates are nickel coated copper plates. 18. The converter as claimed in claim 12, wherein the gate driver is placed near IGBT to get improved noise immunity. 19. The converter as claimed in claim 12, wherein the gate signal from the gate driver PCB is connected to IGBT module using twisted insulated wires to minimize noise coupling. 20. The converter as claimed in claim 12, wherein the capacitor (cpl, cp2), resistor (Rs) network provide across IGBT to avoid voltage spikes. 21. A circuit, method and converter, substantially as herein described with reference to the accompanying drawings. /] /1 A II

Documents:

1200-CHE-2005 AMENDED PAGES OF SPECIFICATION 24-02-2012.pdf

1200-CHE-2005 AMENDED .CLAIMS 24-02-2012.pdf

1200-CHE-2005 AMENDED CLAIMS 24-02-2012.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS 10-03-2011.pdf

1200-CHE-2005 POWER OF ATTORNEY 24-02-2012.pdf

1200-CHE-2005 POWER OF ATTORNEY. 24-02-2012.pdf

1200-CHE-2005 AMENDED CLAIMS 19-04-2012.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS 17-09-2010.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS 02-03-2012.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS 03-11-2010.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS 06-05-2011.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS 24-02-2012.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS 19-04-2012.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS. 24-02-2012.pdf

1200-CHE-2005 CORRESPONDENCE OTHERS.pdf

1200-CHE-2005 CORRESPONDENCE PO.pdf

1200-CHE-2005 FORM-18.pdf

1200-CHE-2005 POWER OF ATTORNEY.pdf

1200-CHE-2005 CLAIMS 13-10-2009.pdf

1200-CHE-2005 DESCRIPTION (COMPLETE) 13-10-2009.pdf

1200-che-2005 examination report reply recieved 13-10-2009.pdf

1200-che-2005-abstract.pdf

1200-che-2005-claims.pdf

1200-che-2005-correspondnece-others.pdf

1200-che-2005-correspondnece-po.pdf

1200-che-2005-description(complete).pdf

1200-che-2005-description(provisional).pdf

1200-che-2005-drawings.pdf

1200-che-2005-form 1.pdf

1200-che-2005-form 3.pdf

1200-che-2005-form 5.pdf

1200-che-2005-form9.pdf