Title of Invention	'A FIELD PROGRAMMABLE LOGIC DEVICE WITH EFFICIENT MEMORY UTILIZATION'
Abstract	The present invention provides a structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable logic blocks and the input-output resources of the FPGA access the embedded memory or RAM using dedicated direct interconnects. A major part of these direct interconnects surface from programmable logic blocks in vicinity of the RAM. The rest run between the input-output (IO) pads/routing and the RAM blocks. A dedicated bus-routing architecture is provided to club the memories to emulate larger RAM blocks. This bus routing is devoted to interconnection among RAM blocks and is isolated from the PLB routing resources.

Title of Invention

'A FIELD PROGRAMMABLE LOGIC DEVICE WITH EFFICIENT MEMORY UTILIZATION'

Abstract

The present invention provides a structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable logic blocks and the input-output resources of the FPGA access the embedded memory or RAM using dedicated direct interconnects. A major part of these direct interconnects surface from programmable logic blocks in vicinity of the RAM. The rest run between the input-output (IO) pads/routing and the RAM blocks. A dedicated bus-routing architecture is provided to club the memories to emulate larger RAM blocks. This bus routing is devoted to interconnection among RAM blocks and is isolated from the PLB routing resources.

Full Text	Field of the invention: The present invention relates to a field programmable logic device with efficient memory utilization. Background of the invention: Configurable memories are embedded in field programmable logic devices to provide on-chip fast RAM. There are two types of memory resources commercially available as shown in FIG 1. The first type are the LUTs inside Logic blocks 102 of FIG1, that can be combined in various fashions to provide memories of varying widths and depths as in Xilinx XC4000 and Virtex devices. A drawback with these distributed memory resources is that the large memory formed by combining these resources is slow. Moreover one has to provide read/write control circuitry with all LUTs. In case these LUTs are not used to implement memory then the read/write control circuitry associated with LUTs is wasted. The second type of on-chip memory resources is the large chunks/blocks of RAM bits 101 of FIG1, as provided by Xilinx and Altera. These can be configured to provide memories with varying widths and depths. A drawback associated with these resources is that if a block (of say 4k) is used to implement a small memory (say 512x2)), then there is wastage of unused RAM bits (3K). Moreover if a logical memory supports an odd width (say 256x9) then there is even more wastage of resources. The following scenario provides the motivation for providing heterogeneous memory structures in an FPGA or PLD. US patent no. 5801547 described embedded memory structures of the same type which may be combined and configured independently. Accordingly, this patent also sufferrs from the drawbacks described above. The object and summary of the invention: The object of this invention is to obviate ihe above drawbacks. To achieve the said objective this invention provides a field programmable logic device comprising at least two independently configurable embedded memory structures (201, 202) said at least two memory structures including: a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set of available configuration depths, and a first set of available configuration widths, a second memory structure (202) with second configuration options of configurable configuration parameters including a second memory size, a second set of available configuration depths, and a second set of available configuration widths, said memory structures (201, 202) being interconnected (505a, 505b, 508) to form a combined memory structure having a combined set of configuration parameters, characterized in that said first and second configuration options are independently configurable and mutually exclusive in respect of at least one of said configurable parameters, said combined set of configuration parameters including at least one combined parameter comprised of the combination of mutually exclusive homologous parameters of said first (201) and second (202) memory structure for efficient memory utilization without redundancy. The said memory structures are combined to form larger configurations through interconnection of dedicated memory routing tracks (505a, 505b) and horizontal routing channels (508). The said dedicated memory routing tracks (505a, 505b) comprising plurality of bus based vertical tracks originating from memory IDs. The horizontal routing channels (508) comprising several routing tracks. The said dedicated memory routing tracks (505a, 505b) interact with the horizontal routing channels (508) through programmable switches (400). A single set of dedicated memory routing tracks (505a, 505b) spans one or more memory blocks and a plurality of horizontal routing channels (508). The upper and lower end of dedicated memory routing tracks (505a, 505b) are a set of bus based bi-directional programmable buffers (507) to connect different blocks of memory to form deeper and/or wider memories. Since each memory structure (201, 202) supports only a subset of total configuration modes available, the size of the multiplexer at the input/output of said memories (201, 202) will be reduced thereby enhancing the speed of access to the memories. The said memory structures (201, 202) are used independently or in combination to implement logic functions. The said memory structures (201, 202) are multi-port. The said memory structures (201, 202) are Read Only Memory (ROM), Random Access Memory (RAM), Content Addressable Memory (CAM), First In First Out (FIFO) structures. The present invention also provides a method of making a field programmable logic device comprising at least two independently configurable embedded memory structures (201, 202) the method including the steps of: providing a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set of available configuration depths, and a first set of available configuration widths, providing a second memory structure (202) with second configuration options of configurable configuration parameters including a second memory size, a second set of available configuration depths, and a second set of available configuration widths, interconnecting (505a, 505b, 508) said memory structures (201, 202) to form a combined memory structure having a combined set of configuration parameters, characterized in that the method further includes the steps of: making said first and second configuration options independently configurable and mutually exclusive in respect of at least one of said configurable parameters, and including in said combined set of configuration parameters at least one combined parameter comprised of the combination of mutually exclusive homologous parameters of said first (201) and second (202) memory structure for efficient memory utilization without redundancy. Brief Description of the drawings: Figure 1 shows the memory structure according to the prior art consisting of only one type of embedded memory array Figure 2 shows the arrangement according to present invention wherever two types of embedded memory arrays are provided Figure 3 shows the example of the use of two different configurable memory structures to obtain memory of different width. Figure 4 shows the implementation for obtaining 256 x 9 logical memory Figure 5 shows the preferred method of memory to memory and memory to logic interaction. Detailed Description of the invention: It is proposed to provide two or more types of memory resources with the types being distinguishable by the configuration modes supported by them or their size or both. For ease of understanding, at present consider only two types of memory resources. In one embodiment, the different memory structures can be distinguished both on the basis of the configuration modes supported by them and their sizes as shown in Fig 2. FIG2 represents the preferred type of Programmable Logic device that includes three types of programmable resources viz. 201, 202, 203. Component 201 represents programmable memory block with wider configurable data widths and/or larger core size with respect to component 202. Component 202 represents programmable memory block with smaller configurable data widths and/or smaller core size with respect to component 201. Component 203 represents programmable logic blocks that can be any of a PLA or LUT based circuit to implement logic intensive circuits. 202 of FIG2 supports small memory requirements (memory size) with plurality of smaller configurable word sizes for example xl, x2, and x4. The smaller configurable memory arrays can be combined using dedicated (bus-based) as well as general routing resources to create wider or deeper memories. 201 of F1G2 supports large memory requirements (memory size) with plurality of larger configurable word sizes as x8, x16, and x32. The larger memory arrays can also be combined using separate dedicated (bus-based) as well as general routing resources to create wider or deeper memories. Since each memory structure is supporting only a subset of the total configuration modes available, the size of the multiplexer at the input/output of the memories will be reduced. Reduced flexibility at each level enhances the speed of operation at both levels, though it does not affect the overall number of possible combinations of different word sizes available. As the configuration modes supported by both types of memory structures are mutually exclusive they do interact with each other and no separate routing resources between the two types of memory structures are needed. As shown in F1G3, consider if the size of the smaller memory structure is 256 bits and that of the larger memory structure is 2Kbits implying that the smaller memory can implement any of 256x1, 128x2 or 64x4 and the larger can implement any of the 256x8, 128x16 or 64x32 then x9, xl8, x36 modes can also be easily realized as the memory depth in both the memory structures is the same. One of these types of implementation is illustrated in FIG4. FIG4 shows one of the preferred ways to implement a 256x9 logical memory that may be required in some designs. In F1G4, one block of 201 memory and one block of 202 memories are combined to form a memory block of size 256x9 The block of 202 memory is configured in 256x1 mode. 256x1 mode means that this memory has 256 words of 1 bit each. To address 256 words, this memory requires 8 address lines 401, and its output data bus 403, is 1 bit wide. The block of 201 memory is configured in 256x8 mode. 256x8 mode means that this memory has 256 words of 8 bit each. To address 256 words, this memory requires 8 address lines 402, and its output data bus 404, is 8 bits wide. Now to create a 256x9 memory block, the 201 and 202 blocks are combined in the following manner. The address buses of 202 block and 201 block, i.e., 401 and 402 are shorted. The short connection is provided through routing segments and programmable connections (see FIG4). The output data buses of both the blocks together, i.e., 403 and 404 represent the data bus, 405 of 256x9 memory. F1G5 shows a preferred way of memory to memory and memory to logic interaction scheme. The memory block (any of 202 or 201) interacts with logic blocks 203, and other memory blocks through dedicated memory routing tracks and horizontal routing channels. The dedicated memory routing tracks (505a & 505b) consist of plurality of bus-based vertical tracks (originating from memory I/Os) that interact with horizontal routing channels 508, through programmable switches, 400. The horizontal routing tracks in turn interact with logic blocks. The horizontal routing channels also consist of several routing tracks. The dedicated memory routing tracks interact with horizontal routing channels through programmable switches. A single set of dedicated memory routing tracks spans one (or more) memory block and a plurality of horizontal routing channels (as shown in the FIG5). At the upper and the lower ends of dedicated memory routing tracks are a set of bus-based bi-directional programmable buffers 507, that help to connect different blocks of memories to form deeper and/or wider memories. The connection box where dedicated memory routing tracks interact with horizontal routing channels is called Memory Logic Interface (506a & 506b). The interconnections between memory blocks and logic blocks are made possible with this Memory Logic Interface box. It is to be noted that the attached figure is only a representation of the case, in actual connections the number of address and data lines would be larger than shown in the figure. Also the number of tracks in horizontal channel, and the topology of switches in Memory Logic Interface box could be different. In another embodiment of the invention, the different memory structures are distinguished on the basis of the configuration modes supported by them but have same size. In another embodiment different memory structures are provided that are distinguished on the basis of their sizes but supporting same configuration modes. Also, in another embodiment both or any one of the memories can be used in asynchronous ROM mode to implement substantial logic when the design does not require all the on-chip memory resources provided thus saving LUTs in all the cases considered above. The above explanation can be easily extended to more than two types of memory resources. We claim: 1. A field programmable logic device comprising at least two independently configurable embedded memory structures (201, 202) said at least two memory structures comprising: a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set of available configuration depths, and a first set of available configuration widths, a second memory structure (202) with second configuration options of configurable configuration parameters including a second memory size, a second set of available configuration depths, and a second set of available configuration widths, said memory structures (201. 202) being interconnected (505a, 505b, 508) to form a combined memory structure having a combined set of configuration parameters, characterized in that said first and second configuration options are independently configurable and mutually exclusive in respect of at least one of said configurable parameters, said combined set of configuration parameters including at least one combined parameter comprised of the combination of mutually exclusive homologous parameters of said first (201) and second (202) memory structure for efficient memory utilization without redundancy. 2. A field programmable logic device as claimed in claim 1, wherein said memory structures are combined to form larger configurations through interconnection of dedicated memory routing tracks (505a, 505b) and horizontal routing channels (508). 3. A field programmable logic device as claimed in claim 2, wherein said dedicated memory routing tracks (505a, 505b) comprising plurality of bus based vertical tracks originating from memory IOs. 4. A field programmable logic device as claimed in claim 2, wherein horizontal routing channels (508) comprising several routing tracks. 5. A field programmable logic device as claimed in claim 2, wherein said dedicated memory routing tracks (505a, 505b) interact with the horizontal routing channels (508) through programmable switches (400). 6. A field programmable logic device as claimed in claim 2, wherein a single set of dedicated memory routing tracks (505a, 505b) spans one or more memory blocks and a plurality of horizontal routing channels (508). 7. A field programmable logic device as claimed in claim 2, wherein the upper and lower end of dedicated memory routing tracks (505a, 505b) are a set of bus based bi directional programmable buffers (507) to connect different blocks of memory to form deeper and/or wider memories. 8. A field programmable logic device as claimed in claim 1, wherein since each memory structure (201, 202) supports only a subset of total configuration modes available, the size of the multiplexer at the input/output of said memories (201, 202) will be reduced thereby enhancing the speed of access to the memories. 9. A field programmable logic device as claimed in claim 1, wherein said memory structures (201, 202) are used independently or in combination to implement logic functions. 10. A field programmable logic device as claimed in claim 1, wherein said memory structures (201, 202) are multi-port. 11. A field programmable logic device as claimed in claim 1, wherein said memory structures (201, 202) are Read Only Memory (ROM), Random Access Memory (RAM), Content Addressable Memory (CAM), First In First Out (FIFO) structures. 12. A method of making a field programmable logic device comprising at least two independently configurable embedded memory structures (201, 202) the method comprising the steps of: providing a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set of available configuration depths, and a first set of available configuration widths, providing a second memory structure (202) with second configuration options of configurable configuration parameters including a second memory size, a second set of available configuration depths, and a second set of available configuration widths, interconnecting (505a, 505b, 508) said memory structures (201, 202) to form a combined memory structure having a combined set of configuration parameters, characterized in that the method further includes the steps of: making said first and second configuration options independently configurable and mutually exclusive in respect of at least one of said configurable parameters, and including in said combined set of configuration parameters at least one combined parameter comprised of the combination of mutually exclusive homologous parameters of said first (201) and second (202) memory structure for efficient memory utilization without redundancy. 13, A field programmable logic device comprising at least two independently configurable embedded memory structures substantially as herein described with reference to and as illustrated in the accompanying drawings. 14. A method of making a field programmable logic device comprising at least two independently configurable embedded memory structures substantially as herein described with reference to and as illustrated in the accompanying drawings.

Full Text

Field of the invention:
The present invention relates to a field programmable logic device with efficient memory utilization.
Background of the invention:
Configurable memories are embedded in field programmable logic devices to provide on-chip fast RAM. There are two types of memory resources commercially available as shown in FIG 1. The first type are the LUTs inside Logic blocks 102 of FIG1, that can be combined in various fashions to provide memories of varying widths and depths as in Xilinx XC4000 and Virtex devices. A drawback with these distributed memory resources is that the large memory formed by combining these resources is slow. Moreover one has to provide read/write control circuitry with all LUTs. In case these LUTs are not used to implement memory then the read/write control circuitry associated with LUTs is wasted.
The second type of on-chip memory resources is the large chunks/blocks of RAM bits 101 of FIG1, as provided by Xilinx and Altera. These can be configured to provide memories with varying widths and depths. A drawback associated with these resources is that if a block (of say 4k) is used to implement a small memory (say 512x2)), then there is wastage of unused RAM bits (3K). Moreover if a logical memory supports an odd width (say 256x9) then there is even more wastage of resources.
The following scenario provides the motivation for providing heterogeneous memory structures in an FPGA or PLD.
US patent no. 5801547 described embedded memory structures of the same type which may be combined and configured independently. Accordingly, this patent also sufferrs from the drawbacks described above.
The object and summary of the invention:
The object of this invention is to obviate ihe above drawbacks.
To achieve the said objective this invention provides a field programmable logic device comprising at least two independently configurable embedded memory structures (201, 202) said at least two memory structures including:
a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set of available configuration depths, and a first set of available configuration widths, a second memory structure (202) with second configuration options of configurable configuration parameters including a second memory size, a second set of available configuration depths, and a second set of available configuration widths,
said memory structures (201, 202) being interconnected (505a, 505b, 508) to form a combined memory structure having a combined set of configuration parameters, characterized in that
said first and second configuration options are independently configurable and mutually exclusive in respect of at least one of said configurable parameters, said combined set of configuration parameters including at least one combined parameter comprised of the combination of mutually exclusive homologous parameters of said first (201) and second (202) memory structure for efficient memory utilization without redundancy.
The said memory structures are combined to form larger configurations through interconnection of dedicated memory routing tracks (505a, 505b) and horizontal routing channels (508).
The said dedicated memory routing tracks (505a, 505b) comprising plurality of bus based vertical tracks originating from memory IDs.
The horizontal routing channels (508) comprising several routing tracks.
The said dedicated memory routing tracks (505a, 505b) interact with the horizontal routing channels (508) through programmable switches (400).
A single set of dedicated memory routing tracks (505a, 505b) spans one or more memory blocks and a plurality of horizontal routing channels (508).
The upper and lower end of dedicated memory routing tracks (505a, 505b) are a set of bus based bi-directional programmable buffers (507) to connect different blocks of memory to form deeper and/or wider memories.
Since each memory structure (201, 202) supports only a subset of total configuration modes available, the size of the multiplexer at the input/output of said memories (201, 202) will be reduced thereby enhancing the speed of access to the memories.
The said memory structures (201, 202) are used independently or in combination to implement logic functions.
The said memory structures (201, 202) are multi-port.
The said memory structures (201, 202) are Read Only Memory (ROM), Random Access Memory (RAM), Content Addressable Memory (CAM), First In First Out (FIFO) structures.
The present invention also provides a method of making a field programmable logic device comprising at least two independently configurable embedded memory structures (201, 202) the method including the steps of:
providing a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set of available configuration depths, and a first set of available configuration widths,
providing a second memory structure (202) with second configuration options of configurable configuration parameters including a second memory size, a second set of available configuration depths, and a second set of available configuration widths,
interconnecting (505a, 505b, 508) said memory structures (201, 202) to form a combined memory structure having a combined set of configuration parameters, characterized in that the method further includes the steps of: making said first and second configuration options independently configurable and mutually exclusive in respect of at least one of said configurable parameters, and
including in said combined set of configuration parameters at least one combined parameter comprised of the combination of mutually exclusive homologous parameters of said first (201) and second (202) memory structure for efficient memory utilization without redundancy.
Brief Description of the drawings:
Figure 1 shows the memory structure according to the prior art consisting of only one type of embedded memory array
Figure 2 shows the arrangement according to present invention wherever two types of embedded memory arrays are provided
Figure 3 shows the example of the use of two different configurable memory structures to obtain memory of different width.
Figure 4 shows the implementation for obtaining 256 x 9 logical memory
Figure 5 shows the preferred method of memory to memory and memory to logic interaction.
Detailed Description of the invention:
It is proposed to provide two or more types of memory resources with the types being distinguishable by the configuration modes supported by them or their size or both.
For ease of understanding, at present consider only two types of memory resources. In one embodiment, the different memory structures can be distinguished both on the basis of the configuration modes supported by them and their sizes as shown in Fig 2. FIG2 represents the preferred type of Programmable Logic device that includes three types of programmable resources viz. 201, 202, 203. Component 201 represents programmable memory block with wider configurable data widths and/or larger core size with respect to component 202. Component 202 represents programmable memory block with smaller configurable data widths and/or smaller core size with respect to component 201. Component 203 represents
programmable logic blocks that can be any of a PLA or LUT based circuit to implement logic intensive circuits.
202 of FIG2 supports small memory requirements (memory size) with plurality of smaller configurable word sizes for example xl, x2, and x4. The smaller configurable memory arrays can be combined using dedicated (bus-based) as well as general routing resources to create wider or deeper memories. 201 of F1G2 supports large memory requirements (memory size) with plurality of larger configurable word sizes as x8, x16, and x32. The larger memory arrays can also be combined using separate dedicated (bus-based) as well as general routing resources to create wider or deeper memories.
Since each memory structure is supporting only a subset of the total configuration modes available, the size of the multiplexer at the input/output of the memories will be reduced. Reduced flexibility at each level enhances the speed of operation at both levels, though it does not affect the overall number of possible combinations of different word sizes available. As the configuration modes supported by both types of memory structures are mutually exclusive they do interact with each other and no separate routing resources between the two types of memory structures are needed.
As shown in F1G3, consider if the size of the smaller memory structure is 256 bits and that of the larger memory structure is 2Kbits implying that the smaller memory can implement any of 256x1, 128x2 or 64x4 and the larger can implement any of the 256x8, 128x16 or 64x32 then x9, xl8, x36 modes can also be easily realized as the memory depth in both the memory structures is the same. One of these types of implementation is illustrated in FIG4.
FIG4 shows one of the preferred ways to implement a 256x9 logical memory that may be required in some designs. In F1G4, one block of 201 memory and one block of 202 memories are combined to form a memory block of size 256x9 The block of 202 memory is configured in 256x1 mode. 256x1 mode means that this memory has 256 words of 1 bit each. To address 256 words, this memory requires 8 address lines 401, and its output data bus 403, is 1 bit wide. The block of 201 memory is configured in 256x8 mode. 256x8 mode means that this memory has 256 words of 8 bit each. To address 256 words, this memory requires 8 address lines 402, and its output data bus 404, is 8 bits wide. Now to create a 256x9 memory block, the 201 and 202 blocks are combined in the following manner. The address buses of 202
block and 201 block, i.e., 401 and 402 are shorted. The short connection is provided through routing segments and programmable connections (see FIG4). The output data buses of both the blocks together, i.e., 403 and 404 represent the data bus, 405 of 256x9 memory.
F1G5 shows a preferred way of memory to memory and memory to logic interaction scheme. The memory block (any of 202 or 201) interacts with logic blocks 203, and other memory blocks through dedicated memory routing tracks and horizontal routing channels. The dedicated memory routing tracks (505a & 505b) consist of plurality of bus-based vertical tracks (originating from memory I/Os) that interact with horizontal routing channels 508, through programmable switches, 400. The horizontal routing tracks in turn interact with logic blocks. The horizontal routing channels also consist of several routing tracks. The dedicated memory routing tracks interact with horizontal routing channels through programmable switches.
A single set of dedicated memory routing tracks spans one (or more) memory block and a plurality of horizontal routing channels (as shown in the FIG5). At the upper and the lower ends of dedicated memory routing tracks are a set of bus-based bi-directional programmable buffers 507, that help to connect different blocks of memories to form deeper and/or wider memories.
The connection box where dedicated memory routing tracks interact with horizontal routing channels is called Memory Logic Interface (506a & 506b). The interconnections between memory blocks and logic blocks are made possible with this Memory Logic Interface box. It is to be noted that the attached figure is only a representation of the case, in actual connections the number of address and data lines would be larger than shown in the figure. Also the number of tracks in horizontal channel, and the topology of switches in Memory Logic Interface box could be different.
In another embodiment of the invention, the different memory structures are distinguished on the basis of the configuration modes supported by them but have same size.
In another embodiment different memory structures are provided that are distinguished on the basis of their sizes but supporting same configuration modes.
Also, in another embodiment both or any one of the memories can be used in asynchronous ROM mode to implement substantial logic when the design does not require all the on-chip memory resources provided thus saving LUTs in all the cases considered above. The above explanation can be easily extended to more than two types of memory resources.

We claim:
1. A field programmable logic device comprising at least two independently
configurable embedded memory structures (201, 202) said at least two memory
structures comprising:
a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set of available configuration depths, and a first set of available configuration widths, a second memory structure (202) with second configuration options of configurable configuration parameters including a second memory size, a second set of available configuration depths, and a second set of available configuration widths,
said memory structures (201. 202) being interconnected (505a, 505b, 508) to form a combined memory structure having a combined set of configuration parameters, characterized in that
said first and second configuration options are independently configurable and mutually exclusive in respect of at least one of said configurable parameters, said combined set of configuration parameters including at least one combined parameter comprised of the combination of mutually exclusive homologous parameters of said first (201) and second (202) memory structure for efficient memory utilization without redundancy.
2. A field programmable logic device as claimed in claim 1, wherein said memory
structures are combined to form larger configurations through interconnection of
dedicated memory routing tracks (505a, 505b) and horizontal routing channels (508).
3. A field programmable logic device as claimed in claim 2, wherein said dedicated
memory routing tracks (505a, 505b) comprising plurality of bus based vertical tracks
originating from memory IOs.
4. A field programmable logic device as claimed in claim 2, wherein horizontal routing
channels (508) comprising several routing tracks.
5. A field programmable logic device as claimed in claim 2, wherein said dedicated
memory routing tracks (505a, 505b) interact with the horizontal routing channels
(508) through programmable switches (400).
6. A field programmable logic device as claimed in claim 2, wherein a single set of
dedicated memory routing tracks (505a, 505b) spans one or more memory blocks and
a plurality of horizontal routing channels (508).
7. A field programmable logic device as claimed in claim 2, wherein the upper and
lower end of dedicated memory routing tracks (505a, 505b) are a set of bus based bi
directional programmable buffers (507) to connect different blocks of memory to
form deeper and/or wider memories.
8. A field programmable logic device as claimed in claim 1, wherein since each memory
structure (201, 202) supports only a subset of total configuration modes available, the
size of the multiplexer at the input/output of said memories (201, 202) will be reduced
thereby enhancing the speed of access to the memories.
9. A field programmable logic device as claimed in claim 1, wherein said memory
structures (201, 202) are used independently or in combination to implement logic
functions.
10. A field programmable logic device as claimed in claim 1, wherein said memory
structures (201, 202) are multi-port.
11. A field programmable logic device as claimed in claim 1, wherein said memory
structures (201, 202) are Read Only Memory (ROM), Random Access Memory
(RAM), Content Addressable Memory (CAM), First In First Out (FIFO) structures.
12. A method of making a field programmable logic device comprising at least two
independently configurable embedded memory structures (201, 202) the method
comprising the steps of:
providing a first memory structure (201) with first configuration options of configurable configuration parameters including a first memory size, a first set
of available configuration depths, and a first set of available configuration
widths,
providing a second memory structure (202) with second configuration options
of configurable configuration parameters including a second memory size, a
second set of available configuration depths, and a second set of available
configuration widths,
interconnecting (505a, 505b, 508) said memory structures (201, 202) to form a
combined memory structure having a combined set of configuration
parameters, characterized in that the method further includes the steps of:
making said first and second configuration options independently configurable
and mutually exclusive in respect of at least one of said configurable
parameters, and
including in said combined set of configuration parameters at least one
combined parameter comprised of the combination of mutually exclusive
homologous parameters of said first (201) and second (202) memory structure
for efficient memory utilization without redundancy.
13, A field programmable logic device comprising at least two independently
configurable embedded memory structures substantially as herein described with
reference to and as illustrated in the accompanying drawings.
14. A method of making a field programmable logic device comprising at least two
independently configurable embedded memory structures substantially as herein
described with reference to and as illustrated in the accompanying drawings.

Documents:

728-del-2001-abstract.pdf

728-del-2001-claims cancelled.pdf

728-del-2001-claims.pdf

728-del-2001-complete specification (granted).pdf

728-del-2001-correspondence-others.pdf

728-del-2001-correspondence-po.pdf

728-del-2001-description (complete).pdf

728-del-2001-drawings.pdf

728-del-2001-form-1.pdf

728-del-2001-form-13.pdf

728-del-2001-form-18.pdf

728-del-2001-form-2.pdf

728-del-2001-form-3.pdf

728-del-2001-pa.pdf

728-del-2001-Petition thers-(21-06-2012).pdf

728-del-2001-petition-124.pdf

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Patent Number

249549

Indian Patent Application Number

728/DEL/2001

PG Journal Number

43/2011

Publication Date

28-Oct-2011

Grant Date

25-Oct-2011

Date of Filing

29-Jun-2001

Name of Patentee

STMICROELECTRONICS LTD.

Applicant Address

PLOT NO. 1, KNOWLEDGE PARK III, GREATER NOIDA -201308, UP. INDIA

Inventors:

#	Inventor's Name	Inventor's Address
1	ANURAG CHAUDHARY,	F-59A, MIG FLATS, HARI NAGAR NEW DELHI-11006 INDIA
2	MONINDER SING	14/149 SUBHASH NAGAR, NEW DELHI-110027

PCT International Classification Number

H03K 19/177

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA