Title of Invention

POWER SEMI-CONDUCTOR MODULE WITH REDUCED PARASITIC INDUCTANCES

Abstract A power semi-conductor module with a housing and along with it one or more half bridge circuitry arrangements arranged in it is suggested. Each half bridge circuit arrangement herein has a first (TOP) and a second (BOT) power switch, wherein each of these power switches consists if one power transistor and one allocated power diode (recovery diode). The power semi-conductor module has further one DC connection of positive polarity and one DC connection of negative polarity. Per half bridge circuit arrangement there are two AC connections electrically not in direct connection with each other. Each TOP transistor is connected with the power diode of the BOT switch and a first AC connection and every BOT transistor is connected with the power diode of the TOP switch and a second AC connection.
Full Text FORM 2
THE PATENT ACT 1970 (39 of 1970)
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
(See Section 10, and rule 13!
1. TITLE OF INVENTION
POWER SEMI-CONDUCTOR MODULE WITH REDUCED PARASITIC
INDUCTANCES

2. APPLICANT(S)
a) Name
b) Nationality
c) Address

SEMIKRON ELEKTRONIK GMBH & CO. KG
GERMAN Company
POSTFACH 820251,
902 53 NURNBERG,
GERMANY

3. PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in which it is to be performed : -

Description
A power semi-conductor module is introduced, wherein the parasitic inductances within the power semi-conductor module are reduced vis-a-vis standard power semi-conductor modules. Herein, power semi-conductor modules should be considered, whose internal circuitry is designed as half bridge circuit. Similarly, that kind of power semi-conductor modules are considered, whose internal circuitry is designed as a parallel circuit comprising of several half bridge circuits, these include, for example, full bridge circuits as well as 3-phase bridge circuits, or from a single parallel circuit made up of several suitable sub-circuits of half bridges. The wide ranging status of technology for this purpose is built up as example from the DE 39 37 045 Al and DE 100 37 533 CI.
In the DE 39 37 045 for a half bridge a circuitry for reducing the parasitic inductances in the DC supply lines has been described. Herein, both the DC supply cables are located close to each other, however, with the AC current supply line between positive and negative line, and are arranged at least partially parallel to each other. This effects a reduction of live current area of the neighboring arrangement of leads and, thereby a relatively low inductance of this feeder section.
In the DE 39 37 045 the aim of a minimum parasitic inductance is, however, not met due to two major reasons. First the DC connecting conductors are not arranged at minimum distance to each other, since here the AC connection conductor is arranged between both the DC connection conductors. Thus the area with live current in the area of DC connecting conductor is not minimal and, therefore, also the inductances for this area are not minimal. Secondly, the first and second power switches are arranged relatively wide from each other, which also increase the parasitic inductances.
The DE 100 37 533 CI reveals a more modern, very expensive, but also very efficient circuitry for the reduction of parasitic inductances. Herein all areas with live current within a power semiconductor module are minimized as far as possible. The disadvantage of this arrangement is the considerable design and production effort for a power semi-conductor modules.
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All power semi-conductor modules as per the described status of technology have per half bridge circuit one AC voltage output. This is disadvantageous to the extent that, if the external circuit of the power semi-conductor modules should be designed differently, as dependent of the fact, whether the current flows via the first (TOP) or the second (BOT) branch of the respective half bridge.
The base task for the invention is to introduce a power semi-conductor module, which has few parasitic inductances, is accessible to an easy manufacturing and allows an additional flexible circuit arrangement of the AC output.
The task is resolved in accordance to the invention through the measures of features of claims 1 and 2. Preferred design forms are described in the sub-claims.
The invention based power semi-conductor module has few parasitic inductances, however, based on design of individual component arrangement based on the deviation from the above said state of technology.
The power semi-conductor module itself has housing. In the first design, there is a single or multiple parallel half bridge circuitry arrangement. Each of these half bridge circuitry arrangements has a first (TOP) and a second (BOT) power switch, wherein each power switch consists of at least one power transistor and one allocated power diode of a so-called recovery type diode. The power semi-conductor module has further minimum one DC connection of positive polarity and one DC connection of m negative polarity. Based on the invention each half bridge circuitry arranged in the power semi-conductor module has at least two AC connections not electrically connected with each other in the inside of the power semi-conductor module.
The low parasitic inductances are reached in a way, that per half bridge circuitry arrangement the minimum one TOP transistor is connected with the at least one power diode allocated to the BOT switch with the AC connection allocated to this half bridge circuitry arrangement. Similarly per half bridge circuitry arrangement to which at least one BOT transistor with which at least one power diode of the TOP switch are connected with the second AC connection allocated to this half bridge circuitry arrangement.
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The deciding criterion for low parasitic inductances is, that during the commutation, the areas with live current are as small as possible. According to the state of technology, with respect to the TOP transistor whose allocated recovery diode is arranged next to it. During the commutation, for example, while switching-off the TOP switch, the current flows through the TOP transistor and then through the recovery diode allocated to the BOT switch. Similar, behavior can be observed also during switching off the BOT switch with the recovery diode of the TOP switch. Through the arrangement of the TOP transistor and the BOT recovery diode for a first AC connection and through the respective arrangement of the BOT transistor and the TOP recovery diode for a second AC connection, during a commutation process the area with live current is smaller than in the arrangement as per state of technology. Thus the parasitic inductances in the power semiconductor modules are reduced.
The division of an AC connection in AC connection one each allocated to the TOP and the BOT transistor continues to permit a flexible external wiring of the power semi-conductor module. Thus the wiring of the AC connection can be designed differently depending on, whether the current flows via the first (TOP) or the second (BOT) branch of the respective half bridge circuitry arrangement.
In another design, in the housing (32) several identical sub-circuits of a half bridge circuitry arrangement are arranged. Herein, a complete half bridge circuitry arrangement as described above consists of a first (TOP) and a second (BOT) power switch. The power semi-conductor module has at least one DC connection of positive polarity and at least one DC connection of negative polarity. Further, each sub-circuit within the scope of first design of this power semi-conductor module has at least one TOP transistor, one power diode of the BOT switch and one AC connection, wherein these components are connected with each other according to the circuit. Alternatively, a second design of this power semi-conductor module has at least one BOT transistor, one power diode of the TOP switch and one AC connection, wherein these components are connected with each other according to the circuit.
The inventive thought is explained in detail on the basis of design examples in the Fig. 1 to 4.
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Fig. 1 shows one power semi-conductor module each with one half or a 3-phase bridge circuitry arrangement as per the state of technology.
Fig. 2 shows an invention based power semi-conductor module with a half bridge circuitry arrangement.
Fig. 3 shows an invention based power semi-conductor module with a 3-phase bridge circuitry arrangement.
Fig. 4 shows another design of an invention based power semi-conductor module with a sub-circuit of a 3- phase bridge circuitry arrangement.
Fig. 1 shows schematically the state of technology of power semi-conductor modules with a half or 3-phase bridge circuitry arrangement. Fig. la shows schematically one power semi-conductor module with housing (30). In this are arranged one first (TOP) and one second (BOT) power switch. The respective power switches consist of at least one power transistor (10, 12), preferably an IGBT (insulated gate bipolar transistor), and at least one anti-parallel switched recovery diode (20, 22), wherein the respective transistors and allocated recovery diodes are arranged close to each other. The TOP switch is connected with one DC connection of positive polarity (40) and the BOT switch is connected with one DC connection of negative polarity (50). Both the switches continue to be switched with each other and with an AC connection (60).
Fig. 1 b shows another power semi-conductor module with a housing. In this are arranged parallel three half bridge circuitry arrangements and form a 3- phase bridge circuit. Each of these half bridges is designed like the description to Fig. la. The respective TOP switches continue to be connected with the DC connection of positive polarity (40) and the respective BOT switch with the DC connection of negative polarity (50). Each half bridge circuit is connected with a separate AC connection (60 a, b, c) originating from the housing (30).
Fig. 2 shows an invention based power semi-conductor module with a half bridge circuitry arrangement. Fig. 2a shows herein schematically a power semi-conductor module with a housing (30) and a half bridge circuitry arrangement. Herein the TOP switch consists of two parallel switched TOP transistors (10), preferably IGBTs, and two allocated and similarly parallel
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switched recovery diodes (20). Analogous to this, the BOT switch consists of two parallel switched BOT transistors (12) and two allocated similarly parallel switched recovery diodes (22). The recovery diodes of each switch are arranged here space-wise in the other switch respectively.
It is especially preferred, although the arrangement of components of half bridge circuitry arrangement already suggests to arrange close to each other the TOP transistors (10) and the recovery diodes (22) of the BOT switch, like the BOT transistors (12) and the recovery diodes (20) of the TOP switch. This reduces further the parasitic inductances of the power semiconductor module.
The inputs (collectors) of the TOP transistors (10) are connected with a first DC connection of positive polarity (40) of the housing (30). The outputs (Emitter) are connected with the first AC output (62) of the housing and with the cathodes of the recovery diodes (22) of the BOT switch. The anodes of the recovery diodes (22) are connected with the first DC connection of negative polarity (50) of the housing (30). Analogue to this, the arrangement is built up from BOT transistors (12), recovery diodes (20) of the TOP switch and the second AC connection (64) of the housing (30). Through direct external connection of both the AC connections (62, 64), the identical functionality of a power semi-conductor module is achieved according to the state of technology represented in Fig. la.
Fig. 2b shows another design of an invention based power semi-conductor module with a half bridge circuitry arrangement. The arrangement of components of half bridge circuit is identical like the one shown in Fig. 2a. As against this, the power semi-conductor module has only one external DC connection of positive (40) or negative (50) polarity each. Further, it is represented here, that each of the first (62) and the second (64) AC output is wired with a coil (82, 84). This kind of wiring is shown, as an example, for a bridge short circuit to prevent damage to the respective switch, because the short circuit current through the coils - based on law of induction -rises slowly and thus a control circuit can switch-off the respective circuit much before their destruction.
Fig. 3 shows an invention based power semi-conductor module with a 3- phase bridge circuitry arrangement. Schematically represented here is a power semi-conductor module with a housing (30) and a 3-phase bridge circuit arrangement. This consists of a parallel arrangement of three half
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bridge circuitry arrangements like those described in the Fig. 2. The inputs (collectors) of all TOP transistors (10 a, b, e) of all three half bridges are connected with the DC connection of positive N polarity (40) of the housing (30). The outputs (Emitter) are connected per half bridge with one each of first AC output (62 a, b, c) of the housing and with the cathodes of the recovery diodes (22 a, b, c) of the BOT switch. The anodes of recovery diodes (22 a, b, c) are connected with the DC connection of negative polarity (50) of the housing. Analogue to this is the arrangement of BOT transistors (12 a, b, c), recovery diodes (20 a, b, c) of the TOP switch and per half bridge of second AC connection (64 a, b, c) of the housing.
Fig. 4 shows another design of an invention based power semi-conductor module. Herein are represented in a first housing (32a) a first design and in a second housing a second design. The first design has a housing (32a) with first sub-circuits of a 3- phase bridge circuitry arrangement, wherein this consists of a parallel arrangement of the TOP transistor (10 a, be) with the power diode (22 a, b, c) of the BOT switch and a separate AC connection (62 a, b, c). The second design has a second housing (32b) with the second sub-circuits of a 3-phase bridge circuitry arrangement arranged in it, wherein this consists of a parallel arrangement of the BOT transistor (12 a, b, c) with the power diode (20 a, b, c) of the TOP switch and a separate AC connection (64 a, b, c).
A reluctance motor (84) represented here has three rotary windings. Herein, the first connection of the first rotor winding is connected with the AC output (62a) of the first sub-circuit of the first design of the invention based power semi-conductor module. The second connection of the first rotary winding is connected with the AC output (64a) of the first sub-circuit of the second design of the invention based power semi-conductor module. In analogical way, both the other rotary windings of the reluctance motor (84) are connected with the second and third sub-circuits of the power semi-conductor module.
Through the invention based buildup of both these designs of the power semi-conductor module it is possible to arrange each of the components of a half bridge circuit involved in a commutation process close to each other and thereby having low parasitic inductances in a common housing (32 a. b) and to ensure a suitable connection to a motor, here to a reluctance motor (84).
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We Claim:
1. Power semi-conductor module with a housing (30) and herein arranged one or more half bridge circuitry arrangements with first (TOP) and a second (BOT) power switch per half bridge circuitry arrangements, wherein every power switch consists of at least one power transistor (10, 12) and at least one allocated power diode (recovery diode) (20, 22), And the power semi-conductor module has at least one DC connection (40) of positive polarity, at least one DC connection (50) of negative polarity and per half bridge circuitry arrangement at least two AC connections (62, 64) electrically not directly connected with each other, wherein at least one TOP transistor (10) is connected with at least one power diode (22) of the BOT switch and the first AC connection (62) and the minimum one BOT transistor (12) is connected with at least one power diode (20) of the TOP switch and second AC connection (64).
2. Power semi-conductor module with a housing (32 a, b) and herein a multiple of e parallel arranged identical sub-circuits of half bridge circuit arrangements, wherein a half bridge circuit arrangement consists of a first (TOP) and a second (BOT) power switch and, every power switch consists of at least one power transistor (10, 12) and at least one allocated power diode (recovery diode) (20, 22), and the power semi-conductor module has at least one DC connection (40) of positive polarity and at least one DC connection (50) of negative polarity, wherein every sub-circuit of half bridge circuit consists of at least one TOP transistor (10) with at least one power diode (22) of the BOT switch and one AC connection (62), which are connected with each other according to circuit or which consists of at least one BOT transistor (12) with at least one power diode (20) of the TOP switch and one AC connection (64), which are connected with each other in accordance to the circuit.
3. Power semi-conductor module as per Claim 1 or 2, wherein all TOP transistors (10) are arranged close to each other and to the power diode (22) of the BOT switch or all BOT transistors (12) are arranged close to each other and to the power diode (20) of the TOP switch.
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4. Power semi-conductor module as per Claim 1 or 2, wherein the transistors (10, 12) are designed as IGBTs (insulated gate bipolar transistor).








Dated this 18th day of November, 2005


HIRAL CHANDRAKANT JOSHI
AGENT FOR
SEMIKRON ELEKTRONIK GMBH & CO. KG.
9

ABSTRACT
A power semi-conductor module with a housing and along with it one or more half bridge circuitry arrangements arranged in it is suggested. Each half bridge circuit arrangement herein has a first (TOP) and a second (BOT) power switch, wherein each of these power switches consists of one power transistor and one allocated power diode (recovery diode). The power semi-conductor module has further one DC connection of positive polarity and one DC connection of negative polarity. Per half bridge circuit arrangement there are two AC connections electrically not in direct connection with each other. Each TOP transistor is connected with the power diode of the BOT switch and a first AC connection and every BOT transistor is connected with the power diode of the TOP switch and a second AC connection.
(Fig. 3)
To
The Controller of Patents,
The Patent Office,
Mumbai.
10

Documents:

1443-mum-2005-abstract(18-11-2005).pdf

1443-mum-2005-abstract(granted)-(17-9-2010).pdf

1443-mum-2005-abstract.doc

1443-mum-2005-abstract.pdf

1443-mum-2005-cancelled pages(2-8-2010).pdf

1443-mum-2005-claims(granted)-(17-9-2010).pdf

1443-mum-2005-claims.doc

1443-mum-2005-claims.pdf

1443-mum-2005-correspondence(1-12-2005).pdf

1443-MUM-2005-CORRESPONDENCE(2-8-2010).pdf

1443-mum-2005-correspondence(ipo)-(17-9-2010).pdf

1443-mum-2005-correspondence-received-1801105.pdf

1443-mum-2005-deccription (complete).pdf

1443-mum-2005-description(granted)-(17-9-2010).pdf

1443-mum-2005-drawing(18-11-2005).pdf

1443-MUM-2005-DRAWING(2-8-2010).pdf

1443-mum-2005-drawing(granted)-(17-9-2010).pdf

1443-mum-2005-drawings.pdf

1443-mum-2005-form 1(18-11-2005).pdf

1443-MUM-2005-FORM 1(2-8-2010).pdf

1443-mum-2005-form 18(5-9-2007).pdf

1443-mum-2005-form 2(granted)-(17-9-2010).pdf

1443-mum-2005-form 2(title page)-(18-11-2005).pdf

1443-MUM-2005-FORM 2(TITLE PAGE)-(2-8-2010).pdf

1443-mum-2005-form 2(title page)-(granted)-(17-9-2010).pdf

1443-mum-2005-form 3(18-11-2005).pdf

1443-MUM-2005-FORM 3(2-8-2010).pdf

1443-mum-2005-form 5(18-11-2005).pdf

1443-MUM-2005-FORM 5(2-8-2010).pdf

1443-mum-2005-form-1.pdf

1443-mum-2005-form-2.doc

1443-mum-2005-form-2.pdf

1443-mum-2005-form-26.pdf

1443-mum-2005-form-3.pdf

1443-mum-2005-form-5.pdf

1443-MUM-2005-GENERAL POWER OF ATTORNEY(2-8-2010).pdf

1443-MUM-2005-PETITION UNDER RULE 137(2-8-2010).pdf

1443-MUM-2005-REPLY TO EXAMINATION REPORT(2-8-2010).pdf

abstract1.jpg


Patent Number 242894
Indian Patent Application Number 1443/MUM/2005
PG Journal Number 39/2010
Publication Date 24-Sep-2010
Grant Date 17-Sep-2010
Date of Filing 18-Nov-2005
Name of Patentee SEMIKRON ELEKTRONIK GMBH & CO. KG
Applicant Address POSTFACH 820251, 90253 NURNBERG,
Inventors:
# Inventor's Name Inventor's Address
1 DEJAN SCHREIBER Pirckheimerstr. 49, 90408 Nurnberg
2 HEINRICH HEILBRONNER BIRKENWEG 6, 90547 STEIN
PCT International Classification Number H01L25/07
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 102004059313.2 2004-12-09 Germany