Title of Invention	"AN INTERCONNECT STRUCTURE"
Abstract	The present invention provides an interconnect structure (800) comprising: first and second bumps (112A, 112B); a first metal layer (202) coupled to the first and second bumps (112A, 112B), the first metal layer (202) being formed in a space substantially enclosed by a first dielectric layer (ILD), the first dielectric layer (ILD) having a substantially planar top surface, the first metal layer (202) being coupled to a top metal layer (160) of an integrated circuit die (150), the first metal layer (202) being operative to transfer current (250) from the first and second bumps (112A, 112B) to the top metal layer (160) of the integrated circuit die (150); a second metal layer (212) over the first metal layer (202), the second metal layer (212) being coupled to the first bump (112A), a third bump (230) and the first metal layer (202), the second metal layer (212) being operative to transfer current (250) from the first (112A) and third (230) bumps to the first metal layer (202), which is operative to transfer current to the top metal layer (160) of the integrated circuit die (150); and wherein traces of the second metal layer (212) are orthogonal to traces of the first metal layer (202). [FIG 8A]

Title of Invention

"AN INTERCONNECT STRUCTURE"

Abstract

The present invention provides an interconnect structure (800) comprising: first and second bumps (112A, 112B); a first metal layer (202) coupled to the first and second bumps (112A, 112B), the first metal layer (202) being formed in a space substantially enclosed by a first dielectric layer (ILD), the first dielectric layer (ILD) having a substantially planar top surface, the first metal layer (202) being coupled to a top metal layer (160) of an integrated circuit die (150), the first metal layer (202) being operative to transfer current (250) from the first and second bumps (112A, 112B) to the top metal layer (160) of the integrated circuit die (150); a second metal layer (212) over the first metal layer (202), the second metal layer (212) being coupled to the first bump (112A), a third bump (230) and the first metal layer (202), the second metal layer (212) being operative to transfer current (250) from the first (112A) and third (230) bumps to the first metal layer (202), which is operative to transfer current to the top metal layer (160) of the integrated circuit die (150); and wherein traces of the second metal layer (212) are orthogonal to traces of the first metal layer (202). [FIG 8A]

Full Text	BACKGROUND [0002] Each generation of complementary metal oxide semiconductor (CMOS) circuits usable in a microprocessor may have more transistors operating at lower voltages and higher frequencies. Since the resistance of transistors in each new generation may decrease more than voltage, and transistors may leak more current, CMOS circuits may demand more current. Higher current may be needed to pass from a substrate through a solder bump and a Controlled Collapse Chip Connection (C4) bump to a die. Each C4 bump may only be able to handle a limited amount of current due to electron migration failure. C4 bumps are known in the semiconductor industry as connections which provide current between a die and a substrate. WE CLAIM: 1. An interconnect structure (800) comprising: first and second bumps (112A, 112B); a first metal layer (202) coupled to the first and second bumps (112A, 112B), the first metal layer (202) being formed in a space substantially enclosed by a first dielectric layer (ILD), the first dielectric layer (ILD) having a substantially planar top surface, the first metal layer (202) being coupled to a top metal layer (160) of an integrated circuit die (150), the first metal layer (202) being operative to transfer current (250) from the first and second bumps (112A, 112B) to the top metal layer (160) of the integrated circuit die (150); a second metal layer (212) over the first metal layer (202), the second metal layer (212) being coupled to the first bump (112A), a third bump (230) and the first metal layer (202), the second metal layer (212) being operative to transfer current (250) from the first (112A) and third (230) bumps to the first metal layer (202), which is operative to transfer current to the top metal layer (160) of the integrated circuit die (150); and wherein traces of the second metal layer (212) are orthogonal to traces of first metal layer (202). 2. The interconnect structure as claimed in Claim 1, wherein the first dielectric layer (206) comprises a self-planarizing, photodefinable polymer or a self-planarizing, non-photodefinable polymer. 3. The interconnect structure as claimed in Claim 1, wherein the first dielectric layer (206) is spray coated. 4. The interconnect structure as claimed in Claim 1, wherein the first dielectric layer (206) is laminated. 5. The interconnect structure as claimed in Claim 1, wherein die first metal layer (202) is 10 to 50 microns thick. 6. The interconnect structure as claimed in Claim 1, wherein the first metal layer (202) comprises electroplated copper. 7. The interconnect structure as claimed in Claim 1, wherein the first metal layer (202) is deposited in vias (209) over a first base layer metallization (208), which is deposited over the top metal layer (206) of the integrated circuit die (150). 8. A method for forming an interconnect structure as claimed in any preceding claim, said method comprising: forming a first metal layer over a first base layer metallization, the first base layer metallization contacting a top metal layer of an integrated circuit die; forming a first substantially planar dielectric layer over the first metal layer; forming vias in the first dielectric layer; forming a second base layer metallization in the vias of the first dielectric layer; forming bumps over the second base layer metallization, the top metal layer being coupled to the first metal layer, the first metal layer being operative to transfer current from the bumps to the top metal layer of the integrated circuit die; and forming a second metal layer after forming the first metal layer and before forming the bumps, the second metal layer being coupled to the adeast two bumps and the first metal layer, the second metal layer operative to transfer current from the at least two bumps to the first metal layer, which is operative to transfer current to the top metal layer of the integrated circuit die, wherein traces of the second metal layer are orthogonal to traces of first metal layer. 9. The method as claimed in Claim 8, wherein forming a first substantially planar dielectric layer comprises spray coating a dielectric material. 10. The method as claimed in Claim 8, wherein forming a first substantially planar dielectric layer comprises rolling and pressing a lamination material. 11. The method as claimed in Claim 8, wherein forming the first metal layer comprises forming a 10 to 50-micron thick metal layer. 12. The method as claimed in Claim 8, wherein forming the first metal layer over the first base layer metallization is done by electroplating copper to the first base layer metallization. 13. The method as claimed in Claim 8, wherein said forming a first dielectric layer uses a self-planarizing, photodefinable polymer or a self-planarizing, non-photodefinable polymer. 14. The method as claimed in Claim 8, wherein the first metal layer has a height of more than 40 microns above the surface, the first metal layer contacting a top metal layer of an integrated circuit die under the surface. 15. The method as claimed in Claim 14, wherein forming the substantially planar dielectric layer comprises spray coating a dielectric material around and over the metal structures. 16. The method as claimed in Claim 14, wherein forming the substantially planar dielectric layer comprises moving a sprayer to spray coat a dielectric material around and over the metal structures. 17. The method as claimed in Claim 14, wherein forming the substantially planar dielectric layer comprises rolling and pressing a lamination material around and over the metal structures. 18. An interconnect structure (800) as claimed in claims 1 to 7 comprising: first and second bumps (112A, 112B); a first metal layer (202) coupled to the first and second bumps (112A, 112B), the first metal layer (202) being formed in a trench of a dielectric layer (ILD), the first metal layer (202) being coupled to a top metal layer (160) of an integrated circuit die (150), the first metal layer (202) being adapted to transfer current (250) from the first and second bumps (112A, 112B) to the top metal layer (160) of the integrated circuit die (150); and a second metal layer (212) over the first metal layer (202), the second metal layer (212) being coupled to the first bump (112A), a third bump (230), and the first metal layer (202), the second metal layer (212) being adapted to transfer current from the first (112A) and third (230) bumps to the first metal layer (202), which is adapted to transfer current to the top metal layer (160) of the integrated circuit die (150); wherein traces of the second metal layer (212) are orthogonal to traces of the first metal layer (202). 19. The interconnect structure as claimed in Claim 18, wherein the first and second bumps (112A, 112B) are Controlled Collapse Chip Connection bumps. 20. The interconnect structure as claimed in Claim 18, wherein the first and second bumps (112A, 112B) are coupled to first and second solder bumps of a substrate. 21. The interconnect structure as claimed in Claim 18, wherein the first metal layer is 10 to 50 microns thick. 22. The interconnect structure as claimed in Claim 18, wherein the first metal layer comprises electroplated copper. 23. The interconnect structure as claimed in Claim 18, wherein the first metal layer is deposited in vias over a first base layer metallization, which is deposited over the top metal layer of the integrated circuit die. 24. The interconnect structure as claimed in Claim 18, wherein a first dielectric layer encloses the first metal layer. 25. The interconnect structure as claimed in Claim 24, wherein the first dielectric layer comprises a self-planarizing, photodefinable polymer or a self-planarizing, non-photo definable polymer. 26. The interconnect structure as claimed in Claim 18, wherein diffusion barriers are provided over and on sides of the first metal layer. 27. A method for forming an interconnect structure as claimed in any of claims 18 to 26, said method comprising: forming a first metal layer over a first base layer metallization, the first base layer metallization contacting a top metal layer of an integrated circuit die; forming a first dielectric layer over the first metal layer; forming vias in the first dielectric layer; forming a second base layer metallization in the vias of the first dielectric layer; forming bumps over the second base layer metallization, the top metal layer being coupled to the first metal layer, the first metal layer being adapted to transfer current from the bumps to the top metal layer of the integrated circuit die, and forming a second metal layer after forming the first metal layer and before forming the bumps, the second metal layer being coupled to the at least two bumps and the first metal layer, the second metal layer adapted to transfer current from the at least two bumps to the first metal layer, which is adapted to transfer current to the top metal layer of the integrated circuit die, wherein traces of the second metal layer are orthogonal to traces of first metal layer. 28. The method as claimed in Claim 27, wherein the first and second bumps are Controlled Collapse Chip Connection bumps. 29. The method as claimed in Claim 27, wherein the first metal layer is about 10 to 50 microns thick. 30. The method as claimed in Claim 27, wherein forming the first metal layer over first base layer metallization comprises electroplating copper to the first base layer metallization. 31. The method as claimed in Claim 27, comprising attaching the bumps to solder bumps of a substrate. 32. The method as claimed in Claim 27, comprising forming the first base layer metallization in vias of a polyimide layer. 33. The method as claimed in Claim 27, comprising forming the first base layer metallization in vias of a benzocyclobutene layer. 34. The method as claimed in Claim 27, comprising forming the first base layer metallization in vias of an epoxy layer. 35. The method as claimed in Claim 27, wherein said forming a first dielectric layer uses a self-planarizing, photodefinable polymer or a self-planarizing, non-photodefinable polymer. 36. The method as claimed in Claim 27, comprising forming diffusion barriers over and on sides of the first metal layer.

Full Text

BACKGROUND
[0002] Each generation of complementary metal oxide semiconductor (CMOS) circuits usable in a microprocessor may have more transistors operating at lower voltages and higher frequencies. Since the resistance of transistors in each new generation may decrease more than voltage, and transistors may leak more current, CMOS circuits may demand more current. Higher current may be needed to pass from a substrate through a solder bump and a Controlled Collapse Chip Connection (C4) bump to a die. Each C4 bump may only be able to handle a limited amount of current due to electron migration failure. C4 bumps are known in the semiconductor industry as connections which provide current between a die and a substrate.

WE CLAIM:
1. An interconnect structure (800) comprising:
first and second bumps (112A, 112B);
a first metal layer (202) coupled to the first and second bumps (112A, 112B), the first metal layer (202) being formed in a space substantially enclosed by a first dielectric layer (ILD), the first dielectric layer (ILD) having a substantially planar top surface, the first metal layer (202) being coupled to a top metal layer (160) of an integrated circuit die (150), the first metal layer (202) being operative to transfer current (250) from the first and second bumps (112A, 112B) to the top metal layer (160) of the integrated circuit die (150);
a second metal layer (212) over the first metal layer (202), the second metal layer (212) being coupled to the first bump (112A), a third bump (230) and the first metal layer (202), the second metal layer (212) being operative to transfer current (250) from the first (112A) and third (230) bumps to the first metal layer (202), which is operative to transfer current to the top metal layer (160) of the integrated circuit die (150); and
wherein traces of the second metal layer (212) are orthogonal to traces of first metal layer (202).
2. The interconnect structure as claimed in Claim 1, wherein the first dielectric layer (206) comprises a self-planarizing, photodefinable polymer or a self-planarizing, non-photodefinable polymer.
3. The interconnect structure as claimed in Claim 1, wherein the first dielectric layer (206) is spray coated.
4. The interconnect structure as claimed in Claim 1, wherein the first dielectric layer (206) is laminated.
5. The interconnect structure as claimed in Claim 1, wherein die first metal layer (202) is 10 to 50 microns thick.
6. The interconnect structure as claimed in Claim 1, wherein the first metal layer (202) comprises electroplated copper.
7. The interconnect structure as claimed in Claim 1, wherein the first metal layer (202) is deposited in vias (209) over a first base layer metallization (208), which is deposited over the top metal layer (206) of the integrated circuit die (150).
8. A method for forming an interconnect structure as claimed in any preceding claim, said method comprising:
forming a first metal layer over a first base layer metallization, the first base layer metallization contacting a top metal layer of an integrated circuit die;
forming a first substantially planar dielectric layer over the first metal layer;
forming vias in the first dielectric layer;
forming a second base layer metallization in the vias of the first dielectric layer;
forming bumps over the second base layer metallization, the top metal layer being coupled to the first metal layer, the first metal layer being operative to transfer current from the bumps to the top metal layer of the integrated circuit die; and
forming a second metal layer after forming the first metal layer and before forming the bumps, the second metal layer being coupled to the adeast two bumps and the first metal layer, the second metal layer operative to transfer current from the at least two bumps to the first metal layer, which is operative to transfer current to the top metal layer of the integrated circuit die,
wherein traces of the second metal layer are orthogonal to traces of first metal layer.
9. The method as claimed in Claim 8, wherein forming a first substantially planar dielectric layer comprises spray coating a dielectric material.
10. The method as claimed in Claim 8, wherein forming a first substantially planar dielectric layer comprises rolling and pressing a lamination material.
11. The method as claimed in Claim 8, wherein forming the first metal layer comprises forming a 10 to 50-micron thick metal layer.
12. The method as claimed in Claim 8, wherein forming the first metal layer over the first base layer metallization is done by electroplating copper to the first base layer metallization.
13. The method as claimed in Claim 8, wherein said forming a first dielectric layer uses a self-planarizing, photodefinable polymer or a self-planarizing, non-photodefinable polymer.
14. The method as claimed in Claim 8, wherein the first metal layer has a height of more than 40 microns above the surface, the first metal layer contacting a top metal layer of an integrated circuit die under the surface.
15. The method as claimed in Claim 14, wherein forming the substantially planar dielectric layer comprises spray coating a dielectric material around and over the metal structures.
16. The method as claimed in Claim 14, wherein forming the substantially planar dielectric layer comprises moving a sprayer to spray coat a dielectric material around and over the metal structures.
17. The method as claimed in Claim 14, wherein forming the substantially planar dielectric layer comprises rolling and pressing a lamination material around and over the metal structures.
18. An interconnect structure (800) as claimed in claims 1 to 7 comprising:
first and second bumps (112A, 112B);
a first metal layer (202) coupled to the first and second bumps (112A, 112B), the first metal layer (202) being formed in a trench of a dielectric layer (ILD), the first metal layer (202) being coupled to a top metal layer (160) of an integrated circuit die (150), the first metal layer (202) being adapted to transfer current (250) from the first and second bumps (112A, 112B) to the top metal layer (160) of the integrated circuit die (150); and
a second metal layer (212) over the first metal layer (202), the second metal layer (212) being coupled to the first bump (112A), a third bump (230), and the first metal layer (202), the second metal layer (212) being adapted to transfer current from the first (112A) and third (230) bumps to the first metal layer (202), which is adapted to transfer current to the top metal layer (160) of the integrated circuit die (150);
wherein traces of the second metal layer (212) are orthogonal to traces of the first metal layer (202).
19. The interconnect structure as claimed in Claim 18, wherein the first and second
bumps (112A, 112B) are Controlled Collapse Chip Connection bumps.
20. The interconnect structure as claimed in Claim 18, wherein the first and second
bumps (112A, 112B) are coupled to first and second solder bumps of a substrate.
21. The interconnect structure as claimed in Claim 18, wherein the first metal layer is 10
to 50 microns thick.
22. The interconnect structure as claimed in Claim 18, wherein the first metal layer comprises electroplated copper.
23. The interconnect structure as claimed in Claim 18, wherein the first metal layer is deposited in vias over a first base layer metallization, which is deposited over the top metal layer of the integrated circuit die.
24. The interconnect structure as claimed in Claim 18, wherein a first dielectric layer encloses the first metal layer.
25. The interconnect structure as claimed in Claim 24, wherein the first dielectric layer comprises a self-planarizing, photodefinable polymer or a self-planarizing, non-photo definable polymer.
26. The interconnect structure as claimed in Claim 18, wherein diffusion barriers are provided over and on sides of the first metal layer.
27. A method for forming an interconnect structure as claimed in any of claims 18 to 26, said method comprising:
forming a first metal layer over a first base layer metallization, the first base layer metallization contacting a top metal layer of an integrated circuit die;
forming a first dielectric layer over the first metal layer;
forming vias in the first dielectric layer;
forming a second base layer metallization in the vias of the first dielectric layer;
forming bumps over the second base layer metallization, the top metal layer being coupled to the first metal layer, the first metal layer being adapted to transfer current from the bumps to the top metal layer of the integrated circuit die, and
forming a second metal layer after forming the first metal layer and before forming the bumps, the second metal layer being coupled to the at least two bumps and the first metal layer, the second metal layer adapted to transfer current from the at least two bumps to
the first metal layer, which is adapted to transfer current to the top metal layer of the integrated circuit die,
wherein traces of the second metal layer are orthogonal to traces of first metal layer.
28. The method as claimed in Claim 27, wherein the first and second bumps are Controlled Collapse Chip Connection bumps.
29. The method as claimed in Claim 27, wherein the first metal layer is about 10 to 50 microns thick.
30. The method as claimed in Claim 27, wherein forming the first metal layer over first base layer metallization comprises electroplating copper to the first base layer metallization.
31. The method as claimed in Claim 27, comprising attaching the bumps to solder bumps of a substrate.
32. The method as claimed in Claim 27, comprising forming the first base layer metallization in vias of a polyimide layer.
33. The method as claimed in Claim 27, comprising forming the first base layer metallization in vias of a benzocyclobutene layer.
34. The method as claimed in Claim 27, comprising forming the first base layer metallization in vias of an epoxy layer.
35. The method as claimed in Claim 27, wherein said forming a first dielectric layer uses a self-planarizing, photodefinable polymer or a self-planarizing, non-photodefinable polymer.
36. The method as claimed in Claim 27, comprising forming diffusion barriers over and on sides of the first metal layer.

Documents:

1068-DELNP-2006-Abstract-(15-09-2009).pdf

1068-DELNP-2006-Abstract-(25-02-2010).pdf

1068-delnp-2006-abstract.pdf

1068-DELNP-2006-Claims-(15-09-2009).pdf

1068-DELNP-2006-Claims-(25-02-2010).pdf

1068-delnp-2006-claims.pdf

1068-DELNP-2006-Correspondence-Others (05-02-2010).pdf

1068-delnp-2006-Correspondence-Others-(03-09-2009).pdf

1068-DELNP-2006-Correspondence-Others-(15-09-2009).pdf

1068-DELNP-2006-Correspondence-Others-(20-08-2009).pdf

1068-DELNP-2006-Correspondence-Others-(24-02-2010).pdf

1068-DELNP-2006-Correspondence-Others-(25-02-2010).pdf

1068-delnp-2006-correspondence-others.pdf

1068-delnp-2006-correspondence-others1.pdf

1068-DELNP-2006-Description (Complete)-(15-09-2009).pdf

1068-DELNP-2006-Description (Complete)-(25-02-2010).pdf

1068-delnp-2006-description (complete).pdf

1068-DELNP-2006-Drawings-(15-09-2009).pdf

1068-delnp-2006-drawings.pdf

1068-DELNP-2006-Form-1-(15-09-2009).pdf

1068-DELNP-2006-Form-1-(25-02-2010).pdf

1068-delnp-2006-form-1.pdf

1068-delnp-2006-form-18.pdf

1068-DELNP-2006-Form-2-(15-09-2009).pdf

1068-DELNP-2006-Form-2-(25-02-2010).pdf

1068-delnp-2006-form-2.pdf

1068-DELNP-2006-Form-3-(20-08-2009).pdf

1068-delnp-2006-form-3.pdf

1068-delnp-2006-form-5.pdf

1068-delnp-2006-gpa.pdf

1068-delnp-2006-pct-210.pdf

1068-delnp-2006-Petition-137-(03-09-2009).pdf

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Patent Number

242775

Indian Patent Application Number

1068/DELNP/2006

PG Journal Number

38/2010

Publication Date

17-Sep-2010

Grant Date

09-Sep-2010

Date of Filing

28-Feb-2006

Name of Patentee

INTEL CORPORATION

Applicant Address

2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CA 94052, UNITED STATES OF AMERICA

Inventors:

#	Inventor's Name	Inventor's Address
1	MARTELL, ROBERT	14813 NW BENJAMIN COURT, PORTLAND, OR 97229, UNITED STATES OF AMERICA.
2	KIM, SARAH	5584 NW 149th COURT, PORTLAND, OR 97229, UNITED STATES OF AMERICA.
3	AYERS, DAVID	37884 MENARD COURT, FREMONT, CA 94536, UNITED STATES OF AMERICA.
4	MOON, PETER	4901 SW 26th DRIVE, PORTLAND, OR 97201, UNITED STATES OF AMERICA.
5	LIST, RICHARD	16675 SW IVY GLENN STREET, BEAVERTON, OR 97007, UNITED STATES OF AMERICA.
6	TOWLE, STEVEN	301 WEST DESERT FLOWER LANE, PHONIX AZ 85045, UNITED STATES OF AMERICA.
7	LEE, KEVIN	7793 SW 172nd PLACE, BEAVERTON, OR 97007, UNITED STATES OF AMERICA.

PCT International Classification Number

H01L 21/00

PCT International Application Number

PCT/US2004/028949

PCT International Filing date

2004-09-03

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	10/659,044	2003-09-09	U.S.A.
2	10/745,059	2003-12-22	U.S.A.