Title of Invention

"AN APPARATUS FOR PROVIDING RESISTANCE TO SINGLE EVENT UPSET TO PULSE WIDTH MODULATOR INTEGRATED CIRCUIT"

Abstract A circuit for use with a pulse width modulated integrated circuit (PWM IC) having a soft-start reset function comprising a diode (CR1) having a first terminal connected to a soft-start reset terminal of the integrated circuit, a voltage divider (R1, R2) coupled between a voltage reference and a common terminal for the integrated circuit, the diode having a second terminal coupled to a tap of the voltage divider and a soft-start capacitor (C1) coupled between the second terminal of the diode and the common terminal whereby upon power startup of the integrated circuit, the soft-start capacitor is charged by the tap of the voltage divider and wherein in the event of a single event upset condition, when the soft-start reset terminal of the inte...
Full Text The present invention provides an apparatus for providing resistance to single event upset to pulse width modulator integrated circuit.
BACKGROUND OF THE INVENTION
Modern DC to DC converters and switching power supplies usually use commercial Pulse Width Modulator Integrated Circuits (PWM ICs) to significantly reduce circuit complexity and total parts count. These PWM ICs generally include a soft-start feature that slowly charges an external capacitor to control the start-up rate of the switching power supply. Under various fault conditions, the PWM 1C may discharge the soft-start capacitor and initialize a power supply restart to protect both the power supply and load from overstress caused by the fault. This discharge mechanism makes commercial PWM ICs unsuitable for space applications (i.e., satellites, planetary probes, International Space Station, etc.) because of the potential for Single Event Upset (SEU).
SEU is caused by energetic particles commonly encountered in the space environment. These energetic particles can inadvertently turn on semiconductor junctions and cause an undesirable change in the operation of electronic devices and systems. An SEU of the PWM 1C soft-start circuit can cause temporary interruption of the power supply output, thus affecting any electronic systems that
comprise the power supply load. Therefore, many power supplies and DC to DC converters intended for use in space applications utilize PWM circuits composed of many discrete components arranged in such a way as to eliminate the possibility of SEU. This increases the total component count and circuit complexity relative to a comparable design utilizing a PWM 1C. The higher component count and circuit complexity generally has a negative impact on the overall power supply reliability.
Figure 1 illustrates a conventional non-latching implementation of a soft-start reset mechanism in a PWM 1C. The current source Is charges the soft-start capacitor Cl during start-up. When a fault condition or shutdown command is generated, Qd discharges Cl. SBU events can inadvertently result in Qd being tamed on and the quick discharge of Cl, causing an interruption in normal operation of the power supply.
Figure 2 illustrates a modification for improving the SEU response of the circuit of Figure 1. The addition of the resistor Rl limits the discharge current through Qd. Therefore, during the SEU event, Cl will become only partially discharged thus preventing interruption of the power supply operation and allowing faster recovery from the SEU event. Since Cl is charged by the constant current source Is, Rl does not interfere with the desired charge duration of Cl.
Figure 3 illustrates a latching implementation of the soft-start reset mechanism in a PWM 1C. The soft-start capacitor Cl is charged to a predetermined voltage through the resistor divider comprised of Rl and R2 during power supply start-up. When a fault condition or shutdown command is generated, the SCR is triggered and discharges Cl until the discharge current drops below the SCR's hold current. Thus, the discharge mechanism is latched until Cl is discharged to a predetermined level, at which point the discharge mechanism is reset and the power supply then re-starts. SEU events can inadvertently result in triggering of the SCR (or equivalent latching circuit), which then would force the near complete discharge of Cl and thus cause an interruption
in normal operation of the power supply. Adding a resistor in series with the capacitor as in the previous example (Figure 2) will not work in this case because the required value of resistance would be prohibitively large and thus cause interference with the desired charge duration of the capacitor Cl.
The prior art circuit of Fig. 2, although helping to mitigate against SEUs, may not prevent the SEU discharge of the soft-start capacitor Cl. In the circuit of Fig. 2, although the resistor Rl reduces the rate at which the capacitor discharges due to an SEU, it also reduces the rate at which the capacitor discharges in the event of an actual fault or shutdown, which is undesirable. It is desirable to provide a circuit which prevents SEUs from discharging the soft-start capacitor and which does not result in changing the capacitor charge duration hi the event of an actual fault or shutdown.
It is also desirable to provide a circuit which prevents SEUs from discharging the soft-start capacitor and which also allows discharge of the capacitor in the event of actual faults or shutdown conditions.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a circuit which prevents SEU induced discharges of the soft-start capacitor and which, at the same time, allows normal charge duration of the soft-start capacitor upon startup.
It is also an object of the present invention to provide such a circuit that, in the-event of an actual fault or shutdown, allows the capacitor to be discharged.
By careful arrangement of a few discrete components external to a PWM 1C, it is possible to minimize or eliminate the effects of SEU on a PWM IC's soft-start circuit while retaining most of the other features and benefits that a PWM 1C may offer.
The above and other objects of the invention are achieved by a circuit for use with a pulse width modulated integrated circuit having a soft-start reset
function comprising a diode having a first terminal connected to a soft-start reset terminal of the integrated circuit, a voltage divider coupled between a voltage reference and a common terminal for the integrated circuit, the diode having a second terminal coupled to a tap of the voltage divider and a soft-start capacitor coupled between the second terminal of the diode and the common terminal whereby upon power startup of the integrated circuit, the soft-start capacitor is charged by the tap of the voltage divider and wherein in the event of a single event upset condition, when the soft-start reset terminal of the integrated circuit is reduced to a level at or near the level of the common terminal of the integrated circuit, the diode prevents the soft-start capacitor from discharging through the integrated circuit.
According to a further aspect, the circuit further comprises an external fault detection and shutdown triggered circuit across the soft-start capacitor for discharging the capacitor.
Other objects, features and advantages of the present invention will be apparent from the detailed description which follows.
BRIEF DESCRIPTION OF THE DRAWING(S)
The invention will now be described hi greater detail in the following detailed description with reference to the drawings in which:
Fig. 1 shows a prior art PWM 1C having a non-latching soft-start reset circuit;
Fig. 2 shows a prior art PWM 1C using a non-latching soft-start reset with external limiting resistor;
Fig. 3 shows a PWM 1C using a latching soft-start reset circuit;
Fig. 4 shows a latching soft-start reset circuit according to the present invention which prevents SEU induced capacitor discharge and having an external reset mechanism.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
With reference again to the drawings, Figure 4 illustrates a circuit for preventing SEU induced discharge of capacitor Cl. The addition of diode CR1 prevents the PWM 1C from discharging capacitor Cl while not affecting the desired charge duration of Cl. Ql and R3 provide an optional SEU tolerant mechanism for discharging Cl in the event of a fault or shutdown condition.
The start-up capacitor Cl charges via the voltage divider comprised of resistors Rl and R2. Transistor Ql is normally off.
In the event of an SEU taming on the SCR, the diode CR1 prevents the capacitor Cl from discharging through the SCR.
In the event of a fault of shutdown, the soft-start capacitor Cl cannot discharge through the SCR because of diode CR1. An alternate mechanism is provided to discharge the soft-start capacitor in the event of a fault or shutdown condition. This is provided by transistor Ql which, if turned on by a fault or a shutdown condition, it will allow the capacitor Cl to discharge through the series circuit comprising R3 and Ql.
Accordingly, a commercially available PWM 1C may be used in applications where SEUs occur, for example in space and military applications, because the soft-start capacitor will not be discharged in the event of an SEU and therefore will not shutdown the power supply for the device. A separate fault detection and shutdown circuit is provided comprising transistor Ql and resistor R3 to provide shutdown and fault detection. Further, the circuit according to the invention does not interfere with the normal capacitor charge duration since the capacitor Cl charges through resistor Rl.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the present invention should be limited not by the specific disclosure herein, but only by the appended claims.





We claim;
1. An apparatus for providing resistance to single event upset to pulse width modulator
integrated circuit comprising :
a pulse width modulated integrated circuit (PWM 1C) having a soft-start reset function and a soft-start reset terminal (EA) connected thereto:
a diode (CR1) having a first terminal connected to a soft-start reset terminal (EA) of said integrated circuit (PWM 1C);
a voltage divider (Rl, R2) coupled between a voltage reference and a common terminal for said integrated circuit, the diode (CR1) having a second terminal coupled to a tap of said voltage divider (Rl, R2); and a soft-start capacitor (Cl) coupled between the second terminal of said diode (Rl, R2) and the common terminal; whereby upon power startup of the integrated circuit (PWM 1C), the soft-start capacitor (Cl) is charged by the tap of the voltage divider (Rl, R2) and wherein in the event of a single event upset condition, when the soft-start reset terminal of the integrated circuit (PWM 1C) is reduced to a level at or near the level of the common terminal of the integrated circuit (PWM 1C), the diode (CR1) prevents the soft-start capacitor (Cl) from discharging through the integrated circuit (PWM 1C).
2. The apparatus as claimed in claim 1 wherein an external fault detection and shutdown
triggered circuit (Ql, R3) is coupled across said soft-start capacitor (Cl) for
discharging the capacitor (Cl).
3. The apparatus as claimed in claim 2 wherein the external fault detection and
shutdown circuit (Ql, R3) comprises a switch (Ql) coupled across said soft-start
capacitor (Cl).
4. The apparatus as claimed in claim 3, wherein the switch (Ql) is disposed in series
with a resistor (R3) across the soft-start capacitor (Cl).
5. The apparatus as claimed in claim 4, wherein the switch is provided with a transistor
(Ql) having a control terminal coupled to an external fault detection and shutdown
signal.
6. The apparatus as claimed in claim 1, wherein the said pulse width modulated
integrated circuit (PWM 1C) has a semiconductor switch coupled between the
common terminal and the soft-start reset terminal (EA).
7. The apparatus as claimed in claim 6, wherein the switch in the said pulse width
modulated integrated circuit (PWM 1C) comprises a thyrisistor.
8. The apparatus as claimed in claim 1, wherein the voltage divider (Rl, R2) comprises a
resistor divider circuit.
9. The apparatus as claimed in claim 1, wherein the diode (CR1) is polarized such that
the first terminal is the anode and the second terminal is the cathode.


Documents:

1981-delnp-2005-abstract.pdf

1981-delnp-2005-claims.pdf

1981-delnp-2005-complete specification (as filed).pdf

1981-delnp-2005-complete specification (granted).pdf

1981-delnp-2005-correspondence-others.pdf

1981-delnp-2005-correspondence-po.pdf

1981-delnp-2005-description (complete).pdf

1981-delnp-2005-drawings.pdf

1981-delnp-2005-form-1.pdf

1981-delnp-2005-form-18.pdf

1981-delnp-2005-form-2.pdf

1981-delnp-2005-form-3.pdf

1981-delnp-2005-form-5.pdf

1981-delnp-2005-gpa.pdf

1981-delnp-2005-pct-210.pdf

abstract.jpg


Patent Number 240206
Indian Patent Application Number 1981/DELNP/2005
PG Journal Number 19/2010
Publication Date 07-May-2010
Grant Date 29-Apr-2010
Date of Filing 10-May-2005
Name of Patentee INTERNATIONAL RECTIFIER CORPORATION
Applicant Address 233 KANSAS STREET, EI SEGUNDO, CA 90245, U.S.A.
Inventors:
# Inventor's Name Inventor's Address
1 BAKER, STEVE C/O INTERNATIONAL RECTIFIER CORPORATION 233 KANSAS STREET, EI SEGUNDO, CA 90245, U.S.A.
PCT International Classification Number H03K 3/02
PCT International Application Number PCT/US2003/036381
PCT International Filing date 2003-11-13
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 60/426,448 2002-11-14 U.S.A.