Title of Invention

METHOD FOR CONTROLLING A CENTRAL PROCESSING UNIT FOR ADDRESSING IN RELATION TO A MEMORY AND CONTROLLER

Abstract

The present invention is based on the finding that free CPU operation code identifiers (310) of a CPU (30) or CPU operation code identifiers useable for any reason can be used to control supporting means (40) upstream of the CPU (30), which is able to form, responsive to these operation code identifiers (310), a new, for example, physical address in relation to a second memory area (20) having a second memory (5) which is larger than the, for example, logic memory size (370, 380) addressable by the CPU. By means of the special operation code identifiers (310), it is thus possible in the course of an executable machine code to address the supporting means (40) which monitors the data traffic via which the operation codes to be processed or the operation code identifiers are provided to the CPU (30), from the memory (20) to the CPU (30), and which can take measures in relation to the new formed address when certain special operation code identifiers (310) occur. In this way, on the one hand, a complicated redesign of the CPU (30) and, on the other hand, the necessity of a software-resetting of the current memory window (370, 380) complicated as regards both the executable machine code and the processing speed are avoided.

Full Text

Description lethod for Controlling a Central Processing Unit for Addressing in relation to a Memory id Controller. he present invention relates to controllers, such as. for example, microcontrollers, icroprocessors and the like, as are. for example, emplo\'ed in ASICs (application )ecific integrated circuit). SOCs (SNstem on chip) and the like. and. in particular, to )ntrollers basing on a CPU architecture (CPU =^ central processing unit) which do not ipport an addressing of a menior\ si-^e required. Ithough the de\elopment of microprocessors and microcontrollers has led to insiderable performance increases, in certain technological tlelds of application, such . for example, in the chip card area or in SOC designs, older CPU architectures are eferred to newer architectures when integrating a CPf! in an integrated circuit. A ason for this is that newer CPU architectures having a higher performance are often 'ersized for the respective field of application provided and thus, as regards the tasks to performed, require too much power and take up too much chip area. Another reason r preferring an older CPU architecture to a newer, more powerful one is that the ftware devel'.)pment environment for the older CPl' architectures, .such as. for example. ; 8051- or 8052-based microcontroller architecture, is often more popular with stomers, and that more software developers are available for them. : 43 40 .-^51 Al directl} deals with treating jump instructions within the scope of :)anding thj address space of the program counter of a microprocessor. With this :roprocessor. the program to be executed is stored in a prograin storage 30. wherein the instructions to be executed in succession reach the decoder 20 or the processing unit 20 of the microprocessor 1. respecti\el>. \ia a data terminal 12a. With a program counter overflow or underflow, a counting clock circuit 10 sees to the fact that the xalue of the program counter 8 is expanded b\' a corrected high-order part in a register 2 and 4. With absolute jumps, in the program code in the program memon, 16. two instruction lines are inserted, i.e. a MOVE instruction which writes the high-order bits of the expanded address into the register 2.4. and a normal jump instruction (L.IMP). which enters a 16-bit address into the register 8. which usualh is only to be processed b> the processor 1. Via a line 23. the processing unit 20 sees to the fact that errors due to the circuit 10 are prevented b\ deacti\ating the same. .-Vpart from the absolute jump instructions, in this document further jump instructions are also dealt with. All implementations have in common, that some additional instructions are required, that the same come from the normal instructions supply of the microprocessor, howexer. This document discloses no means which monitors the data traffic from the memory to the central processing unit with regard to an operation code identifier, and. in case an operation code identifier is included in the data traffic, provides a predetermined operation code identifier to the central processing unit. The problem of the software de\elopment environment, more popular with cu.stomers. for older controUci architectures is of particular importance in the chip card area, since in this case the generation of the machine programs which can be processed on the chip card or tif executable machine codes does not fall into the responsibilitv of the chip manufacturer but, for reasons of safety, or maior customers, such as, for example, banks and thei: soft//are development companies, and of the respective operatiri^ system aeveloping company. In addition, due to the hiqh numbers required, it is of enormous importance foi tne chip card custcr":ers to use chip card controllers adapt^-d ¦ , the respective requirements in order to keep the ccst ay. .". ow as possible. In order to satisfy the low-end chip card -iiea and to meet the desire of some customers lor well-kn>^v;n software developing environments, the chip caro m.anufacturer consequently has to be in a position t^; jffer chip cards basing on an older microcontroller arcnitecture. A problem in using older controller architectures ir. chip card manufacturing, however, is that their ways of addressino are not sufficient. Thus, m the chip caiG area, rhe capaoility of an 8051-based CPU is basically sutticient to take over the managing tasks of a chip cara, but ror reasons of high safety requirements, cryptography algorithms which include calculating operations m relation to very large operands must be processed on the ihip card by cryptocoprocessors. In the well-known RSA Rivesi, Sharmir and Adleman) algorithm, operand lengths of, tor example, 1024 are usual. Due to these large operano lengths to be processed and the complexity of the cryptography algorithrrs themselves, access to the largest possible memory is required in chip cards. Here, the problen, of using CPLs basing on older controller architectures- :_s that they only allow an addressing of small memory sizes. 8051- based CPLis, for example, only allow an addressir.g if 64 kBytes. A possible solution for rendering addressable a la:qe memory Qfispite the usage of a controller having an ¦; Ider architecture is to use externally storea descriptors or basis addresses determining the position of a memoii- window addressed by the CPU so that the memory area addressable by the CPU '--an be shifted over the entire larger memo!-/ by means o;: the memory window. Fig. 4 shows a block diagram of an 8-bit controller generally indicated at b:'0 an:; consisting of an 8051-based CPU 805 and an MM!J mern/ry management unit), and a memory 815 connectec tc ti- controller 800, which can consist of different r.ierciKiv types, SL.ch as, for example, a read-only mem:'y/ :P-'~l , -, random acress memory (PiiM;, a ncn-vclati_e mier.o; / ¦:i.H), such as, for example, an EEPROM or a flash mentor/, .::d tne like, and is only illustrated as a block for a b^-tt-: understanding. The CPU 30 5 is connected, via a-^ ---b ¦: address line 820 and a bidirectional S-bit dat t iin-:- -r25, to the MML 310 which, in turn, is connected tc the m.^^imcry 815 via a 12-bit address line 840 and a bidirectiona. 8-bit data line ••;45. In the case of a chip card, the lontr^ ^ler 800 is, for example, connected to further compo;ierts, such as, for exam.ple, a cryptocoprocessor for performing cryptography algorithms, an interrupt module, a conta^-" or contactless interface for performing the c&mimuni catiu: to a terminal, a random number generator and further ;o!iipcr;ents, which are net illustrated in Fig. 4 for simpiif i:at lor.. A problem with the controller 800 of Fig. 4 is that t\u- CPU 805 is based on an 8-bit architecture and, as regards ,ts command set 855, only allows an addressing cf 64 ^B^te.^, while the size of the memory 815, in the case of o cni|;. card, must be larger and, in the example of Cig. -, is r^r example one miegabyte. The reason why only 64 kEytes .ire addressable for the CPU 805 is that in data accesses b^ means of the comimand set 855, and, in particular, oy mear.s of the reaa/v;rite commands, such as, for example, * he MC' t:ommands, and in code accesses for producing ^n adcress, only two bytes 16 bits) are used which only dlow iCitit_ ; cf 2'^ = 64k st,:.tes. Wnen executing a read command, the CPU 805 outputs ' he I^. ^ bit address on the 8-bit address line 820 and "he &-bi' data line 825. ;-.s a response, the CPU 605, on the data lines 825, waits for the memory contents of the memLCty 815 at the address required. In order to enable addressing the 1-MB memo.:y 815, a data descriptor 860 is stored outside the CPU 805 in the MMU 810 indicating a basis address added to the lb-bit address by the CPU 805, whereupon rhe ;esult is output on the 12-bit address line 840 and tne 8-tit data line 845 r'or addressing to the memory 81^. In ;_h s .-.-;¦/, ^ 64k data :-iemory window 865 in the rriemory 315 ;s .ler-r.ed oy the descriptor 860, the starting address of whicr, corresponds to the basis address indicated by th^-i descriptor 8 60. By providing the descriptor 86 0 and the MMU 810, it is ensured that the CPU 805 will alwa\ s iccf-ss the memory window 865 in memory accesses in relatior to the memiory 815, wherein the address output b-_. the CP J H'': indicates the offset of the byte to be read wothm tne memory window 875. The CPU 805 executes a write ir read comiTiand, wherein the MMU 810 translates the It-bit address from the l:PU 805 into a physical 20-bit address and redirects the access correspondingly. Although ihe concept of the descriptor 8b0 can be extended to any memory sizes in connection with the MMU &iO, it is of disadvantage in that, in memory accesses tc addresses of the memory 815 outside the memory window 865, the MMU 810 must first be reconfigured, i.e. the descriptor 36iJ must be reset correspondingly. This reconfiguration ot the MMU 810 is especially complicated since it requires a software- setting of the descriptor 860 and since, in a memor ,• continual Ly visible (i.e. addressable) for the CPU --05, a managing rode 870 must be stored, including ar MMU setting code for setting the descriptor 860, which recuces 'ne memory oirectly addressable, which is miostly '.er,- sriiall anyway. Im addition, the setting of the oescr j_pt .;r ~ kX} requires idditional clock cycles, which ; educes -rher operating speed of the controller. Assuming tl-e I'em^ry sizes IndLcated above, the duration for a dato arcooS to a memory adiress of the memory 815 outside the netr-.^ry window 865, for -1 compiled program, is, for exarriple, 14r' o....-ck cycles compared to 4 clock cycles for memory- ac :esses within tne current memory window 865. The problem of the MMU reconfiguration :ncreaseo ;¦ the area of code accesses wherein, in a coriesponding 'v-d/, a code deS'-riptor 8'/5 defines a code raemciy "¦•.'ir. ic;.- c ¦¦ , i:. that, when executing subprograms, i.e. -all .^ jmr-'ai. :.- , i,memory ajeas outside the memory window cSu, tne reiurn jump into the currently set memory window 880 must b^:- ei.surea. While onJy the code descriptor 875 must oe reset v;hen leaving the currently set memory window 880 wnile processing the machine code in the normal contnand sequence, i.e. when there is no jump command, or in jump cDmn.ards without return intention, like in data a:cesses, i<: tust be> ensured n jump commands with return intention tnat ,, in the case of tne return jump, the code descriptor ^75 i.- --et to the original value. In order to ensure tnis, the managing code 870 Tiust further comprise an initializinc c jde :alied in each jump command with return intentit n reiatLfiq *o a destinati'jn outside the currently set code manor/ v/indow 880 to ensure the restoration of the descriptor set rings before the jumip when returning. A possible sof tware;-realization is to pre vide, f't r . och bank, i.e. each possible memory window position, of the memory 810, an initializing code and a setting and resetting code organized in a table and stored it the continually visible memory area of the memory -^10. It order to perforn- a jump command with return intentiori beytntl the limits of the currently set memory windov.' 8 65, a iuin;.: command v;i ^h return intention, from a program -ode, ,eto a function m the continually visible miemort arec: mus' ¦ ake place, loaimg, into an internal register 585, su :h .-.e, for example, a data pointer DPTR, the 16-bit -iddrets )t ¦ ne destinatic'i code in relation to the destir.atior tr^nK, x.e. the offset within the destination bank, where the ccji'im.and to which has been jumped is, and subsequently calkin.: the initializitig code with a jump command without returr intention into the continually visiole memory area, by executing the initializing code, the address 11: -he MMU resetting code for recovering the currently set '^inccw 8-0 or the GUI rent bank is at first shifted to a sta^k ¦ i stack memory 89(, then the address written befcre into th^- interna]. i egister 88 5 is shifted to the ~-ack : -' ^-. ¦ finally the MMU setting code for the nev; aest.-.a: i-o' [¦¦Ml bank is called by a jump command without return ;. nt ¦. r.t lor:. At the end of the setting code, after MML reccnf:. gu: . ng nas taken plav.;e, a jump is performed to the cesirei :un-:Lon or the desired subprogram in the new set men^ory window Vvith a return -jump command. After processing the functi.m, '^ne l-IMU resettina code for restoring the original MMU conf i ¦:;uration or for re'::overing the originally set memory window ¦-- j is called by a return command to recover the oriainal MMJ setting. The return jump command at the end or tiie resetting code then, within the newly set memcr^y wi :>aov; 885, jumps to the corresponding following position .: the program code. In order to be able to reset the MMU -^0 b'/ means of :.he CPU commands contained in the MML setting cr resetting code, either special commands can be prov.aed with whic/i the CPU 805 can address the MMU 81C and ' ne descriptors 860 and 875, respectively, oi the MMU b responds to reserved 8-bit addresses fron the CPn H'-- on the address and data lines 820 and 825. In order to realize a memory area within the rrem(;ry -15, continual Ly addressable or visible for tr.e CPU 8ii5, :,ot all the 16-bi" addresses output by tne CPU 8C-5 are mapp^-J bf the MMU b:0 to the memory window 865 but to a fixeo nemorf area of t!te memory 815 so that the effectivelt aridt-. s sabxe size of the memory window 865 is reduced by the tian-nainq code 8'0 . It is the object of the present inventioit to prctid. a method fo.: controlling a central processing unit fc addressin.j in relation to a memory and a control_ei >^o tnat the addret-'sing of memory sizes excee'ding the miem^.-.rv size which can be addressed as a maximum by the CPU due to ,^s architecture; is less complicated. This ob^eci: ls achieved by a method accordirig tc ci^irr . or 9 and a controller according to claim 2 or .0. The present invention is rased on the iindir:g tr. it ti'-- I'P'/ operation cedes of the CPU, i.e. operation :;odes t: wr.i.rh no command irom the command set of the CPU nas teei assigned anci which, in the following, will be referre. lo as free operation codes, cr CPU operation ':;ode :denti;^5rs to which a command is already assigned but vjhicr are isable for another reason or are free as regards ^erta.n ope^dnds can be used to control supporting means upstrear; of f 'le CPU, which is able to form, responsive to :)pera-;icn L-:de identifiers generally referred to as special operaticn ccae identif iers>, a new, for example, physical, address ir relation to a second memory area having a second memory size which is larger than the, for example, locic memory size addressable by the CPU. By means of the spec^a: operation ;ode identifiers, it is possible in the course tf an executable machine code to address supporting meau-- which monitors the data traffic from the memor'/ t :;• tnt CPU, via which the operation code identifiers to be processed are supplied to the CPU, and which can take measures us regards the new formed address when certain special operation code identifiers occur. In this way, or the one hand, a cc-miplicated redesign of the CPU and, on ' he . ther hand, the requirement for a software-resettinc cr ttt current memiory window complicated as regards totu ^ -.^ executable machine code and the processing speec ar^- avoided. According to an aspect of the present mventi ^n rei,-ina to program jumps, supporting means is able -jo pr.viie, ro tne CPU, an operation code identifier assigned to a j unrc comm.and from the command set of the CPU. The j uirp "-^nmand operation code identifier contains a suitable destrnaticri address as regards the first, such as, tor exampie, .ogic, memory area to suitably set a program counter. T:ie supporting means at the same time manages a descrip'^ r of the MMU, v.'hich indicates the position of the tir,3t luemory area withi.n the memory area or which is set such thio.* the destination address, together with tne c^: de desc:i['' r, results in the new address. The ;; ump comnand £ap{'li- -: to the CPU relates to a destination address in relatio: zo the first memory area. The supporting means sets t^ie destinatiC'U address to which the jump corrjriand ls reared and the code descriptor such that the nev. address i / lu the first, fcr example, logic memory area, and thus the destinaticn address to which the jump corrLmand supplied to the CPU refers, in connection with the descriptor, corresponds to the new, for example, physical adoress. In this way, the supporting means, responsive to sniy j special operation code identifier, ensures tha^:, on :ne one hand, the descriptor and, on the other hand, tne prc-gr'am counter for the next code access of the CPU to regues^: the next opera'C-ion code identifier tO' be processed from •:r.e memory are set suitably, wherein a managing code wou^:; be required for this in the software solution illustrate::: in the introductory description. According t:o another aspect of the presen"". invention referring "::o a data access command, the support in j m able to supply a predeterrtiined CPU operation cr^de to 'he CPU in order to "stimulate" it suitably or to put ir ;n a suitable state, and to manipulate an address the CP[! outputs to the memory, based on the new f c rmeo adiire.-;,- sc that, from the perspective of the memory, the i mp .¦es-¦ .. 3n results that the CPU were able to address the secc.nd r:;emorj' area. In th:e case that, ouring a programi, the .:3n'eri';- at a certain address of the memiory outside the set mem.-rv v. Lnd.:,.w or the first memory area is to be read, that is ir i^. ..ition to the second memory area, a free operatic n code prc-/:ded for this may, for example, be inserted into the pi oc^=-ssabxe machine cooe. If it is requested by the CPU as the r;ext command to be processed from the memory, the supporting means responds to determine a new address for exampl-, from either a p;irt of the operation code itself or : rom reqister informatLo-i within the CPU or from register inior.'nan.on outside the CPU, such as, for example, in the supporting means. Tlie memory is read out at this add:-ess. Ir. a.:j;ticn, one or se-.'-rral CPU operation codes are suppliea tj "-¦'.-': CF'J in order for the CPU to enter a subsequently suppLiei memiory conr.ents into a desired destination register •'. the CPU. Additionally, the program counter fci indica-in; the next opera": ion code to be executed in the meirioi y is '.et suitably s. ¦ that the memory can be accessed with "h^:- .-lew address so that the memory contents of the new address can be read anii can be output to the CPU. Ever: in the case of data accesses, no managing code is consequently required to shift the tirst memory area or the memory windcw set before. By providing the usage of the free operation cedes o' of special operation code identifiers to control support mg means formung the nesw addresses outside the CPU, a d.rect addressing of the entire memory beyond the memcry arf-c directly addressable by the CPU with the CPU operrttt.r. code identifiers can be preferably obtained without na'-'in-; to perform essential changes on the setup of the CPU. B; the fact that the supporting means is upstream, of the CP^ , i.e. connected to the CPU in such a way that ir can moiiit' i the data traffic from the memory to the CPU, the free oper.iti^n code identifiers not assigned to a commano frorr tt^e ."L^mmand set of the CPU can, for example, be intercepted b\ rre supporting means before they reach the CPU. On the t.^sis if the new adcress formed by the supporting mieans, t-. wi.ich the free operation code refers, the supporting iieans -an suitably stimulate or control the CPU and, if req;.. i i ^-.t;, suitably manipulate the address signals of the :P'. t> w.-nrds the outside, i.e. in relation to the memiory. A orepaied software-resetting of a descriptor or a basis address is not requires, whereby, on the one hand, providing a managing code is omitted and, on the other hand, the number of clock cycles a code jump or a data access fron a currently set memory window requires is reduce!. By omitting Che managing code, no memory space in tne remory area continually addressable or visible for the c'?U is occupied. Another ad/antage of the present invention is ^nat o :iowr. compatibility to machine codes which only base on tt-r CPU operation ':ode identifiers can be ensured sine- tne supporting means may be transparent or imipercef-tiol- :or CE^U operation code identifiers. In additi'"--n, tne suppcrtmg means can oe provided to reset a code descript^' r :)r iata descrip'tcr in data accesses and jump commiands .n reiacion to addresses outside the currently set memiory v;indow so that resetcing the memory window can be obtained oy ¦inly one free c: special operation code identifier. By hardware- processing the free or special operation code : dent .i.:; _ers outside the CPU, additional interrupts during, fc.-: example, resetting the descriptors can be avoided so that, compared to software-resetting, the susceptibility to failure .s reduced. Preferred embodiments of the present invention -vi_..l ;e detailed subsequently referring to the appendec diav.'.ngs m which: E'ig. 1 IS a block diagram of a controller ac:ordir\j co an embodiment of the present invention; Fig. 2a and 2b sliow a flow chart showing the steps pfrrt jrme;: in tne controller of Fig. 1 in the :ase 'hat - :ree operation code corresponds to a read -ommanl witn 1 idirect addressing; Fig. 3 1:- a flow chart showing the steps per termed :,n tlie controller of Fig. 1 in the .case that tttr free operation code corresponds to a ]ump command with direct addressing with return iitent.:n; and Fig. 4 IS a block diagram of a controller using o previous possible solution zo extend rhe addressing possibilities of a C-'U. Fxeferring to the subseguent detailed description of arembodiment of the present invention, it i = to oe note:i that it refers to the controller of a chip' cara altnough ^ ne present in/ention may also be applied to ~ontr'..ller5 ;.n different fields of application, such as, for exampie, in ASICs, SOCs or TPMs (trusted platformi module], oi ma'/ be embodied as an individual microcontroller element . It is also to be noted that the following embodiments only rely on free, non-reserved free operation codes t: which no command from a command set of the CPU is assigneo. T* is to be noted that it is also possible in alternative embodiments for controlling the supporting means to ..se reserved operation codes in the form of operation cooe identifier;; which are suitable for this fcr differen: reasons, wherein the expression operation code identirier subsequent] y is intendeo to include a comibination of dn operation c-ode and an optional operand, such as, lor example, an address section. It could, for example, te the case that a certain commiand is not supported or used c y the compiler ard the operation code of which tnus can be employed otherwise, or that an operation code in combination v/ith a certain operand is free, i.e. undef.nea. In addition, it is to be mentioned that the subsequent description refers to a memory having a site of 1M3 addressed by 20 bits, although different memory,- Sjzes, such as, for exanple, 14 MB, and different numbers oi bits tor addressing, such as, for example, 24, are also possib.-. Fig. 1 show::: a microcontroller generally indicated at. .U according tc^ an embodiment of the present invention, ,ti\d a memory 20. The controller 10 includes a CPL' 30, suppoi^ing means 40 ana an MMU or memory managing unit: 50. Th-e C:-'.! 30 is based on an 8051 controller architecture and is connected t the supporting means 40 via a bidiiec' i' :.,;^ ••:- bit data lir.e 60, an 8-bii: address line 80 and an ^nt'--:rup^. line Int 90. The supporting means 40 is connected ':o M.e MMU 50 via .i bidirectional 8-bit data line 100, an 8--; .t address line 120 and an interrupt line Int 130. Bonh *ne supporting means 4 0 and the MMU 50 are connectec t'j t;r.<:-> memory 20 via an 8-bit data line 140 and 150, respect .vely, and a 12-bi': address line 180 and 190, respectively. The CPU 30, apart from other components not shown, su,_-h as, for example, adders, includes a decoder 21C, an in'zernal RAJM IRAM 22(' as well as internal registers to whicri a stacK indicator o.: stack memory indicator 230, a program. co-^;ntei 240, a data counter register DPTR 245 and an accumijla'ror 2 50 oelong. E'urther internal registers 2 60 are provided in the IRAM 22i.' in which a stack memory or stack 2^0 is further provided. The decoder 210 decodes operatic'^i c'vdes or operatiori code identifiers 280 supplied to the CPU -0 on the 3-bit drita line 60, wherein to each CPU operat..ori -ode or operatioi"! code identifier 280, a coiTimand fron a coirLmana set 2 90 of i: he CPU 3 0 is assigned. The supporting means 40 also includes a decoder 30 ) t decode operation codes or operation code identitiers supplied tc the supporting means 40 on the 8-bit data ..me 14 0 from the memory 20. The supporting means 40 re.spor.ds r .: certain C'pe:;ation codes 310 which do not belong tc th- CPU operation c-.^des 280 or are not for those reserved 'ipe;-.ticn codes, and i.V' which consequently no conamiano fron tne command set 290 of the CPU 30 is assigned. These cperi*ion codes will t)e referred to as free operation codes ilo subsequentl',-. Apart from the decoder 300, the support, ng means 40 fu/. ther includes an adder 320 to miodifv, >is w:ll be discussed subsequently, ^U-bit addresses rormea .. r, tne supportinq means 40 by an offset value of, for e>.am[:ie, 4 or 16 bits, and an external data pointer regiscei XI E-TR 325 having a i'lze of three bytes. The MMU 50 includes external registers f•/r: st:::L'"g .-¦. latu descriptor 330, a code descriptor 340 ano, opt . or ai., _. , a:. interrupt descriptc^r 350. Apart from the components mentioned, the ^.'PU :¦, thf supporting means 40 and the MMU 50 each icclud- -; ^nr r :.llirig means which are, however, not shown and perforr, --onci.l tasks obvijus from the following description. It is to be pointed out that the chip card cont,ro lie/: 10 may further be connected to other comiponents n..'t shc-wi in Fig. 1 for reasons of clarity. One or several cryptocoprocessors for performing cryptography algor_':hms, a transmission/reception interface, such aS, fcr example, an UART moiule (universal asynchronous receiver- transmittei'J , an oscillator for producing an interna; clock, an interrupt module for hardware-generating interrupt signals and a random number generator which are connected ": o the controller 10, and, for example, particular.l V' to the supporting means 40 via an adare:-?; data bus can, fcr example, belong to the components ::oune"red. The set of operation code identifiers the "PU 2[> ;nr_udes, in the present case, consists of CPU operation :oae identifiers 280 and free operation code identifieis ¦.;('. Each operation code identifier generally consists ol in operation code indicating the type of comitiand a,~id thi.h the manner of frecessing for either the CPU 3C or tie supporting means 40 and, if applicable, or furtier: informatior, such as, for example, an address p^ .rtror :or indicating an address to which the commana asso:iatec to the operatim code refers, and/or an ciperand se'/tion t :: r indicating an operand to which the command refers, sunt as. for example, an offset value in relation tj the acdress indicated in the address section, or an addend for at. addition command. The overall number of operation codes, and consequently that of the operation code identifiers, is thus limited by the number of coding possioilit i^e- f c r the operatior. ides . Correspond:, ng to the limited number of adaress lines ^ i3 and data lines kO, the command set 29C only allows the Crf 30 to access -- memory area with a limited memory size, ,e. nA kBytes m ::¦. bitwise access. Even in code accesses ir_ ¦.-.hicn the CPU 30 requests the next operation coce identifa-i tc be process.-d by means of the 16-bit cede address stc^ted iii the program counter 240, addressing is liniiteo tc a •- kBytes mem'">ry. In the present embodiment, the size of the memcry 2(j .s to be, for example, one megabyte, wherein other memory sizes are also possible. The memory 20 can thus include a plurality jf memory types, such as, for example, an yj\M, ROM, NVM, such as, for example, an EEPROM or a flash memory, or the like. In order to allow the addiessin.j of the entire physical memory 20 by the CPU iO in data accesses b'/ means of the command set 2 90 i-r in code requests, the data descriptor 330 and the code descr:,ptor 340 are provided in the MMU 50, determining the basii addresses ir the position for a code window area 11C: ^nd a data window area 380 within the memory 20, which nav- a respective size of 64 kBytes and determiner loq-c mem.;ry areas to winch the data accesses by means of the ::omrriand set 2 90 or the code accesses of the CPU 3'i by r.eans >: the program counter 240 refer. The principle of memory accesses with the help ot th-- descriptors 330 and 340 is to be illustrated at i irst with the example of a read command from the command set ,r i > provided t : write, to the accumulator 250, the memor.' contents or an address determined in two bytes of the internal registers 260, such as, for example, m '/-ht- aata pointer re,3ister DPTR, i.e. in the usual riotation. t iF.ing the example of the command "MOVX A, @DPTR". It is t" r^e noted tnat the subsequently described embcdimer_t is .¦;e^l as the following ones refer to scenarios in which the currently jequested comiriand immediately fllow;- ~. ']¦¦'¦'[ comiTiand, nnd in which the CPU 30 outputs ' he aidi -S: requestea .^n the program counter for requestinc t'le .rrent command. It is possible that in other scer.arioe i ¦; w:..in the currently requested command does not ::irectli f > ¦, .. :,'W the jump cjmmand, the subsequent address is managed :• the memory 20 m the form of an auto-mcrementer attcrnar ., ^. all y incrementing a 20-bit code address, and ir. which the PU 30 only outputs a request or activation signal to thi-r m>7/miry 20. The CPU 30 requests the command by outputting the If-.-r, it address stored in the program counter 240 on the nddicss lines 80 and data lines 60. The supportinc means -40 pdsses the addres-. signals on to the address lines 12C and lata lines 100 ;n an unchanged form. The MMU 5l manipu.at-c'b the address si^^nals indicating the 16-bit code addres.s leased m the code descriptor 34 0. The code descriptor 34 0, fc' example, cr-ntains more significant 4 bits placed .. n : i ont of the 16 lilts of the code address, wherety 16 oossiiie memory winiiow positions result which, subsequent It , wi.^l also be referred to as banks. Or the code descrlpto: "40, apart from the more significant 4 bits which are fla^ ea m front of tt\e 16 bits of the code address, contains tiithei bits to allow more than 16 possible memory winoov; positions. The MMU 50 outputs the resulting 20-Dir i: ;:.i address t: the memory 20 to request the machine c,;de, . .e. in this ca.-e "MOVX A, @DPTR". The memory Ij cutouts i r.e CPU operation vode identifier 280 from the code mem^r. window 370 via tne data lines 150, 100 and 60 to the CPU 3t.y wherein tn€- MMU 50 or the supporting means 40, respectively, passes on the CPU operation lode identifier. The decoder 210 decodes the operation code identifiei .:'80 of the corniTiand MOVX A, @DPTR and, correspondir.g ':o ' r:e decoded command on the data and address i ines 6C, r , outputs riie contents of the data pointer in orie: r access the correj;ponding memory contents in the data i^er.or;. v.'inaov; 380. By being passed on by the supporting means 40, ^ne i6- bit address of the data pointer reaches tne MI-1 ' producing the corresponding 20-bit address tro:\ .\ • .eth^r with the data descriptor 330 and outputtmg it t; f.-r memory 30 rn the address and data lines 1^0, ]' 0. Tn- memory 20 returns the corresponding memory con"er';s rf.e CPU 30 via the data lines 150, 100 ana 60, wheic _t loaded int.' nhe accumulator 2 50 by the CP'. 30, is i ;- determined by the operation code of tne comirian-j M;:v> ,- , @DPTR. In order tc avoid a complicated sof tware-reconf-_gi^ rm:; or resetting cf the descriptors 330 and 340 before a jumr command or a data access beyond the limits of tne ":oa-i memory window 370 or the data memory window 38C', respectively, as has been described above, the ^upporv^ng means 4 0 is connected to the CPU 30 in such a way "hd' it can moniror the data traffic from the memory 20 to th., CPU 30 to be able to respond to the free operation : I'des ¦ : O'l before the CPU 30, when they are requested from tht .; ¦. oe memory window 370 of the miemiory 20. As will be snown v ¦, the subsequent discussion, it can be guaranteeo by ^^ii.; arrangement jf the supporting means 40 that the ^crma;; -n of a sufficiently large address, i.e. of a 10-b^' a:id:-iss, in the supporting means 40 can be guarantees, wh le tr^- 'IPC 30 is suitably "stimulated" by the supportiiig mec:ri5 4^ The supporting m-^ans 40 is further connected to the PC 3- -uch that it can monitor the data traffic from the CP'_ 2' ' the memory 20 in 'jrder to manipulate address signals th^- Mf-'l 50 outputs m tider to. pe^rform addressing in relati: i *c ¦ i '= memory 2-.0. Referring to Fig. 2, a course of steps will oe de5crib--3 subsequently, as occurs in the controller of Fig. 1 //he'; the next operation code identifier to be p^rtormed following a jump command, which the CPU requests, is i free operation code identifier corresponding to a reed jr ^:ad command referring to an internal destination re'jister ;f the CPU and a 20-bit source address indicated b'/ rrear. 3 of indirect a:^o.ressing in inLernal registers :¦! th- Pt • . In step 4 0C, the CPU 30 must be, at first, cent trolled oy the executing program in such a way that tne re3i.r~e:r: to which the new read command as regards the address Eorn.ation is to refer, are loaded to jointly result m the J j-t :-" address to which the new read comiriand is relate!. Ir. t tie embodiment shown in Fig. 2, these are the internal registers E--1, R2 and R3 of the CPU. In oraer t; f-lj. tnese internal registers, the following CPU operation c-de identifier sequence could, for example, be present :: the memory 20 in front of the free operation code identi:ler: "MOVX A, @Dptr", "MOV R2, A", "MOV R3, #0xl3H", whei-.-.n Ri with 1 = 1 ... 3 indicates an internal register Ri, A indicates the accumulator 250,, Dptr indicates tne data pointer .45 and #0xl3H indicates a direct address in a hexade':imo.. form. In step 40'"', the CPU 30 requests a next c.^mmtanc t L-: executed ii this case directly following n j umf. cmrrir^nd, cy outputting the 16-bit code address stored in the ;:r':.j:-am counter 24 i on the address and data lines 80, UJ. Th- 16- bit code address of the program counter 240, 11 s":ef- -10, after it hfis passed the supporting means -^0 unchangei, is mapped or nanipulated by the MMU 50 using the . oa- descriptor 340 to a 20-bit code address p^ssino c i • .i.- MMU 50 to the 'iiemory 20. The 16-bit code address stoi-d : rhe program ::ounter, for example, corresponds to a ie::s significan-i part of the 20-bit code address, while • ¦,-; code descriptor 340 corresponds to a more sign.-f icart 4-L: . v part of the 20-bit address, or a more significant n-biL fait, wherein n is, for example, 12. The mapping or manipu ^ dticri of the 16-bit code address is performed b,' the MMU : j by means of supplementing in. Alternatively, the cc-ie descriptoi; 340 can correspond to a 20-bi" bas-s .^r •¦•.arting address ci a bank so thar the mapping is perf'.. rm>-d :•; means of adding the descriptor 34 0 to the 16-b:t ccoe •idcirt--ss. In step.' 4]b, the operation code identifier of " r- i ¦-:. .ies\-=:i command at the 20-bit cede address having re3u,-t-i : r .^m vne code descriptor 340 and the 16-bit program count'-r .4:" i.-- taken from the memory 20 and, via the address rn^; d.-' _-; lines 150, 190 and 120, reaches the supporting mein:~ 40 unhindered from the MMU 50. In step 42'.:, the decoder 300 of the suppc; ting mecin^ -'¦'J checks vjhether the operation code identifier re:e:ve'-. by the memory 20 has a free operation code, as is Ln:;ici':ted oy the operation code. If, in step 420, the result i.; trar. tne operation code taken from the memory is not a f-'ee operation code, it is, in step 425, passeo unhirdere'-i ;n supporting means 4 0 and passed on the CPU -¦0 vir, t.ne address ana data lines 60 and 80, whereupon the CF'J operation c^.^de identifier is decoded and executed cy ' ne CPU 30 m tlie conventional manner. If the operatioii c...(::(e from the memory 20 is, however, a free operation cc.de, the operation cede will be decoded in step 430 to deteimir.e which of the free operation codes 310 the operat^^or C' 3c is . As has been mentioned hereinbefore, in the lase f Fie: 2 it is assumed that the operation code is a ""ree ' perar _n code corresp'vnding to a read command with itidire.t addressing. In step 435, the supporting meats 4C ie"ei:'..ies the contents cf the internal registers Rl t. P.3 :f t hf- rU 30. The determination can be realized in dirferenr v.av:-. According to an embodiment, the supporting means 10 is further connected to the CPU 30 via a line 542, w.'iie.h niaKes it possible for supporting means 40 to poll the c intent.-- of the registers Rl to R3. This can, for example, be executed with the help of a trace mechanism so that tne sup-port mo means 40, via the line 542, is connected to ar mtt-;: r.al bus of the CPU 30 to which the IRAM 220 is connecteo, ,:i;.>: via which the registers Rl to R3 in the IRAM 220 are Ic-aced. In another embodiment, the supporting means 40, fjr determining the contents of the registers Rl t :j F5, jses CPU operation code identifiers which _Lt sjppli'-s '\c \-.e c&O to stimulate the CPU in such a way that i ¦. outnui;- '-i- contents or the registers Rl to R3 on the data li-ie r ¦ , wherein suitable meaisures are taken to cortrol thtv pr. gram counter 2 4C' suitably. In step 440, the supporting means 40, from the oetermmed contents, forms the 20-bit address to v/hicn the free operation code identifier or the read commiand i.- rela!^-d. In step 44 5, a predetermined CPU read operation loae identifier is supplied to the CPU 30 by the supportinc; means 4 0 depending on the free operation code identifiei oi the free operation code. Since the free operatic:, cjde, for example, corresponds to a read command loading the memcry contents at the 20-bit address determined fromi the -'eg-rster contents inrc- the accumulator register 250, the supporting means 40, in the present code, supplies an CPU operatici code to the CPU, corresponding to a command "MOVZ A, @FL", i.e. a read command as regards the memory 20, pro'/ided ' ; load the m.emory contents at the address indic-ated by th-. registers used into the register A. The predetermmeo operation code identifier, in this case, would onlv ^onsist of the operation code. In step 450, the CPU 30 receives the CPU operation c^ ie identifier supplied by the supporting means 4' ana de ;od' , it. When execur_ing the supplied CPU operation lode identifier for the command MOVX, the CPU 30 ccntrols the' address and data lines 60 and 80 with the 16-bit adriress contained in the CPU operation code identifier with resp-r ;" to direct addressing or determined from an internal reigister with r-ispect to the indirect addressing anc fier. waits for a result to be supplied on the data line;:- t' "lo write to tht= destination register, i.e. the accumu^. at i 2 50. In step 455, the supporting means 40 manipulates the address sigials from the CPU 30 based on the 20-01^ g :'_:Les5 determined rrom the registers R2 to R3 ana passes ' h-r-.'; ;n to the memo] y 20 to access the conr.ent3 of the nr'emt.rv .-^'- The manipulation of the address signals or of the :'6~! :: address, respectively, by the CPU 30 can, ror example-, comprise refjlacing it by the 20-bit. address itself, ct.;oing or supplementing the missing section, such as, tor example, the four most significant bits, of the 20-t:it addres.-r ' ^.j the 16 bits of the CPU 30 and, if required, in case ^ •- . -: has not taken place already in step 4 30, aoditicna-ly adding unusec bits of the free operation cede iaeniif;, er as an offset value to the result. In step 465, the memory contents of the accessec 2'J-b:: address is then supplied to the CPU 30 via the cat.Ti ar.d address lines 60, 80, 140 and 180 and the supporting means 40. In step 470, the CPU 30 which, due to the predetermineo CPU read operation code identifier suppliec in step 4- ¦¦, is stimulated r-orrespondingly or has been placed ir a predetermined state, loads the supplied memory -: on^;,eri' > into the destination register, i.e. the accumulates ^: ¦ ' t, as is defined b'V the CPU read operation code. Finally, t r.^- CPU 30, in step 475, adapts the program counte!" 240 corresponding to the supplied predetermineti CPU re.id operation code identifier, wherein this step car tike uiace at an earli^^r time. After step -i75, the program counter 240, v;^thin th- / ie memory viindovj 370, consequently points to the nrixt c.')ri:fianc to be processed or operation code identifier ace or j.in : to the normal command sequence and the memory content.3 -.;: the 20-bit address to which the free operation code iaeni. . : ler has been related is in the accumulator 250. Independently of the position of the currently set data memory A^iri^^w 380, no software-reconfiguration of the MMU 50 or ot "he data descriptor 330 is required. When rea.izina i.rie controller shown in Fig. 1, the memory access .-iCc ;)rc . rig tr Fig. 2 only takes two more clock cycles tnan ir memi:r. accesses \: : means of read commands fromi t:re ccririarid ;-•: ^ :• j v;ithin the ¦_:urrently set memory window 36 '. The addressing when executing the free operatic n rod-- identifier, in this embodiment, is performed b\ mean - of indirect addressing using the CPU's own registers. Nevertheless, in the design of the contrc'^ler 10 oasr^j on an existina CPU layout, hardly any changes of The CP' layout are required so that the implementation of su ¦.'. a controller is not complicated. Referring to Fig. 2, it is also to be pointed cut th^r." it is possible to use an externally arranged register, rjch as, for example, an XDPTR register 325 for forming tr.e 20- bit address. In this case, the free operation code wii^ld include the- indication that the XDPTR register is to be used for addressing. This could be loaded with va-uer from internal registers of the CPU, such as, fc r examp-^e, v. rth the contents of the registers Rl, R2, R3 m step hO( ty other free operation code identifiers. In the latter rase, these free operation code identifiers wouid simply b to the commands for loading the registers Rl tc R; c: step 400. When using such free operation codes using the external register XDPTR 325, the CPU 30 weald nrt hare cc be changed as regards layout to determine the crntertr cf the registers Rl to R3. This has the advantage that i r:e CF'J registers Pu to R7 could be continually used f o ¦" ritrerent purpC'Ses m the meantime. Examples of commands for loading, reading 3r otnerwis-e using the external register XDPTR 325 are Liste-i subsequently, wherein the usual notation has been use 3: Xmov XDPTR ¦R3&R2&R1} (2B) Xmov XDPTR R7&R6&R5) (2B) Xpush ^2B) Xpop l2B) Xmov XDPTR,'?!DPTR ',2B) Consider MSB imos^ significant cit ¦ , L^J E .-as- significant, tit: po; it . r. Xmov @DPTR,XDPTR (2B) Consider MSB (most significant bit), LSB .east significant oit'i pc-;i* t. Xmov XDPTR, wRi (2B) with 1 = 0...7 Xmov {aRi,XrPTR (28) with i==0...7 Xmov XDPTR,dadr (2B) Xmov dadr,7.DPTR (2B) Xadd XDPTR,#constl6 (4B) Xadd XDPTR. (Rn&Rn-l) (2B) with n=1...7 Xinc wherein Xmov indicates a register load corraiiana, Xad-.":: indicates an adding command, Xpush indicates a stac.K filling co'nmand, Xpop indicates a stack discharge coirar.and and Xinc indicates an incrementing command. DP7"R, Ri Aith i = 1...7, dadr and X belong to the internal registers :f the CPU 30. constl6 indicates a 16-bit operand. "&"-sigr;-; indicate a concatenation of the two expressions to t :\e left and right. The bytes required for the respecti/e opetation code identifier are indicated in brackets on t:ie ciq'-:t hand side. It is to re pointed out that the possible read c; miTi.-.;r..is basing cf the free operation code identifiers ?ar t- related t: all the possible destination register.; o; another addressable memory in the CPU 30. In aid:tj r, possible read commands, based on free operati:"i oo' identif iei s, with indirect addressing car use il. t .' t registers or all the memory space wichin the CPU 3(' •- c each combination of this for forming the 20-bJt adare.ss •"'. which the read command refers. In addition, combinations ¦¦ ': direct and indirect addressing are possible, i.e. ; combination c>f the contents of one or several incei na registers cf the CPU 30 and one or several oytes ur 1 itsi within an address portion of the free operation :oGe identifier. It is also : : be pointed oat that the previ ^'Us ies: rif t .^on is easily applicable to free operatic'n code identitie:s correspondirg to write commands as regards a 20-oit address, wherein only the transmission direction ot tt.e accessed miemC'ry contents is to be changed to from the ; t-U 30 to the memory 20. In the foll;wing, in table 1 using the usual notation, examples of possible read commands XMOV are indi:ared, which can be processed by the supporting means 4 j responsive c: corresponding free operation rode identifiers 310 according to the embodiment of Fig. 2. XMOV ;_s tc indicate an operation code entering a memory con^ients indicated by special registers into, for example, the accumulator register, as will be discussed in greater detail referring to generic pointers. Subsequently, P:. with 1 = 0...4 is to oe an internal register Ri, XDPTR is tc be r he external data pointer 325 and A is to be the accumulator 250 and "off?" is to indicate an offset value of 8 bits. "&" indicates a concatenation of the expressions tc tr.e left and the right. Table 1 Read Corrmiano.? Xmov A @XDPTR+off8 (3B) Xmov A eXDPT'R-^Rx (3B) with Rx = {P ),r4} Xmov A IS (R3cxR2&Rl,)+of f8 (3B) Xmov A (s (R3(uR2&Rl)+Rx (38) with Rx = {Ri,H4} It is also pointed out that it can be provided that tne supporting means 40 supports a free operation code providea for handli ig generic pointers or is responsive tc^ i'" A generic pc.nter consists of an address and an ;ndiCri- ..on of the addres;:'ing type., The addressing type mdicati'^n basically : ndicates using which command the menoi'/ ; to ce accessed wjth the address of the generic pointer. Th- 8051 architectu:- provides four addressing types tc .-."h;-:!" '\e access typ'c using new free operation code ident^fiei. s added. The rour 8051 addressing types include: IData 3c:ess, wherein the access (read or wr:te) '^ i'-.es place in relation to the IRAM 220 of rhe CPU 3i h,^.-Lng ^- size of . 56 bytes and thus can be addressed vitn ¦¦i-V one byte, XData access, wherein the access takes place iMCVX :.o the currently set data memory window 28C of tne external memory ;>;RAM) and two bytes are indicated for addressing, PData access, wherein the access also takes p-^ace r : the currently set data memory window 380 of the externa., memory iXHAM) and, for addressing, a register AdrXl'i ,s combined v.'ith the predetermined register Rl tc ^ _e.. ! a 16-bit aadress, and code access, wherein the currently set code memojy window 37C is accessed (MOVC) and two bytes are ;:lsi indicated tor addressing. When outputting the respe',. t :.ve 16-bit address by the CPU 30 on the data and aidresj- lines 60 and 80, a code access could, for examfjle, ce dif f erenti-ired from an Xdata access towards th-- L;it.s.::e by indi':at:ng a different bus status on an addjCijna line I not :;-hown) . In a foilowinc embodiment, the information ot the genej pointer, i.e. the address indication and the addressing type indicaticTi, similarly to the embodiment of Fig. 2, regarding the indication of the 20-bit address, within the machine code sequence is stored before in the internal registers Rl to R3, whereupon a subsequent free c-peLa-iion code identifier corresponding to a command for hana.. ing generic pointers is provided to activate the sappor^ing means 40 v.hich subsequently, depending on the adaressmg type indication, supplies to the CPU 30 a prea-vtc rn'i. r ed 'I'FU operatiC'n ::ode identifier having an address rejin .^c'". depending on the address indication of the generic pointer. The generi:- pointer to which the cc-mmand for hinolin:' generic pointers is referred can, however, be -jIso contained in a portion c^f the free operation c ide identifier of the command for handling generic pointers itself. Like in the description of Fig. 2, it s pointed C'Ut that not only the usage of internal registtrrs f^t r indirect addressing is possible, but that further external registers, such as, for example, the external >;DPTR register 3.25, can be used, wherein the fo_lowirig description can easily be transferred to this case. In the following table 2, with the example of read processes, for each type of access indicated in tne first column, th':; command actually aimed at in the usua. m.-tation is listed m the second column, the contents of the register F ~ is listed in the third column, the conte.nts of the registe;-r R2 is listed in the fourth cclumn, the contents ci the register Rl at a respective time wher the code access to the free operation code identifier fc handling gcineric pointers takes place is listeo ir tie fifth colunn and the CPU operation code identifier snp'plied to the CPU 30 by the supporting means 4 0 cr the corresponding command in the usual notation is i-istec3 m the sixth column. Here, the @ sign is to indicate the memory contents to which the following expressi-;n, at cm address, p.;ints, A indicates the accumulator 25n, AdrXn indicates an internal register of the CPU 30, MOVX indicates a read/write command regarding tne memory i 3, MOV indicates a read/write command referring tC' the internal memory IRA'-l 220 of the CPU 30 and MOVC inaicates -i c )ae access in telation to the memory 20. Table 2 Addr. iEfcCt Rj R2 Rl : op--r,3 ¦. . on I type i amed at 8 I 8 bit B bit i -cde I I bit i' ident . r ier i j : ^UC'P'I - ea to i i I ¦ he n- "¦ i Idata I M0\' A, @R1 OOh 1 -* address i l-lOV A, '-^Rl ' I I access j _______________________________ inaicat.on | Xdata (MOV/. Olh {address ROV.-: A, t^Rl ' i access j A, @ i R2 , Rl)_____________{ indication__________i i Pdata I MOVX FEh AdrXh address M3VX A, (JRl ' access A, @ j AdrXh, Rl)__________j_________ indication ,' code MOVC FFh | address MuVC A, ! access A, @A-t- (R2, Rl)_________j indication___________ItlH^^l^ 20-bit i MOVX lOh I address MOVX A,iJRl i data I A,@(f3,R2,Rl) - j indication ' access j____________________[ EFh j_________________________[__ _ ___^ arbitrary value In the case that the supporting means 40 receives ':he f i ee operation code identifier for handling a generic P'-^mcef . the supporting means 40 consequently decodes the ccnteni-- of the register R3 where the addressing type indication . .- stored, to feeo,, depending on the addressing type indication, in the case that tne addressing type is net 20-bit data access, the central processing unit 30 ^ '.PL' ooeration cede identifier corresponding to a wcize,'\es:i command in relation to the memory associated t. the addressing type, and in the case that the addressino t /pe indication corr-ssponds to a 20-bit data access, to tee J v .t-r central processing unit 30 a predetermined CPU operati-m cede identifier corresponding to a write/read command :. n relation tc the memory 20, and subsequencl\ , if su, trfi..e, to take predetermined action to suitably manipulate a.iares- signals of the central processing unit 30. In the case of an IData access, the supporting means 4;, instead cf tr.e free operation code identifi-r f'_v h-in":.._ng generic pointers, which subsequently, regarding 'he u : i _-. i notation, will be referred to as XMOV operation '.ode, i>eds the CPU 30 the operation code identifier for "MOl A. ' In the case . f an XData access, the CPU 30 ;3 fea trie /r'J operation cooe for "MOVX A, lapi" instead of the XMOoperation coc:e, wherein the supporting means 40 mianr pu_. ates the 16-bit address output by the CPU 30 respo-nsive to t ne CPU operatior code during the address transfer re:fardir;j the more significant byte corresponding to tne contents :.f the internal register R2 and passes the manipulated adoress on to the MMU 50. In the case or the code access, the CPU 30 is fed the ("T'l operation code for "MOVC A, ft+DPTR" instead cf the XMOV operation code, wherein the supporting means 40 manifruJ-jtes the 16-bit adaress output by the CPU 30 responsive tc ttre CPU operation code fed during the address transfer according tc the contents of the internal register.-: F2 c:nd Rl and outputs it to the MMU 50 in a changed formi. In the case of a PData access, the CPU 30 is red tr.e ':?': operation code for "MOVX A, yRl" instead of the XMCV operation code. In the case of d 20-bit data access, the CPU :j is fee t;e CPU operation ^ode for "MOVX A, @R1" instead .f the XMOV operation code, wherein the supporting means 4 0, as has already been described above, manipulates the address ojtput by the CPU 30 during the address transfer wi'h th-: contents of the internal registers R2 to R3 anil outputs i' to the memory 20 in a changed form. The advantage of providing a free operati'^n cccie toi handling generic pointers is that the handling ot generic pointers takes place m hardware, while scftwaie-lee, .aing would usually be required for this. In a special realizat 1 ^Ti of the controller of Fig. 1 v;.tn f : c/.d i ¦. ; a special free operation code for handling jener^c poi-.ters, a time saving of about 20 clock cycles ha.-^ beer C'Otd^.ned. It is to be pointed out that, as is shown m tcbi- ,., several coimgs, i.e. Ih-Eh, are possible for od^nq ^he indication that this is a 20-bit data access. Theee 1 combinat io is of four bits could be used t' enahle addressing of a 14 MB memory, together v;iin ancther . bits, instead of, in the present embodiment, a 1 MB niemory by using 2 4 bits for addressing and by using If-b^t .mes instead of 12-bit lines 180, 190. After the course of steps for the controller or F.g. .. has been descriDed hereinbefore referring to free cperat^^'^-n codes relating to read/write commands, the mode of operation oi the controller 10 will be described subsequently in the context with free operation code- corresponding to jump commands, such as, ror example, a jump command with return intention or without return intent ion. Fig. 5 shovvs the course of steps, as takes place .. n ¦ r.e controller cf Fig. 1, regarding an embodiment wnerei! ehe CPU requests the next operation code identifier fcr processing and this is a free operation cede laentit .ei relating t: a jump command with direct adcressing an^, witn return intention. Like in the previous emit edimenti , ' r.e request of the next operation code identilier c^kes f^iace indicating the code address in the program, countei . ret differently, it is assumied that a previous jump cemLmatd has been processed directly before it. Otherwise, tee request only takes place by outputting a request signal fromi the CPU 30 and using a 20-bit code address fee by me mere -ry 20. In step 60C', the CPU 30 requests a next comman'j t^: b-^ executed which, in this case, directly follows ; i jmi; command, by cutputting the 16-bit code ado;;ess t; : f= ; . r; the program counter 24 0 on the address ana iata li c^' - i , 60. The 16-:?it code address of the program counter 24 is mapped or manipulated in step 605, after i^ has passe..; ihe supporting r^ieans 4 0 unchanged, by the MMU ; 0 usi'ig th:- ;ode descriptor >40 to a 20-bit code address passing m ttu.- MMU 50 to the memory 20. The 16-bit code address st^^rec ir r he program counter, for example, corresponds t: a ^--ss significant cart of the 20-bit code address, v;hi.e th-r :ode descriptor 340 corresponds to a more significant 4-r:.i;. part of the 20-c.it address or to a more significant n-bi'; p-it, wherein n, for example, equals 12. The mappiing or manipulation of the 16-bit code address is performei; t\ the MMU 50 by means of supplementing it. Alternativel/, the code descriptor 340 can correspond to a 20-trt basis oi starting aadress of a bank so that the mapping is perfcrmed by means of adding the descriptor 340 to the 16-b.t cod- address . In step 610, the operation code identifier or the regue-ied command, at tJie 20-bit code address having resulted iron the code descriptor 340 and the 16-bit program countt-r . 4L', is taken from the memory 20 and reaches the supportirg means 4 0 unhir/dered from the MMU 50 via the address ana data lines 15C, 190 and 120. En step 615, tte decoder 300 of the suppcrtmj means ,^0 checks whether the operation code identifier :"ecei'. ea b'/ the memory 20 ^s a free operation code identirier, as is indicated by tiie operation code. In the case r he resu.t i. step 615 is thcjr the operation code identifier taken iron the memory is i ot a free, operation code identifier, it is passed, in step 620, unhindered in the supporting mieans 4;j and passed on to the CPU 30 via the address ana da^^a ._nes 60 and 80, whereupon the CPU operation code is oecodeT and executed by the CPU 30 in the conventional manner. I: ^ne operation C'.)de identifier from the memory ^0 is, h'jwe-er, •; free operation code identifier, the operation cede is decoded m -tep 625 to determine which of •ne fiee operation c.ries 310 the operation coae is. In the embo'iiment of Fig. 3 it is, as has reen rren" ic^-ed before, assnmied that the requested operatiin ccoe identifier ,-3 a free operation code identifier ref a jump comimicind with direct addressing and v-. ith retnrr intention. Ln step 630, the supporting mear.s 40, f i on; * ne address port ion contained in the free operation oo'.ie identifier, forms the 20-bit address tc which the iiew amp^ command is related and which is the destination adaress of the jump corrimand corresponding to the free operaticm -^de identifier. This step can, for example, also inclucie determining an offset value directly from another por' : c-n of the free operation code identifier or indirectly t r. cm a register internal or external to the CPU 3C and addinc it to the 20-bit address indicated in the address seci ic^r by the adder 320. The free operation code identifier, fc.: example, in(;:ludes a byte for the operation code ano tr^ree more bytes, of which 20 bits indicate the ^0-bit aadit-ss and the rerriaining four bits indicate the offset va;.ue. In step 635, the CPU 30 is fed the free operaticn oat- ov the supporting means 40 although the free cperatior. c. '.-a: does not be^ ong tC' the CPU operatic^n codes determir in^i ::.he command set 2 90. Step 635 is provided to ir.cremient tho- programi coar;ter 240 in the CPU to consider the fac' t f ^'the free op'^.-ration code identifier correspcnding t_ 11"- jump commani^ with direct 20-bit addressing, requir^f-s - bytes, while a CPU op)eration code identifier of i ", ALL command subsequently fed to the CPU 30 is only 3 bster long. Step 635 can, however, also be omitted whea c jump command without return intention is to take place, sitice the program counter status in this case is not :eqairec a- a return jump address. Step 635 can also be omi'.ted An^^n the stack 2 70 of the CPU 30 is described in ano'.her v. iv, as will be described subsequently referring t :-¦ the fcil;/v'ing step. In step 64:, the CPU 30 is fed, by the sup^porti-.g me.:.:..-.. 4 , a sequence of predetermined CPU operation 2ode identifier- including at least one jump command fromi tne coirtmano set 290 of the CPU 30, referring to a 16-bit address whiL'r. finally, together with the code descriptor 340, i.= t; give the 20-bit j umip address to be, for example, suitacl^ set for subsequent commiand requests according to steps 6' ; to 610. The sequence depends on the free operation c:.de and the 20-bit address determined fromi the internal registers. In step 65l, the CPU 30 decodes the sequence ot predetermiired CPU operation code identifiers ani exeLutes the corresponding commands. As is summed up in step '-':/), the sequence of CPU operation code identifiers is pn.video such that the CPU 30 when executing the sequence if 'TU operaticin code identifiers sets the program counter F: to the lower, i.e. less significant, 16 bits of the address determined from the internal registers, fill:: the stack 27C with a 20-bit address pcdnting to the op-eirition code identifier following the free operation cede identifier, and increases the stack pointer 230 b^^ ttiee bytes. Supporting means 40, in step 635, feeds the C n. 30 for example a jump command with return intention lettvirina to a 16-bit destination address corresponding ti an . tiset value of the 20-bit address determined from the a'adii-?;? portion in relation to the 64 kBytes bank containing rnis 20-bit addiess to set the program counter 240 t: * he .b-bst destination address, and subsequently, in step o4', . stach: filling con.mand (in the usual notation referrec tc a:- PUS.H commands) corresponding to the missing bits of the 1: -oit address to enter the 20-bit address of the operatiori ::ode identifier following the free operation cede iaentil..er into the stack 270. Or the supporting means 40 for exomple feeds the CPU 30, in step 635, a jump command vn th'.mt return mterition and then, in step 645, th:ee stac'i i.^Iin:: commands (iii the usual notation referred t-^ as PUS.i commands) respectively corresponding to a portion :f ¦ne 20-bit adar-.ss to enter the 20-bit address of t_'..,^ .p.--;": i. :. code identifier following the free operatiTi cC'.:e identifier into the stack 270. In step 660, the supporting means 40 performs ar. actualization or adaptation of the code descripv^or 34 ." based on the 20-bit address determined from the acdres- portion so that, subsequently, the code descripior 34, is set in sucr a way that the 20-bit address is contiine:! m the code memory window 370 and the program counter 24 0 points to the desired position within the code memory window 37 0. In this way, the supporting means 4'j manaaes the code descriptor 340. Corresponding to the free data accesses, the aavantaoe results in code jumps, by the present invention, tha" managing tfie code descriptor required due to the memc i _,• size maximally addressable for the CPU need not be ootained by software-resetting the code descriptor out that resetting can be obtained by a free operation coce identifier corresponding to a 20-bit jump commanc an; responds t-; the supporting means 40 in order t: feed rhe CPU 30 inf';)rmation relating to the 20-bit address an; at the same time update or adapt the code descripr oi . .'i particular m jumps with return intention in v;t.ic:"i in.- software expenditure for setting anew ana resetting ¦le code descriptor is very comiplicated, a ] ump fr^-e :)p-:;iticr; code identifier offers a considerable advantag-:-. In addition, che usage of jump commands frori' the 'Ommai. 1 set 290 still remains possible since the supp )rtiri'j mear.-j 40 is transparent for the CPU operation codes determining ire command set 290 and does not respond to tnem. The jump commands from the command set 290 are consequently executed with regard to the currently set or fixed memory wi'ioow 370. It is to be pointed out that, similarly to the a.ita accesses aescribed referring to Fig. 2, m coae ¦ um]: .'^ . t:^o, there are different possibilities for fortiing "h- .'_ ' -::it address t^: which the jump command is related, particular, a free operation code using indire'^t adur-:ss ing according :,o the embodiment of Fig. 2 is feasille. After the niode of operation of the controller cf V'ia i has been descrjbed hereinbefore relating to tne mooe cf operation -^'hen free operation codes relating tc code "'umps or data ac:;esses occur, special embodiments referr inu tc different possible variations and improvements jf th- simplified illustration hereinbefore will oe describeo. It can be provided to realize the commands executed t; .¦ the supporting means 40, to which the free opexatior coder are assigned, a;, atomic commands which cannot he interi/up-ed t::. the supporting means 40 by interrupt signals on zhi- interrupt line 90 by the CPU 30 or on the interrjpt i_;ne 130 by the MMU 50. In this case, the suppor-iing means stops incoming interrupt signals. Apart from that, it ..s als:. possible to use further free operation codes 31C in order to realize non-interruptible code sequences as aromic commands. Although it fas been described before that roth cne co^^e and the data memory window 370 and 380 have i siz-? .f 64 kBytes and that only one code and one dati des :ript'" - 330 and 340 must be managed in the MMU 50, i" cari a._sc ::- provided that the code memory window 370 and or ti.e la'\ -. memory windov; 380 are divided into several segments together resulting in 64 kBytes. Possible segment si;:es are, for exam^fle, 16 kE5ytes or 32 kBytes. In the cas^- c! a 32 kBytes segmtent size of the memory windows 370 and 38'. , ^wo data descriptors and two code descriptors would fe managed in the MMU 50. It could, for example, he pr;video to use one respective memory segment in relati-^n to tne ROM and XRAM memory areas and to use the respective othe: memory segment in relation to the EEPROM memory area. In 20-bit jumos, the two descriptors or only one v/ould oe adaptea automiatically. In a 32k program ¦:• unte: '/' 'e r '" . jw, i.e. excee ling the program counter 240 or 32k, the ;-!:-h 5^ would be incremented or decremented automiatica^.ly. '_-/erflow and underflow would also have to be dealt with corre;^ly for relative jumps. In relative jumps exiting ci segment, the program counter in the CPU is, for examiple, aiapced and the MMU descriptors are reset. When exiting the pcogiarri counter of a segment, a so-called auto-in':remer,te r, ine procedure :. s, for example, similar to tha' of lelative j umps. In additioii, it is possible that there are several bunks cf internal registers, such as, for example, the legLSt^^rs Rl to R3, and that when accessing or polling the contents of the registers Rl to R3 by the supporting means, as h^s been described hereinbefore, the bank just set is useo. Furthermiore, other internal registers of the CPU thar. the registers RX to R7, dadr and DPTR mentioned abcve car generally f^e used for indirect addressing. Referring t,c the previous description, it is tc b^^ p' ':.nted out that different modifications are possible as r-eg^rds the setup cf the controller of Fig. 1. Thus, it i:-., rcr example, not necessary that the MMU 50 anc the suppc.rting means 40 be separated fromi each other. The descriptC'rs and the stack extension can, for example, be nanaged L^y - he supporting means 40 or by means of it. When the supp- ii or programs using memory access commands or - umip c jmruarci.-: frirr! the commiano set 290 of the CPU 30 is omitted anl -ni', programs using free operation codes for code jump- ai.c data accesses are supported, the data descriptcr can bc- dispensed vvith completely. The advantage cf programs .:nly using 20-bit data access or jump commands is that fo; such programs, a continually addressable memory having a size cf 1 megabyte would be visible or addressable. In addit.ca, it is to be pc mted out that the setup of the CPU car. b*- formed difterently so that, for example, the ac.;uriui c-r .ir register 2^'l', the stack pointer 230 and the projrom > cunter 24 0 may be Tianaged in the IPAM 22 0. The I F.AM ca -. r-Is include an/ ither memiory type or any combmatiiins il ';iis, such as, for example, an NVM. In relation to the courses illustrated in Fig. . ana ", it is to be pC'._nted out that they may be changed as lega.-^s the order c[ the steps. Additionally and alternatively to the 20-bit cooe iumj command with, return intention (FCALL) described where.;, three bytes are put to the stack and the MMU is reconfigured automatically, a 20-bit code 3 ump CDmniam.: without return intention (FJMP) executed like the IID-bit FCALL jump described before but without storing the return jump data in the stack, may be provided. As an example, in all the 2u-bit jump commands with return option ^r ret ^rn intention, three bytes are written to the stack, where l-" the CPU return commands (RET) are provided such *hat -;nree bytes are ta-:en from the stack. Based on the bytes rake.n from the stack, the code descriptor could be brough" t the state before the last CALL command. For eadt interr ipt level, a separate context may be stored in crder no" t have to restore the old context when a return j uiT:p -cc.r.s, i.e. a returr jump command to the command set 2 90'. The previous embodiment of a controller thus solves se'.-eral problems v/hrc"! are based on using an architeiture sufficient as regards the processing speed bit m.ju.': f 11 :-nt as regards tne addressing capacity. The controlle: described nereinbefore allows a direct effic_ent ,.-iCc:es.T -. o data in an exjianded address space. In a special realization, r he access time is only two clock eye le.s longer than \u accesses to data in a currently set rriemoiv window. In addition, when using a mixed, both direct and indirect addressing, using, for example, tne daia po^'iter and a free section of the free operation code or:' rou: oits, by means of the 24-bit adder in the supporting .-necns, without changing the data pointer, several bytec •2'^ - 16 bytes ¦ of r.e ighboring data can be acce;ssea dire 't./ i , using the -right bits as an offset as regards tn-j: z. .ia i ¦:¦.-¦ s formed of the address portion of the free opera':i'_n (/ode and the data pointer. The code segmenting oy th~ MMU is thus made easier by the fact that the programmier noe.s ric longer have to explicitly reconfigure the MMU tj -xecute a code in a non-set memory window. Reconfiguring anc restoring take place automiatically by using 20-oit a ae jump and data access commands based on free operation codes so that the programmers sees the entire physica-_ address space of 1 MB as a linear addressable address soaie, wherein at the same time a down compatibility t :j c rcurams only basing on the command set of the CPU is maintairiea. For generic pointers, instead of the complicateij eofr ware- decoding, hardware-decoding is used enabling a zor.siaerably faster processing. Like in 20-bit data accesses, ever ^n handling generic pointers, an offset value froiri ar unused section of the free operation code identifier can be used to efficiently access consecutive data without ;:hang:ng a data pointer. In addition, the internal stack ranae ¦. an be extended b\ an external one and non-interruptibie ccae seguences can be realized as atomic commands. Tnese novelties and improvements are obtained by only Ijtt.t changes of an existing CPU layout by translatinri l rer operation lade identifiers into operation code ident.frer seguences and by modifying the CPU external con:;rri , ignals by supporting means or a shell which can fce exei-urec «;; a state machiine in such a way that the comimands, "ov. ai'":5 the outside, l:;k like the desired commands. In particular in the chip card area, the advantage ri-s-rlts by the present invention that a capability excess anc a code additional expenditure with the custcmer are mir^imized and chdt ct the same time an efficient ccmpiier ;-;up|:c.rt is obtained. As regards the MMU and the supporting means, i' _s l . be pointed ou~ that they can be realized as ^ unir. Finally, i "¦ is to be pornted out Lhat the present in\e.-itio: is further applicable to other controller archite:tuies than the SOU architecture mentioned above and '.hat, consequentl'^', the memory size indications as reaards \re memory window and of the memory and the byte-vjise readout and the numoer of address and data lines only iilustr-ite exemiplary examples. 1. A metnoi for controlling a central processir:g in l ¦ i3Ci for addressing in relation to a memory \2\'; , wher-r-iiii -x set of operati;:.'n code identifiers including at least me special oC'---ration code identifier is assc^. iate':; t ^ " -¦ central pr.:cessing unit ill;, wherein the central processina unit (30) is arranged to address a first niemory area (27C, 380) having a first memory size of tie men;cry (20), wherein the method comprises the foliowin;j stef.s: monitoring i615) a data traffic from the memory (30) \ :¦ the central processing unit {30} by supporting miean;-- 40' coupled tc the central processing unit (30 ; in the case in which the data traffic from the rremory 20)] to the cent], al processing unit (30) includes the spec-^al operation code identifier (310), formiing ^630) a new address by the supporting n.ear'.s (40), wherein the new address is defined in a secc^nd memiory area (20) having a second memory size of tTie memory ;'20), wherein the second memory size .. s larger than the first memory size; providiri^.; (645) a predetermined operation coce identif i t:;-r to which a jump command from a comimand ~et of the central processing unit (30) is assigned, t ^he central p.rocessing unit (30) by the supporting near.s (40), wherein the predetermined operation code identifier has a destination address in relat lot t-- t.he first merr : ry area (370, 380); and managing 660) a code descriptor (340) b/ the supportiri-j means (40), yielding, together with t ne destinati'jn address, the new address. 2. A controll':-! having:: a central processing unit (30) having a set o: rper at ion code identifiers (280, 310) including at leas" c ne special operation code identifier, wherein the centra^ procr:Ssing unit (30; is arranged tc address a first memory .^rt---; ,3'^0, 380) having a first memcry size of a mern'_ rv i 1 "' supportinc means (40) coupled to the central pro: es.': ing unit (30) to moriitor a data traffic from :he memiry tO) to the central processing unit (30), wherein the supporting means (40) is arrariged "o oer.-'jrm, in the case in which the data traffic fron. the memory [20' to the cent:ral processing unit (30) incluaes the spe^" lal operation code identifier (310), th€5 follcwing steps: forming a new address, wherein the; new address i^: definec in a second memory area (20) having a second memory size of the memory (20), wherei:. the se::orij memory area is larger than the first miemory area, and providing a predetermined operation coae ident.._ f a e-r" to which a jump command from a command set of tne cerjtral processing unit (30) is assigned, to the central processing unit (30), wherein the predetermii;iec operation code identifier has a destinaiion ._idaress in relation to the first memory area (370, 380;; and managing a code descriptor (340), yielding, together with the destination address, the new aadres5. 3. The contr.ller according to claim 2, wherein tne set ¦:)f operation ccce identifiers (280, 310) comprises a plurality of operaticn code identifiers, to which commiands irt-: associated determining the command set (290 ¦ of t!ie tentral processing unit (30), and wherein no command from, the command set (290) of the central processing unit 30 assigned to tne special operation code identifier (3iO,. . 4. The controller according to claim 2 or 3, f'.rtne- comprising: an externa.i register for storing the code descriptor, wherein tn^ external register is arranged exte;: .a - i \ r tne central p recessing unit '30,>, wherein the :-Gde ie-;r i ;: *: or is provide; to define the position of the tirst memoi/ area (370) within the second memory area (20,', wherein tne supporting means (40) is arranged tc pert rm, in the case that the data traffic from the memory ;o 'ne central prot'essing unit includes the special operatior code identifier, the following steps: setting a value of the code descriptor 340 i m sum a way that the new address is contained ir, the fitsr memory area, and setting the destination address in relation tj tne first memory area (370) in such a way that the destination address in relation to the first nemorv area (370' corresponds tc the new address in lelati )n to the second memory area. 5. The controller according to claim 4, further ccmpr^is j ng : a program courter (240) included in the central prjcessing unit (30), in which a code address in relation to -he first memory area (370) is stored; means (50' coupled to tne central processing -^nit 30 ::. order to monit.^r a data traffic from the central process, ng unit (30) tc the memory (20), and arranged to perform, i; the case that the data traffic from the central processir.c unit (30) to the memory (20) includes the code address ir relation to the first memory area, the following steps: descriptor (340) to obtain the ne-^- adaress ir re-at;icri to the second memory area (20); and passinc it on to the memory (20) in a rhang-rd fori m order t ¦: access the memory (20 5 . 6. The controller according to one of claims 2 i r.- \, wherein the central processing unit (30,i i.- arrana perform, responsive to the supplied predetermtine i '¦pe-_-::ic. code identiiier for requesting a next operation :oce identifier to be processed, the following steps: storing the destination address in a program count-: (240) of the central processing unit (S'^), ar d outputtirg it within the data traffic fromi the :en!rcil processing unit (30) to the memory (20). 7. The controller according to one of claim.s 2 to 6, wherein the central processing unit (30) further comprises a stack miemorv (270) and a stack memory pointer (13C' indicating a position in the stack memory l2^"0i wher*-- d,-:ta is currently taken from the stack memory (27r ¦ by the central processing unit (30) or addea to it, and wneieir the supporting means (40) is adapted to further provide j* least another predetermined operation code identif-er t the central pr:cessing unit (30), wherein a comananf; rrorr the command set of the central processing uni* (30 r :.r filling the st:ick mem.ory at the stack memory pointer wit ¦ value dependin>.; on a current address in relation tc the second memiory cziea at which the operation code identiiie; following the special operation code identifier is iiranje is assigned tc the at least one further operation c -d- ident i fier. 8. The controller according to one of claims 2 to &, wherein the des'ination address is a less significarr fjai • part of the new address. 9. A method for controlling a central proc^ssin.; uni" 30- for addressing in relation to a memory (20 , whe^rem -. set of operatio'i code identifiers includinq at leas' b. si.- ^a] operation c de identifier is assC'Ciated tc the _er,'r.T processing unit (30), wherein the central crocessing .i.Lt (30) is arranged to address a first memory area ;3"0, -'^u; having a fii"st memory size of the memory fiOi, wneiej: :;he method comprises the following steps: monitoring i420) a data traffic from the memory 2\. • t _ the central processing unit (30) and a data traffic -rom r •:- central processing unit (301 to the memiory 20) i-y supporting means (40) coupled to the centra^ processin ; unit (30); if the data i raffle from the memory (20) to the cen^. ra^ processing uriit \2Q) includes the special operation cooe identifier, forming i440) a new address by the supporting meant (40), wherein the new address is defined m a secor,;! memory area (20) having a second memory size '.-f th^^ memory ^2')], wherein the second memory size i.-- ^araer than the rirst memory size; providing ;445) a predetermined operation code identifief to which a command from the c>-_'mmanc set r the centr;;il processing unit (30) is assicned, tc th- central fi tcessing unit ',30) by the suppcrtinc mt-ar . (40); ano manipulating (455) an address defined in relat ^or- t. the first memory area (380), within the data t-^arfi. from the central processing unit (30) to the miemcry (20) based on the new address by the supporting mean^ relation to the second memory area. 10. A contrcller having: a central pricessmg unit i, 30i having a sen c-f .:;er-^ .¦¦: code identitLers i280, 310 j including at le.^st = Sf.-¦_; . ;. operation code identifier, wherein the central pi oc-es.; .rig unit (30) is arranged to address a first memory ores '0, 380) having i first memory size of a memory [20'; supporting m-eans (40) coupled to the centra.- prc:es-:iri ; unit (30, m order to monitor a data traffir frcn t!;e memory i20; - o the central processing unit 30) anc a -jaca traffic from the central processing unit (3C) to nh^.- memory (20) , wherein the supporting means is arranged to performi, ii. the case that the data traffic from the memory (20) t^ tne central processing unit (30) includes the special operation code identifier, the following steps: forming a new address, wherein the new addres.: _s defined in a second memory area (380) having u sec':.n3 memory size of the memory (20), wherein the se-ccid memory size is larger than the first memc-ry s:ze; providing a predetermined operation code identir^ei ^o which a command from the command set of the centra, processin'j unit (30) is associated, to trie certr.il proces3in>4 unit (30); and manipulating an address defined in relation t.. t!.e first memory area (380), within the data traftic t: ¦ u the central processing unit (30) to the memor\ i 1 0': based on t.he new address in order to obtain a manipulat€:d address in relation to the second Tieniory area. 11. The controller according to claim 10, wher-eir, tr.e set of operation code identifiers (280, 310) :ompr__ses .:= plurality of operation code identifiers t ;¦ whi :h :;oiTL:ridnds are assigned determining the command set 290 i of t r-^ central prjc:essing unit [30 i, and wherein no c mrnin.; i ;; on the commano set i290) of the central proc-essin': ^-il'. jG is associaced to the special operation code idr^nt if i-;r: (310) . 12. The controller according to claim 10 vr 12, v.-riei-iin thi predetermined operation code identifier i.- asscciate"i to a write or read command from the command se' (29') if -.ne central processing unit (30). 13. The controller according to one of claims -0 "o 1, wherein the command relates to an access address Ln relation to the first memory area (380) ccrresponiinq to a portion of the new address, and wherein the suf^porting means (40' is arranged to perform, when manipulating the address defined in relation to the first memor\ ared 380; within the data traffic from the central processing .nit (30) to the memory (20), the following step: supplementing it by a remaining portion of th-- ri^v. addres;;- . 14. The controller according to one of claims I'j ic - ¦ , wherein the command relates to an access address .. n relation t(. the first memory area (380), c:nd whereir: vne supporting means (40) is arranged to perfcrm, wne: manipulatii\q the address defined in relatzo-n t^: the ;irst memory arec: (380) within the data traffic from the- ct-noral processing unit to the memory (20), the fcilowing stt-f: replacing it by the new address. 15. The cor~;troller according to claim 13 cr 14, wrier^:-'^n the command fuither relates to an offset value, ana whiert.-:. t the supporting means (40) is arranged to add the offset ,aLue to the manipulated address. 16. The cortroller according to one of claims 1 "i further comprising: an external register for storing an address (33 ji, whereir. the external register is arranged externally of tte /entra^ processing unit (30), wherein this address (330 is provided to indicate a position of the first memory acea (380) wlthiri the second memory area (20); means (50) ,:oupled to the central processing un-t (3l' to monitor the data traffic from the central processing init to the memory (20) and arranged to perforrrt, in the case that the daia traffic from the central processirg mi'- (30 to the memory (20) includes an address defined m ::elcirion to the first memory area (380), the following steps: manipulating it based on the contents cf the exteinal register (330) to obtain a corresponding addre.'-s . r. relatior to the second memory area (20;, ana passing it on to the memiory (20) in a cnangei rori' ^o access the memory (20), and wherein tne supporting means (40) is arranged to performi, in the case that the data traffic from '.^he memory (20) to the central processing unit (30) inilude.:: '^ne special oper.ation code identifier, the following step: adapting the contents of the external register ;3- ; ir. such a way that the first memory area ( rSO) ¦'orica i ii.s the manipulated address, and in the case that the data traffic from the memory ^j) to the centrcil processing unit (30) includes an cpecar.on code identifier of the plurality of operation ccoe identifiers, to which a read or write command fr^'m ':h command set ',290) of the central processing unit ['i'J} ^.s associated, :o perform r.he following steps: passing it on to the central processing unit, ano leaving unchanged the address defined in relation " "; the first memory area, in the data traffic fro.T tfe central processing unit (30) to the memory 20 . 17. The controller according to claim 10, v;here:n '.he special operation code identifier corresponds tc a comiriana for handlin^ij a generic pointer, wherein the generi : pointer consists of an address indication and an addressing " /pe indication, wherein the address indication corresponos tc the new address, and wherein the addressing typ- :undi :ai;ion indicates fiat the address indication refers to the secona memory area. 18. The controller according to claim 17, wherein th^- supporting means (40) is arranged to perform, m the lase in which tlrie data traffic from the memory (20) zo th- central processing unit (30) includes a special cper,:.-tion code identifier corresponding to a cortimano for naiidl^ng a generic pointer consisting of an address indication .-.nd an addressing type indication, the following steps: checking the addressing type indication, in the case that the addressing type ..ndicr-.ri :)n indicates that the address indication refe:s tc. me second memory area, performing the format! ^n :jf i:.e new address, the supply of the predetermined ooeiat^iri cede identifier and the manipulation of the addreis, ::,nd 200108562 47 in the case that the addressing type indicat lor indicates that the address indication refers to, the first me-nory area, supplying the centra, processir, j unit wit'i an operation code identifier "o wh:ch a command from the command set (290) referring to ttir- address indication is associated. 19. The controller according to one of clairriS 2 to r d: o 10 to 18, wherein the central processing unit oO) comprj.;es at least an internal register (260) and the supporting means (40) is coupled to the central processing u lit i -C to determine the contents of the at least one internal register, and arranged to perform the foilov.'ing s-;eps wnen forming the new address: determining the contents of the at least one intern^., register, and forming the new address from the contenti of the at least one internal register. 20. The controller according to one of claims 2 to 8 ano LO to 18, comprising at least one external data pointer register (325) arranged externally of the central processing unit, and wherein the supporting means 4l) is arranged to perform the following steps when forming the new address: determinin>^j the contents of the at least cne externa _ data pointei register (325), and forming the new address from the contents of tte tt least one external data pointer register ¦325). 21. The controller according to one of claimis 2 to 8 dUd iO to 20, wherein the supporting means (40) is arranged to perform the following step when forming the new address: forming rhe new address at least partly from an aadress portion of the operation code identifier. 21. The controller according to claim 21, wnerei i the supporting means (40) is arranged to perform the fc LiC'W3.ng step when farming the new address at least parti/ tror the address portion of the operation code identifier: providirg the central processing unit i30) witt tt.e or another special operation code identifier, and wherein the central processing unit (30) comprises a program courter in which a code address in relation t> the first memory area is stored, and the central prccessma unit (30) i;r' arranged to perform the following steps: requesting a next operation code identifier to be processed by means of the code address, and increasing the program counter (240) responsive i: the special operation code identifier supplied t.o the central processing unit (30) and otherwise _^gnoring the special operation code identifier supplied 'o the central processing unit (30). 23. The controller according to one of claims 2 ti & and 10 to 22, wherein the supporting means (40) is arranged to perform, in the case in which the special operaticn i-cde identifier i310) is included in the data traffi : Iron the memory (20i to the central processing unit (30'^, rhe following step: stoppirg incoming interrupt signals. The present invention is based on the finding that free CPU operation code identifiers (310) of a CPU (30) or CPU operation code identifiers useable for any reason can be used to control supporting means (40) upstream of the CPU (30), which is able to form, responsive to these operation code identifiers (310), a new, for example, physical address in relation to a second memory area (20) having a second memory (5) which is larger than the, for example, logic memory size (370, 380) addressable by the CPU. By means of the special operation code identifiers (310), it is thus possible in the course of an executable machine code to address the supporting means (40) which monitors the data traffic via which the operation codes to be processed or the operation code identifiers are provided to the CPU (30), from the memory (20) to the CPU (30), and which can take measures in relation to the new formed address when certain special operation code identifiers (310) occur. In this way, on the one hand, a complicated redesign of the CPU (30) and, on the other hand, the necessity of a software-resetting of the current memory window (370, 380) complicated as regards both the executable machine code and the processing speed are avoided.

Documents:

102-kolnp-2004-abstract.pdf

102-kolnp-2004-claims.pdf

102-kolnp-2004-correspondence.pdf

102-kolnp-2004-description (complete).pdf

102-kolnp-2004-drawings.pdf

102-kolnp-2004-examination report.pdf

102-kolnp-2004-form 1.pdf

102-kolnp-2004-form 18.pdf

102-kolnp-2004-form 2.pdf

102-kolnp-2004-form 3.pdf

102-kolnp-2004-form 5.pdf

102-kolnp-2004-gpa.pdf

102-kolnp-2004-granted-abstract.pdf

102-kolnp-2004-granted-claims.pdf

102-kolnp-2004-granted-correspondence.pdf

102-kolnp-2004-granted-description (complete).pdf

102-kolnp-2004-granted-drawing.pdf

102-kolnp-2004-granted-examination report.pdf

102-kolnp-2004-granted-form 1.pdf

102-kolnp-2004-granted-form 18.pdf

102-kolnp-2004-granted-form 2.pdf

102-kolnp-2004-granted-form 3.pdf

102-kolnp-2004-granted-form 5.pdf

102-kolnp-2004-granted-gpa.pdf

102-kolnp-2004-granted-reply to examination report.pdf

102-kolnp-2004-granted-specification.pdf

102-kolnp-2004-granted-translated copy of priority document.pdf

102-kolnp-2004-reply to examination report.pdf

102-kolnp-2004-specification.pdf

102-kolnp-2004-translated copy of priority document.pdf