Title of Invention	APPARATUS AND METHOD FOR GENERATING AND DECODING FORWARD ERROR CORRECTION CODES HAVING VARIABLE RATE IN A HIGH-RATE WIRELESS DATA COMMUNICATION SYSTEM
Abstract	The invention relates to an apparatus for generating Quasi-Complementary Duo- Binary Turbo Codes (QC-DBTC), comprising a duo-binary turbo encoder (810) having a plurality of constituent encoders for receiving an information symbol stream (800), and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate, wherein the plurality of parity symbol streams are generated from the plurality of constituent encoders associated thereto and the parity symbol streams from one of the plurality of constituent encoders correspond to the parity symbol streams from another one of the plurality of constituent encoders; a quad-symbol mapper(630) for quad-mapping the plurality of systematic symbol streams to one symbol stream; a channel interleaver (816 a) for interleaving the quad-mapped systematic symbol stream and the plurality of parity symbol streams from the plurality of constituent encoders, quaddemapping the quad-mapped systematic symbol stream, interlacing symbol streams in the plurality of parity symbol streams corresponding to each other from among the interleaved parity symbol streams, and serial-concatenating the quaddemapped systematic symbol stream and the interlaced parity symbol streams; and a duo-binary turbo code generator (822) for repeating the serial-concatenated symbol stream, and selecting a predetermined number of symbol streams from the repeated symbol streams according to the given code rate and selection information thereby generating QC-DBTC codes.

Title of Invention

APPARATUS AND METHOD FOR GENERATING AND DECODING FORWARD ERROR CORRECTION CODES HAVING VARIABLE RATE IN A HIGH-RATE WIRELESS DATA COMMUNICATION SYSTEM

Abstract

The invention relates to an apparatus for generating Quasi-Complementary Duo- Binary Turbo Codes (QC-DBTC), comprising a duo-binary turbo encoder (810) having a plurality of constituent encoders for receiving an information symbol stream (800), and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate, wherein the plurality of parity symbol streams are generated from the plurality of constituent encoders associated thereto and the parity symbol streams from one of the plurality of constituent encoders correspond to the parity symbol streams from another one of the plurality of constituent encoders; a quad-symbol mapper(630) for quad-mapping the plurality of systematic symbol streams to one symbol stream; a channel interleaver (816 a) for interleaving the quad-mapped systematic symbol stream and the plurality of parity symbol streams from the plurality of constituent encoders, quaddemapping the quad-mapped systematic symbol stream, interlacing symbol streams in the plurality of parity symbol streams corresponding to each other from among the interleaved parity symbol streams, and serial-concatenating the quaddemapped systematic symbol stream and the interlaced parity symbol streams; and a duo-binary turbo code generator (822) for repeating the serial-concatenated symbol stream, and selecting a predetermined number of symbol streams from the repeated symbol streams according to the given code rate and selection information thereby generating QC-DBTC codes.

Full Text	BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates generally to an apparatus and method for generating Forward Error Correction (FEC) codes in a wireless data communication system. More particularly, the present invention relates to an apparatus and method for generating FEC codes having a variable rate. Description of the Related Art: In general, wireless data communication systems are classified as a Mobile Communication System (MCS), Wireless Local Area Network (WLAN), Wide Area Network (WAN) or Metropolitan Area Network (MAN), all of which are based on mobile communication technology. For the Mobile Communication System, systems for high-speed data transmission are also being developed independently by 3rd Generation Partnership Project-2 (3GPP2), a standardization group for a synchronous Code Division Multiple Access (CDMA) mobile communication system, and 3rd Generation Partnership Project (3GPP), a standardization group for an asynchronous Universal Mobile Telecommunications System (UMTS) mobile communication system. Also, for WLAN, WAN and MAN, various attempts are also being made to transmit radio data at a high rate in the area of IEEE 802.11 to IEEE 802.16 standardization. A description will now be made of Adaptive Modulation & Coding (AMC) as attempted in the foregoing communication standards. Also, a description will be made of an IEEE 802.16a system, a CDMA2000 1x EV-DV (Evolution with Data and Voice) system based on the CDMA mobile communication system, and a High speed Portable Internet (HPi) system currently being developed in South Korea for high-speed data transmission in a 2.4 GHz band, all of which comprise the most substantially advanced systems in the related technical field. First, an IEEE 802.16a system will be described. The IEEE 802.16a system is a system using Orthogonal Frequency Division Multiple Access (OFDMA). FIG. 1 is a block diagram illustrating the structures of physical channels for transmitting high-rate data in an IEEE 802.16a system using Orthogonal Frequency Division Multiplexing (OFDM). Referring to FIG. 1, all of the physical channels transmitted to users Userl, User2, •••, Userm have the same structure. Therefore, in FIG. 1, the same elements are assigned the same reference numerals, and different letters such as a, b, •••, m are added to the ends of the reference numerals as indicators for indicating the respective users and their associated physical channels. Parameters used in the physical channels for the users Userl, User2, •••, Userm can have either the same values or different values. For example, the respective physical channels can be different from one another in input packet size, code rate, modulation order and transmission duration. A description will now be made of a physical channel for a first user Userl, by way of example. In a physical channel, data Userl_Data to be transmitted to a first user Userl is input to a Cyclic Redundancy Check (CRC) adder 101a, and the CRC adder 101a adds a CRC to the input user data Userl_Data so that a reception side can detect an error occurring due to noises in a channel transmission process. The CRC-added user data is input to a tail bit adder 103a, and the tail bit adder 103a adds tail bits to the CRC-added user data. The CRC is an error correction code used for correcting an error occurring due to noises in a channel transmission process, and is generally used for Forward Error Correction (FEC). Generally, convolutional codes or turbo codes are used for the FEC used in a wireless communication system. These codes use tail bits which are termination bits for terminating the corresponding codes at a '0' state on a trellis diagram. Therefore, the tail bit-added data is FEC-encoded by an FEC encoder 105a. As this is well disclosed in the related references, a detailed description thereof will be omitted herein. Next, in order to match the number of output signals of the FEC encoder 105a to the number of modulation symbols allocated to each user, a symbol repetition & puncturing part 107a performs symbol repeating and puncturing on the FEC-encoded data. The symbols that underwent repetition and puncturing are input to a channel interleaver 109a for converting a burst error occurring in the channel into a random error, and the channel interleaver 109a channel-interleaves the input symbols. The channel- interleaved symbols are input to a modulator 111a, and the modulator 111a modulates the channel-interleaved symbols. The modulated symbols are input to a subcarner or subchannel mapper and an NOS or NOOS mapper 120. The subcarrier or subchannel mapper and the NOS or NOOS mapper 120 performs subcarrier or subchannel mapping, and NOS (Number of Slots) or NOOS (Number of OFDM Symbols) mapping on the modulated symbols for a transmission duration allocated to each user. The subcarrier or subchannel mapper and the NOS or NOOS mapper 120 simultaneously processes data for all users. The symbols output from the subcarrier or subchannel mapper and the NOS or NOOS mapper 120 are input to an inverse fast Fourier transform (IFFT) 130, and the IFFT 130 performs inverse fast Fourier transform on the input symbols. In this way, data for each user is converted into one carrier signal and delivered to a radio frequency (RF) unit (not shown). In the foregoing description, "NOS" or "NOOS" designates a transmission duration allocated to each user, and is variable according to a size of user data. Therefore, an increase in NOS or NOOS causes an increase in transmission time allocated to one packet. In addition, "subchannel" designates a set of subcarriers used in Orthogonal Frequency Division Multiplexing (OFDM). It is not necessary that the subcarriers constituting one subchannel should always be arranged in a regular sequence in a frequency domain, and it is typical that multiple subcarriers constitute one subchannel according to a particular pattern. For example, when a given frequency bandwidth is divided into 2048 orthogonal frequencies, if there are 1st to 2048th subcarriers, one subchannel can be configured with 4 subcarriers of 1st, 8th, 16th, 32nd and 64th subcarriers. The configuration of a subchannel and the number of subcarriers constituting the subchannel are subject to change according to standards. FIG. 2 is a block diagram illustrating structures of physical channels for transmitting data to a user in a current HPi high-rate data system. FIG. 2 is substantially identical in structure to that of FIG. 1 except that the structure of FIG. 2 does not add CRC and tail bits. This is because the CRC function can be performed in a Medium Access Control (MAC) layer. Therefore, elements 205r 207. 209, 211. 220 and 230 in FIG. 2 correspond to the elements 105, 10". 109. Ill, 12'-' and 130 ^ FIG. 1, respectively. When the structures of both l-'IGs. 1 and 2 have multiple modulators and multiple FF.C code rates, they require a scheme for determining a code rate and a modulation order for guaranteeing each user the best performance. As illustrated in FIGs. 1 and 2, in a physical channel for a packet transmission service, a modulator is necessary. In addition, FEC codes are used in order to overcome data errors caused by noises occurring in a radio communication channel. However, in the current physical channel for a packet transmission service, FEC codes with a fixed rale are generally used and in particular, the best codes for a given rate are used. This is because the physical channel for a packet transmission service has a characteristic of a stationary channel, such as an Additive White Gaussian Noise (AWGN) channel. Therefore, there is less necessity to take the FEC codes using an adaptive rate into consideration. For example, IEEE 802.16a, a high-rate wireless data sen ice standard, does not guarantee mobility of a mobile station and uses only 6 FEC code rates. A detailed description of the standard is well disclosed in the IEEE 802.16a physical channel standard, the entire contents of which are incorporated herein by reference. While the mobile communication system uses binary turbo codes, the IEEE 802.16a uses duo-binary turbo codes. The duo-binary turbo codes will now be described in greater detail. FIG. 3 is a block diagram illustrating an apparatus for generating rate R=l:2 duo-binary turbo codes, and F-TG. 4 is a block diagram illustrating an apparatus for generating R=1/3 duo-binary turbo codes. As illustrated in FIG. 3, an R-l/2 duo-binary turbo encoder receives 2 information symbols A and B in parallel. The 2 information symbols A and B received in parallel are input in common to a first constituent encoder 301 and a turbo interleaver 302. The turbo interleaver 302 interleaves the 2 parallel input information symbols A and B. and outputs the interleaved information symbols to a second constituent encoder 30?. The 2 parallel input information symbols A and B are output intact as systemic symbols, and the first constituent encoder 301 and the second constituent encoder 3'>3 generate parity symbols CI and C2. respectively, using the 2 input information symbols A and B. As a result, the 2 input information symbols are output intact as systematic svmbols. and each constituent encoder generates one parity symbol. Therefore, a code rate of the encoder is 1 2. An R=I 3 duo-binary turbo encoder of FIG. 4 receives 2 information symbols A and B in parallel. The 2 parallel input information symbols A and B are input in common to a first constituent encoder 401 and a turbo interleave!' 402. The turbo interleaver 402 interleaves the 2 parallel input information symbols A and B, and outputs the interlca\ed information symbols to a second constituent encoder 403. The 2 parallel input information symbols A and B are output intact as systematic symbols, and the first constituent encoder 401 and the second constituent encoder 403 generate parity symbol pairs C1UCI2 and C21;C22, respectively, using the 2 input information symbols A and B. As a result, the 2 input information symbols are output intact as systematic symbols, and each constituent encoder generates two parity symbols. Therefore, a code rate of (lie encoder is 1.3. A description will now be made of an encoding method performed in the duo- binary turbo encoders of FIGs. 3 and 4. It will be assumed that a si^e of an information symbol to be encoded is Nf F.P. and K FP/2 information symbol pairs that are generated by halving the size N_EP information symbol are denoted by A i and B i (wherein i-0, I,---, N_EP:2), respectively. In this case, the duo-binary turbo encoder encodes a symbol pair A_i and B_i by a first constituent encoder 301 (or 401) and outputs a parity symbol Cl (or a parity symbol pair CI 1;C12) as the encoding result. Next, the turbo inlerleaver 302 (or 402) interleaves the N_EP.'2 information symbol pairs A i and B i. and outputs the interleaved information symbol pairs to a second constituent encoder 303 (or 403). The second constituent encoder 303 (or 403) encodes the input information symbol pairs, and outputs a parity symbol C2 (or a parity symbol pair C21 ;C22) as the encoding result. As a result, for N l:P input information symbols, the R-I/2 duo-binary turbo encoder outputs 2\N_EP codeword symbols and the R-1-3 duo-binary turbo encoder outputs 3N_EP codeword symbols. It is generally known to those skilled in the art that the duo-binary turbo codes are slightly superior to the binary turbo codes in performance gain at a high code rate When compared with the binary turbo codes whose information symbol size is N_EP, the duo-binary turbo codes whose information symbol side is also N EP. are reduced to 1.2 in trellis length, that is. frame length, contributing lo a 1 2 reduction in decoding delay. Disadvantageously , however, the duo-binary turbo codes are inferior lo the binary turbo codes in performance at a lower code rale. In addition, the duo-binary turbo codes are higher than the binary turbo codes in terms of decoding complexity, because 4 branches arc used for each state in a trellis diagram. However. CDMA2000 Ix EV-DY (Evolution with Data and Voice,), a synchronous mobile communication standard, guarantees mobility of a mobile station. For a system lo guarantee mobility, not only should data error caused by noises occurring in a wireless communication channel be taken into consideration, but also various schemes for overcoming a data error caused by fading should be taken into consideration. For example, in order for a transmitter to actively cope with a dynamic change in signal-to-noise ratio tSNR) occurring in a fading channel environment, a packet modulation scheme of transmitting the same transmission packet at all times and an AMC scheme of varying a code rate of FEC codes are extensively considered. For example, in CD.MA2000 lx FA'-DV, Quasi-Complementary Turbo Codes (QCTC) are used for a physical channel as a scheme for freely supporting a variable code rate. The QCTC designates a set of turbo codes with various code rates selected by a symbol selector after code symbols, encoded from a given mother code according lo a specific rule, are rearranged as shown in FIG. 5. With reference to FIG. 5, a description will now be made of an operation of QCTC selected as a standard for a CDMA2000 lx FA'-DV system. When an information stream 500 is input to a turbo encoder 510 having a rate R=l.-5, the turbo encoder 510 performs turbo coding on N_EP input information symbols using a mother code. As a result, the turbo encoder 510 generates 5xN_EP code symbols. The generated code symbols are demultiplexed into 5 sub-blocks by a code symbol separator 512. The separated code symbols are denoted by reference numeral 514. The code symbols 514 are divided into a systematic symbol group (or sub-block X) and a plurality of parity symbol groups (or sub-blocks Y0, Yl, Y'O and Y'l). The respective symbol groups undergo Partial Bit Reversal Order (PBRO) interleaving. Here, the respective sub-blocks undergo independent interleaving. This is called "sub-block interleaving." Reference numerals 516a, 516b, 516c, 516d and 516e denote independent devices for performing the PBRO interleaving. Among the PBRO-interleaved symbols, systematic symbols are output intact, and the PBRO-interleaved parity symbols are interlacedly rearranged by interlacers 518a and 518b. The rearrangement is achieved in such a manner that two symbols are interlaced once. That is, the interlacer 518a forms a new group by interlacing parity symbols Y0 and Y'O. Similarly, the interlacer 518b interlacedly rearranges parity symbols Yl and Y'l generated in each sub-block, thereby forming a new group. Therefore, each group generated by interlacing has a size of 2xN_EP. Next, the sub-block comprised of interleaved systematic symbols and the 2 interlaced parity groups are arranged in a regular order and then concatenated, thus generating one new sequence. Here, this operation is denoted by "QCTC Symbols" and reference numeral 520. Through a series of the processes described above, symbol rearrangement for generating QCTC codes is completed. Next, a QCTC symbol selector 522 generates QCTC codes having various code rates by selecting random symbols from 5xN_EP symbols. A conventional binary QCTC design criteria is to take performance improvements of a received signal in a fading channel into consideration. The QCTC design criteria are characterized by optimizing not only code performance, but also channel interleaving performance. The channel interleaving is generally achieved by sub-block interleaving and interlacing. According to the current HPi standard, there are some 120 possible different combinations of modulation schemes and FEC code rates. However, there is no proposed scheme lor genc.ating and determining FEC codes supporting the possible combinations, that is. turbo codes having various code rates. Particularly an OFDM OFDMA svstem has no proposed method for varying an FEC code rate according to a relation between, a modulation scheme and an FEC code rate corresponding to each data rate. In addition, when Hybrid Automatic Repeat Request (HARQj is used, there is no proposed scheme for generating various redundancies. For the binary turbo codes used in a mobile communication system, that is, binary turbo codes defined in the CDMA2000 Ix F.V-DY standard, QCTC has been proposed as a scheme for providing various codes in the foregoing environments. However, QCTC is basically optimized for binary turbo codes. Therefore, separate optimization is required when non-binary turbo codes such as duo-binary turbo codes are used as mother codes. In particular, the use of the duo-binary turbo codes requires symbol classification and interleaving in which a characteristic of systematic symbols are taken into consideration. Accordingly, a need exists for an apparatus and method for generating desired codes and for decoding the desired codes in a high-rate wireless data system. SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide an apparatus and method for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC). and an apparatus and method for decoding the QC-DBTC codes in a high-rate wireless data system in which various packet sizes are used for data transmission. It is another object of the present invention to provide an apparatus and method for generating duo-binary turbo codes having various code rates, and an apparatus and method for decoding the duo-binary turbo codes in an OFDMA high-rate wireless packet data communication system in which HARQ is used. It is another object of the present invention to provide an apparatus and method for generating duo-binary turbo codes, and an apparatus and method for decoding the duo-binary turbo codes in an OFDMA high-rale wireless packet th.ua communication svstem in which various packet sizes arc used, and wherein one of multiple modulation schemes and one of multiple FEC coding schemes are selected according to a channel stale, a buffer state, the number of available subchannels (or subcarriersi, the number of OFDM symbols, and a transmission duration. In accordance with a first aspect of the present invention, there is provided an apparatus for generating subpackets. The apparatus comprises a encoder for encoding information symbols, wherein the information symbols are fed alternatively to two input ports of the encoder; a symbol separator for demultiplexing all of the encoded symbols into two systematic symbol sunblocks and two pairs of parity symbol subblocks; a channel interleaver for separately interleaving the subblocks; a symbol group generator for generating the first symbol-by-symbol multiplexed sequence of one pair of the interleaved parity symbol subblocks, the second symbol-by-symbol multiplexed sequence of another pair of the interleaved parity symbol subblocks and two systematic sequences of two interleaved systematic symbol subblocks: and a symbol selector for selecting a predetermined number of symbols from the two systematic sequences, the first symbol-by-symbol multiplexed sequence and the second symbol-hy-syinbol multiplexed sequence . In accordance with a second aspect of the present invention, there is provided a method for generating subpackets. The method comprises the steps of: encoding information symbols, wherein the information symbols are fed alternatively to two input ports of an encoder; demultiplexing all of the encoded symbols into two systematic symbol subblocks and two pairs of parity symbol subblocks; separately interleaving the subblocks; generating the first symbol-by-symbol multiplexed sequence of one pair of the interleaved parity symbol subblocks, the second symbol-by-symbol multiplexed sequence of another pair of the interleaved parity symbol subblocks and two systematic sequences of two interleaved systematic symbol subblocks; and selecting a predetermined number of symbols from (he two systematic sequences, the first symbol- by-symbol multiplexed sequence and the second symbol-by-symbol multiplexed sequence. In accordance with a third aspect of the present invention, there is provided an apparatus for generating Quasi-Complementary Duo-Binary Turbo ('odes (QC-DBTO. The apparatus comprises a duo-binary turbo encoder having a plurality of constituent encoders for receiving an information symbol stream, and lor generating a plurality or systematic symbol streams and a plurality ol"parity symbol streams according to a given code rate, wherein the parity symbol streams are generated from the constituent encoders associated thereto and the parity symbol si reams from one of the constituent encoders correspond to the parity symbol streams from another one of the constituent encoders; a quad-symbol mapper for quad-mapping the systematic symbol streams to one symbol stream; a channel interleaver for independently interleaving the quad-mapped systematic symbol stream and the parity symbol streams from the constituent encoders, quad- demapping the quad-mapped systematic symbol stream, interlacing symbols in the parity symbol streams corresponding to each other from among Ihe interleaved parity symbol streams, and serial-concatenating the quad-demapped systematic symbol stream lo the interlaced parity symbol streams; and a duo-binary turbo code generator for repeating Ihe serial-concatenated symbol stream, and for selecting a predetermined number of symbols from the repeated symbol stream according to a code rale and selection information thereby generating QC-DBTC codes. In accordance with a fourth aspect of the present invention, there is provided a method for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC). The method comprises the steps of: receiving an information symbol stream and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate; separating the generated symbol streams into systematic symbol streams and parity symbol streams; quad-mapping the separated systematic symbol streams to one symbol stream; independently interleaving the quad- mapped symbol stream and the parity symbol streams; quad-demapping the interleaved systematic symbol stream, interlacing the parity symbol streams in pairs; concatenating the interlaced parity symbol streams lo the quad-demapped systematic symbol stream; and selecting symbols to be transmitted according to a given data rate from ihe concatenated symbols. I:i accordance with a f'lKh aspect oi"th.- present invention, there is provided an apparatus tor generating code symbols by encoding an informal ion symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code (QC-DBTC) encoder and, selecting all or some of die code symbols lo be transmitted from among the generated code symbols. The apparatus comprises a QC-DBTC encoder lor receiving an information symbol stream and generating QC-DlifC symbols according to a predetermined code rate: a separator for separating output symbols of (he QC-DBTC encoder into a plurality of systematic symbol streams and a plurality of parity s\nibol streams, the systematic symbol sLreams being connected into one symbol stream; a plurality of inlerleavers for independently interleaving the parity symbol streams; a systematic symbol stream interleave!' for interleaving the connected systematic symbol stream; an interlaeer for interlacing the parity symbol streams in pairs; a concatcnator for serial-concatenating an output of the systematic symbol stream intcrleaver to an output of the interlaeer; and a symbol selector for selecting symbols to be transmitted according to a given data rate from the concatenated symbols. In accordance with a sixth aspect of the present invention, there is provided a method for generating code symbols by encoding an information symbol stream according lo a given code rate using a Quasi-Complementary Duo-Binary Turbo Code (QC-DBTC) encoder and selecting all or some of the code symbols to be transmitted from among the generated code symbols. The method comprises the steps of receiving an information symbol stream and generating QC-DBTC symbols according to a predetermined code rate; separating output symbols of the QC-DBTC encoder into a plurality of systematic symbol streams and a plurality of parity symbol streams, the systematic symbol streams being connected into one symbol stream; independently interleaving the parity symbol streams; interleaving the connected systematic symbol stream; interlacing the parity symbol streams in pairs; serial-concatenating the interleaved systematic symbol stream to the interlaced parity symbol streams; and selecting symbols to be transmitted according to a given data rate from the concatenated symbols. In accordance with a seventh aspect of the present invention, there is provided ail apparaius lor generating code symbols by encoding an in formation symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code (QC-DBTC) encoder and selecting all or some of the code symbols to be transmitted from among the generated code symbols. The apparatus comprises a QC-DBTC encoder having a plurality ct" constituent encoders for receiving an information symbol si ream, and for generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate, wherein the parity symbol streams arc generated from the constituent encoders associated thereto and the parity symbol streams from one of the constituent encoders correspond to the parity symbol streams from another one of the constituent encoders; a separator for separating a;i output of the QC- DBTC encoder into systematic symbol streams and parity symbol streams; a plurality of interleavers for independently interleaving the systematic symbol streams and the parity symbol streams; an imerlacer for interlacing in pairs, the parity symbol pairs generated from different constituent encoders; a concatenator for serial-concatenating the interleaved systematic symbol streams to the interlaced parity symbol streams; and a symbol selector for selecting symbols to be transmitted according to a given data rate from the concatenated symbols. In accordance with an eighth aspect of the present invention, there is provided a method for generating code symbols by encoding an information symbol stream according to a given code rale using a Quasi-Complementary Duo-Binar\ Turbo Code (QC-DBTC) encoder and selecting all or some of the code symbols to be transmitted from among the generated code symbols. The method comprises the steps of receiving, by the QC-DBTC encoder, the an information symbol stream, and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate, wherein the parity symbol streams arc generated from the constituent encoders associated thereto and the parity symbol streams from one of the constituent encoders correspond to the parity symbol streams from another one of the constituent encoders; separating an output of the QC-DBTC encoder into systematic symbol streams and parity symbol streams; independently interleaving the systematic symbol streams and the parity symbol streams; interlacing the parity symbol pairs in pairs; concatenating the interleaved systematic symbol streams to the interlaced parity symbol streams; and selecting symbols to bo trans mined according to a given data rate, from the concatenated symbols. In accordance with a ninth aspect of the present invention, there is provided an apparatus for decoding all or some of the received code s\mbois generated by encoding an information symbol stream according to a gi\en code rale using a Quasi- Complementary Duo-Binary Turbo Code (QC-DBTC) encoder. The apparatus comprises a selector for inserting a predetermined code symbol in a position corresponding to a punctured symbol among received symbols; a deinlerlacer for deinlcrlacing parity symbols among the symbols generated by the selector; a quad-symbol mapper for quad- mapping systematic symbols among the symbols generated by the selector; a plurality of deinlerleavers for independently deinterlcaving the quad-mapped systematic symbol streams and the deintcrlaced parity symbol streams; a quad-symbol dernapper for quad- demapping the deiuterleaved systematic symbol stream; a code symbol concatcnator for concatenating an output of the quad-symbol dernapper to the deiuterleaved parity symbol streams; and a QC-DBTC decoder for QC-DBTC decoding the concatenated symbol streams. BRIEF DESCRIPTION OF THeIdRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which: FIG. I is a block diagram illustrating structures of physical channels for transmitting high-rate data to a user in an 1EEH 802.16a system using Orthogonal Frequency Division Multiplexing (OFDM); FIG. 2 is a block diagram illustrating structures of physical channels for transmitting data to a user in a current HPi high-rate data system; FIG. 3 is a block diagram illustrating an apparatus for generating rate R¦¦-1/2 duo-binary turbo codes; FIG. 4 is a block diagram illustrating an apparatus for generating R=1.3 duo- binary turbo codes; FIG. 5 is a block diagram illustrating a QCTC symbol generator it: a CDMA2U00 lxEV-DYs> stern: FIG. 6 i.s a block diagram illustrating a structure of a QC-DBTC encoder having a code rate R-1 3 and using duo-binary turbo codes according to an embodiment of the present invention.; FIG. 7 is a block diagram illustrating a structure of a receiver in a QC-DBTC system according to an embodiment of the present invention; F!G 8 is a block diagram illustrating a structure of a transmitter in a QC-DBTC system according to another embodiment of the present invention; and FIG 9 is a block diagram illustrating a structure of a transmitter in a QC-DBTC system according to another embodiment of the present invention. Throughout the drawings, like reference numerals will be understood to refer to like parts, components and structures. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Several exemplary embodiments of the present invention will now be described in detail with reference to the annexed drawings. In the following description, a detailed description of known functions and configurations incorporated herein has been omitted for conciseness. FIG. 6 is a block diagram illustrating a structure of a QC-DBTC encoder having a code rate R=l/3 and using duo-binary turbo codes according to an embodiment ol'the present invention. With reference to FIG. 6, a detailed description will now be made of a structure and operation of a QC-DBTC encoder having a code rate R-l/3 and using duo- binary turbo codes according to an embodiment of the present invention. In FIG. 6. a turbo encoder 610 is substantially identical in structure to that of the turbo encoder described with reference to FIG. 4. FIG. 4 is a block diagram illustrating an apparatus for generating R 1 \3 duo-binary turbo codes. Therefore, an internal structure of the turbo encoder 610 will be described with reference to FIG. 4. The QC-DBTC encoder illustrated in FIG. 6 is similar in structure to a conventional QCTC encoder using binary turbo codes except for the inclusion or" a process of processing .systematic symbols. This is required because in the case of diie- binary turbo codes, as illustrated in FIGs. 3 and 4, N_EP systematic symbols are divided into systematic symbol streams A and B. each comprised of N HP Z systematic symbols. Respective symbols A i and B 1 are encoded in pairs by a first constituent encoder 401. or encoded in pairs by a second constituent encoder 403 after being turbo-interleaved by a turbo interleave!" 402. That is, each of information stream pairs A and B is defined as an information stream pair defined by one transition process on a trellis diagram of each constituent encoder, and a size of the symbol streams is defined as N_EP.'2. Therefore, the QC-DBTC encoder receiving the information stream pairs performs symbol classification based on the symbol pairs A i and B_i as illustrated in FIG 6. Thai is, A_ i and B i are mapped to quad-symbols before being block-interleaved. The encoding process will now be described in detail. For convenience, the description will be made herein with reference lo rale R=l 3 duo-binary turbo codes. However, the encoding process can also be applied to duo-binary turbo codes having a code rate I."2 or other code rales without a change in structure or encoding scheme of the duo-binary turbo codes. The change in code rate simply increases the number of parity symbol groups so that the code rate is reduced. Jfncodinu Process Step I: Output Symbol Classification of Duo-Binarv Turbo Codes Referring lo FIG 6, the turbo encoder 610 using R-l. 3 duo-binary turbo codes as mother codes, performs turbo coding on N_EP input information symbols. The turbo coding process is substantially identical to the conventional duo-binary turbo coding process. Therefore, the duo-binary turbo encoder 610 generates 3xN__EP code symbols. Reference numeral 612 shows a process of separating output symbols of the duo-binary turbo encoder 610 into systematic symbols and parity symbols, and then concatenating the separated symbols. Among the code symbols generated in this manner, systematic symbols are divided into two systematic symbol streams A and B, each comprised of N_HP.'2 symbols, and parity symbols are divided into four parity symbol streams CI 1, CI2, C21 and C22, each comprised of N_EP/2 symbols, as illustrated in FIG. 6. It can be noled that the number of sub-blocks of systematic symbols in the QC-DBTC coding scheme is higher by one than in the conventional QCTC coding scheme of FIG. 5 A mapping relation of the input systematic symbols wil[ now be described. If input systematic sunbols are denoted by S(,k) (wherein k"0. 1. 2. 3.--. N HP-1), A i and B i arc defined as in equation (1) and Equation (2). respectively, shown below. Step 2: Ouad-Svmbol Mapping of Systematic Symbols As illustrated in FIG. 6. the systematic symbol streams A and B are mapped to quad-symbols in accordance with a quad-symbol mapping table described in greater detail below. The quad-symbol mapping is performed by a quad-symbol mapper 630 in such a manner that A i and B_i arc mapped to m i (wherein i" (). 1, 2,--, K EP/2-1). This is equivalent to calculating A i and B i in accordance with liquation (1) and Equation (2). Therefore, a newly generated systematic symbol stream M has a si/e of N_EP 2. There are various possible mapping rules between A i, B_i, and mi. Herein, a mapping rule for mapping A_i and B_i to mi by binary expression will be used as a typical example of the possible mapping rules. Regardless of the mapping rule used, it is important that the new systematic symbol stream M has a si/e of N_ FP.-2 by quad- symbol mapping like the conventional binary QCTC', and that each quad-symbol is mapped to an i"! systematic symbol pair A i and B_i. A quad-symbol mapping table is illustrated below in Table 1. Step 3: Classification of Parity Symbols Next, the code symbols arc separated into a systematic symbol group (or sub- block M) and a plurality of parity symbol groups (or sub-blocks YO, VI. Y'O. and Y'l), and then demultiplexed into 5 sub-blocks. Here, this operation is defined as '"code symbol separation", and is denoted by reference numeral 614 in FIG. 6. The code symbol separator 614 is substantially identical in operation to the conventional QCTC symbol separator 514. An operation performed by the code symbol separator 614 can be expressed as in Equation (3) to Equation (6) shown below. Step 4: Sub-block Interleaving and Interlacing Next, the respective sub-blocks undergo independent interleaving, and this is called '"sub-block interleaving". The sub-block interleaving is achieved by (he PBRO intcrlcavers 616a. 616b, 616c, 616d, and 616e. Here, all of the sub-blocks have the same size of NEP.-2. Subsequently, parity symbols YO and Y'O generated in each sub-block are interlaced and then rearranged, generating a new group. Similarly, parity symbol Yl and Y'l generated in each sub-block arc also interlaced and then rearranged, generating a new group. Here, each of (he groups, or parity symbol streams, has a size o'\ N FP Z. The interlacing is achieved b\ interlacers 61 Sa and 6i Sb. Step 5: Quad-Symbol Inverse Mapping of Systematic Symbols Next. N F.P--2 systematic symbols are calculated from a systematic symbol stream M' newly generated by sub-block interleaving, by demapping (inverse-mapping) a quad-symbol back to binary symbols A i' and B i' in accordance with Table 1. Referring to Table 1, A i and B i can be regarded as A_i' and B_i\ respectively, for example, m_i=3 is mapped to (A i. B_i)~(l,l). As described above, there are various possible mapping rules, and the present invention has no limitation on the mapping rules. The mapping of m_i can be expressed as in Equation (7) below. The quad-demapping in accordance with Equation (7; or other methods is achieved by a quad-symbol demapper 640. Step 6: QC-DBTC Symbol Concatenation Next, a sub-block comprised of interleaved systematic symbols and 2 interlaced parity groups are rearranged in a regular order and then concatenated, thus generating one new sequence. Here, this operation is denoted by "QC-DBTC Symbols" and reference numeral 620 in FIG. 6. Through a series of the processes described above, symbol rearrangement for generating QC-DBTC codes is completed. The QC-DBTC symbol rearrangement can be expressed as in Equation (8) below. In Equation (8), {a\|b} denotes a new sequence obtained by serial-concatenating two sequences 'a' and 'b' and ITRa,b) denotes mutual-interiacing of'two sequences 'a" and 'b'. ThaL is. the sequences 'a' and "b" are interlaced in the order of a_ 0. b 0. a i. b .1, a 2. b.2. -, a M. h_M. Step "¦ QC-DBTC Symbol Selection Ne\i, a QC-DBTC symbol selector 622 generates QC-DBTC codes Inning various code rates by selecting random symbols from 3xN HI' symbols. A scheme for generating the QC-DBTC codes having various code rates is well disclosed in Korean Patent Application No. P2001-0007357, entitled "Code Generating Apparatus and Method in a Code System," filed by the applicant, the entire content of which is incorporated herein by reference. As described above, QC-DBTC is different from the conventional binary QCTC in Step 2 and Step 5. The reason for using the quad-symbol mapping is as follows. First, the use of the quad-symbol mapping makes a si/e of the systematic symbol groups be equal to a size of the parity symbol groups. Therefore, a transmitter includes only one sub-block interleaving device. That is, the use of the same sub-block size contributes to a simplification of the parameters and algorithm for sub-block interleaving. Generally, PBRO interleaving is used as the sub-block interleaving. Second, as the use of the quad-symbol mapping makes a si/e of the systematic symbol groups be equal to a si/c of the parity symbol groups, a receiver also includes only one sub-block interleaving device. The receiver preferably implements sub-block interleaving using an inverse function of the interleaving used in the transmitter, and generally, the use of an inverse function for interleaving causes an increase in implementation complexity of deinterleaving. In addition, the use of different sub-block sizes causes an increase in implementation complexity in proportion thereto. Therefore, the use of the same sub-block size enables the use of a single inverse function., contributing to a reduction in complexity of the receiver. Third, the use of the quad-symbol mapping can improve a channel interleaving depth as compared with a scheme lor separately sub-block-interleaving s\stcma:;e symbol streams A and B. It is well disclosed in related references t!;ai an increase in channel interleaving depth generally improves interleaving perform::.-:e. In particular, the channel interleaving depth is an important performance parameter in a mobile communication system, and as noted above in regard to the conventional binary QCTC. QCTC has a structure of integrating FEC coding and channel interleaving into one scheme. Therefore, even though QCTC has the same coding gain, it is preferable because of its structure to improve performance of channel interleaving. In this context. the quad-symbol mapping structure can extend a channel interleaving area of systematic symbols up to N_EP. However, the scheme for separately sub-block-interleaving systematic symbol streams A and B is limited to N_EP,2 in terms of channel interleaving area. FIG. 7 is a block diagram illustrating a structure of a receiver in a QC-DBTC system according to an embodiment of the present invention. With reference to FIG. I7, a detailed description will now be made of a structure and operation of a receiver in a QC- DBTC system according to an embodiment of the present invention. The receiver performs an inverse process of QC-DBTC used in the transmitter, and restores N_EP systematic symbols from received codeword symbols. With reference to FIG. 7. a description will now be made of a process of restoring systematic symbols. A QC-DBTC symbol selector 710 converts received symbols q.,-,, qi, ¦¦¦, qy.;.i to quad- symbols comprised of parity symbols and systematic symbols. The quad-symbols are denoted by reference numeral 712. Because the quad-symbols are separately comprised of systematic symbols and parity symbols, the systematic symbols are output intact and the parity symbols are divided into interlaced symbols 7L4a and 714b. The interlaced symbols 714a and 714b arc separated into corresponding parity symbols through a deinterlacing process. The systematic symbols are mapped to quad-symbols by a quad- symbol mapper 730. The parity symbol streams separated through the deinterlacing process and the systematic symbol stream are input to their associated PBRO processors 7!6a, 716b, 716c. 716d, and 716c, and the PBRO processors 716a, 716b. 716c, 7l6d, and 716e PBRO-rcarrange the input symbols. The output symbols 718 of the PBRO processors ~16a. 71 Ob. T16c, 7 Kid, and 7 I 6c arc equal to the output symbols of the code symbol separator 6! 4 of FIG 6. li should be noted herein that, because N__LP systcrriatic symbols q k iwherein k=0, I, 2, 3.--. N_EP-1) have real values, the receiver, unlike the transmitter, cannot quad-symbol-map the systematic symbols to (0,0), (0,1). (1,0), (1.1) as shown in Tabic 1. Therefore, symbol positions (q_k, q k- 1) (where k=0, 2. 4,--. N FP-2) corresponding to A_i' and B_F are concatenated into one symbol pair (q_k, q_ k ¦¦ i). wherein the symbol pair is regarded a quad-symbol and size-N_EP.-2 PBRO interleaving is achieved. Thai is, what is preferably done is to simply match the symbol positions of q_k and q k • 1. An example of such a mapping rule is illustrated in Table 2. In the same manner, parity symbols are divided into 4 partly blocks by deinlerlacing, and the parity blocks arc divided into V0, Yl, Y'O and Y'l, respectively, and then converted to CI I, CI2, C21 and C22, by PBRO sub-block deinterleaving. Also, the systematic symbols M' are restored to their original order by PBRO sub-block deinterleaving. Next, a quad-symbol demapper 740 converts m_i (wherein i¦¦--(), 1, 2. ,-¦-, N! FP- !) to (A i, B i) through an inverse process of the transmitter. Next, all of 3N_FP code symbols obtained by concatenating A, B, CTI, CI2, C21 and C22 are input to a duo- binary turbo encoder 722. For reference, when a code rate is higher than 1.3, the number of svmbols actually transmitted is less than 3N EP, and in this case, an erasure symbol is added to q i corresponding to a symbol position where no symbol is transmitted and a QC-DBTC reception operation is performed in the foregoing process. FIG 8 is a block diagram illustrating a structure of a transmitter in a QC-DBTC system according to another embodiment of the present invention. In FIG. 8, only the scheme for extending a si^e oi"the systematic symbols to NEP is described in detail. As illustrated in Fit.,, i, the scheme is substantially the same as the conventional QCTC scheme in structure, hut different in that the scheme of l-'IG. 8 uses a binary turbo encoder. Also, compared with the structure of FIG. 6. the structure of FIG 8 does not include a quad-symbol mapper and a quad-symbol demapper. The structure of l-'IG. 8 is substantially identical to the structure of FIG 6 except for the absence of a quad-symbol mapper and a quad-symbol demapper, and only those differences in structure and function between them will be described. As can be understood from FIG 8, systematic symbols among the code symbols output from a turbo encoder 810 are doubled in terms of size of a PBRO sub-block interleavcr 816a associated with the systematic symbols, while all of the PBRO sub-block interlcavers 616a to 616c for the conventional QCTC codeword have same size. Systematic symbol streams A and B are alternately arranged in the order of A_0, B_0, A_l, B_l, A_2, B .2, -, A then input to the PBRO sub-block interleave!' 816a. Such a structure is advantageous in that channel interleaving is performed on a pcr-binary symbol basis, thai is. on a per-bit basis, thereby improving randomness of channel interleaving. However, this scheme is disadvantageous in that, because the sub-block for systematic symbols is different in si/.e from the sub-blocks for parity symbols, a transmitter and a receiver both require two PBRO sub-block interleaving devices. However, because a channel interleaving depth is extended to N EP in the QC-DBTC scheme illustrated in FIG. 6, a difference between the extended channel interleaving depth and a bit-basis channel interleavcr depth of FIG. 8 is negligible. In another alternative embodiment, only a binary turbo encoder is used while a structure of a QCTC code generation apparatus remains unchanged. In this embodiment, because the number of systematic symbols output from the binary turbo encoder is doubled unlike that in the QCTC scheme, the number of sub-block interlcavers is extended to 2 (MO and Ml). Therefore, all of the sub-block interlcavers have the same size of N EP.2, like those in FIG. 6. Such a scheme is illustrated in l-'IG. 9. Here, only the differences between the structure and function of FIG. 9 and FIG. 6 will be described. The scheme of I'M. 9 has two PBRO sub-block interleave-! for systematic symbols. In FIG. 9. sub-block imerleavers 916al and 916a2 for systematic symbols lia\e the same size as thai, ol' sub-block inter!cavers 9i6b. 9'.6c, 916*1 ant! 916d for purity symbols. Therefore, the systematic symbol streams A and B are sequentially arranged in their associated sub-blocks MO and Ml. subjected to independent PBRO sub-block interleaving, and then sequentially arranged in a QC-DBTC symbol stream. Such a structure is advantageous in that channel interlea\ing is performed on a pcr-binary symbol basis, that is, on a per-bit basis, and all of the sub-blocks can use the same-sized PBRO interleaving devices. However, this scheme is disadvantageous in lhal, because the sub-blocks for the systematic symbols have a small size of N HP. 2 and are arranged in parallel in a QC-DBTC symbol stream, a channel interleaving depth is limited to N EP2 as compared with the conventional scheme of FIG. 6. As described above, the present invention can generate codes having various code rates in a high-rate wireless data system in which a duo-binary turbo code for selecting one of multiple modulation schemes and one of multiple FHC coding schemes before transmission is used as a mother code. In MARQ, the present invention can provide various sub-codewords and redundancies with a simple QC-DBTC encoder, thereby maximizing transmission efficiency of the system. While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art lhal various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. We Claim: 1. An apparatus for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC), comprising: a duo-binary turbo encoder (810) having a plurality of constituent encoders for receiving an information symbol stream (800), and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate, wherein the plurality of parity symbol streams are generated from the plurality of constituent encoders associated thereto and the parity symbol streams from one of the plurality of constituent encoders correspond to the parity symbol streams from another one of the plurality of constituent encoders; a quad-symbol mapper(630) for quad-mapping the plurality of systematic symbol streams to one symbol stream; a channel interleaver (816 a) for interleaving the quad-mapped systematic symbol stream and the plurality of parity symbol streams from the plurality of constituent encoders, quaddemapping the quad-mapped systematic symbol stream, interlacing symbol streams in the plurality of parity symbol streams corresponding to each other from among the interleaved parity symbol streams, and serial-concatenating the quaddemapped systematic symbol stream and the interlaced parity symbol streams; and a duo-binary turbo code generator (822) for repeating the serial- concatenated symbol stream, and selecting a predetermined number of symbol streams from the repeated symbol streams according to the given code rate and selection information thereby generating QC-DBTC codes. 2. The apparatus as claimed in claim 1, wherein the quad-mapped systematic symbol stream output from the quad-symbol mapper is 1/2 the size of the plurality of systematic symbol streams. 3. The apparatus as claimed in claim 1, wherein the quad-mapped systematic symbol stream output from the quad-symbol mapper is equal in size to the QC-DBTC codes. 4. The apparatus as claimed in claim 1, wherein the quad-mapped systematic symbol stream output from the quad-symbol mapper is equal in size to the plurality of parity symbol streams. 5. The apparatus as claimed in claim 1, wherein the channel interleaver comprises: a plurality of interleavers (816b to 816e) for interleaving the quad- mapped systematic symbol stream and the plurality of parity symbol streams output from the plurality of constituent encoders; a quad-symbol demapper (640) for quad-demapping the quadmapped systematic symbol stream; an interlacer (818) for interlacing the interleaved parity symbol streams; and a symbol concatenator (820) for serial-concatenating the quaddemapped symbol streams and the interlaced parity symbol streams. 6. The apparatus as claimed in claim 1, wherein a code rate of the duo- binary turbo encoder is 1/3. 7. A method for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC), comprising the steps of: receiving an information symbol stream and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate; Quad-mapping the plurality of systematic symbol streams to one symbol stream; interleaving the quad-mapped symbol stream and the plurality of parity symbol streams; quad-demapping the interleaved systematic symbol stream; interlacing the plurality of parity symbol streams in pairs; serial-concatenating the interlaced parity symbol streams and the quad-demapped systematic symbol stream; and repeating the serial-concatenated symbol stream, and selecting a predetermined number of symbol streams from the repeated symbol streams according to the given data rate. 8. The method as claimed in claim 7, wherein the interleaving step comprises the steps of: interleaving the quad-mapped systematic symbol stream and the plurality of parity symbol streams; quad-demapping the quad-mapped systematic symbol stream; interlacing the interleaved parity symbol streams; and serial-concatenating the quad-demapped systematic symbol stream and the interlaced parity symbol streams. 9. An apparatus for generating code symbols by encoding an information symbol stream according to a given code rate using a Quasi- Complementary Duo-Binary Turbo Code(QC-DBTC) encoder and selecting all or some of code symbols to be transmitted from among the generated code symbols, the apparatus comprising; a QC-DBTC encoder (810) for receiving an information symbol stream (800) and generating QC-DBTC symbol streams according to a predetermined code rate; a separator (812) for separating the generated QC-DBTC symbol streams into a plurality of systematic symbol streams and a plurality of parity symbol streams, the systematic symbol streams being connected into one symbol stream; a plurality of interleaves (816b to 816e) for interleaving the plurality of parity symbol streams, respectively; a systematic symbol stream interleaver (816a) for interleaving the one systematic-symbol stream; a plurality of interlacers (818a,818b) for interlacing the plurality of parity symbol streams in pairs; a concatentor (820) for serial-concatenating the interleaved systematic symbol stream and the interlaced parity symbol streams, and a symbol selector (822) for repeating the serial-concatenated symbol stream, and selecting a predetermined number of symbol streams from the repeated symbol streams according to the given data rate and selection information thereby generating QC-DBTC codes. lO.The apparatus as claimed in claim 9, wherein the separator interlaces the plurality of systematic symbol streams into one systematic symbol stream, ll.The apparatus as claimed in claim 9, wherein the systematic symbol stream interleaver is two times larger in size than one of the plurality of interleavers for interleaving the parity symbol streams. 12. A method for generating coded symbols by encoding an information symbol stream according to a given code rate using a Quasi- Complementary Duo-Binary Turbo Code (QC-DBT-C) encoder and selecting all or some of code symbols to be transmitted from among the generated code symbols, the method comprising the steps of: receiving an information symbol stream and generating QC-DBTC symbols, streams according to a predetermined code rate; separating the generated QC-DBTC symbol streams into a plurality of systematic symbol streams and a plurality of parity symbol streams, interlacing the plurality of systematic symbol streams into one systematic symbol stream; interleaving the plurality of parity symbol streams, respectively; interleaving the one systematic symbol stream; interlacing the plurality of parity symbol streams in pairs; serial-concatenating the interleaved systematic symbol stream and the interlaced parity symbol streams; and repeating the serial-concatenated symbol stream, and selecting a predetermined number of symbol streams from the repeated symbol streams according to the given code rate and selection information thereby generating QC-DBTC codes. 13. An apparatus for decoding all or some of the received code symbols generated by encoding an information symbol stream according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code (QC- DBTC) encoder, the apparatus comprising: a selector (710) for inserting a predetermined code symbol streams in a position corresponding to a punctured symbol stream among received symbols; a deinterlacer (714a, 714b) for deinterlacing a plurality of parity symbols streams among the symbol streams generated by the selector; a quad-symbol mapper (730) for quad-mapping a plurality of systematic symbols among the symbol streams generated by the selector; a plurality of deinterleavers (716a to 716e) for deinterleaving the quad- mapped systematic symbol streams and the deinterlaced parity symbol streams, respectively; a quad-symbol demapper (740) for quad-demapping the deinter-leaved systematic symbol streams; a code symbol concatenator (720) for concatenating the quad-symbol demapped systematic symbol streams and the deinterleaved parity symbol streams; and a QODBTC decoder (722) for QC-DBTC decoding the concatenated symbol streams. The invention relates to an apparatus for generating Quasi-Complementary Duo- Binary Turbo Codes (QC-DBTC), comprising a duo-binary turbo encoder (810) having a plurality of constituent encoders for receiving an information symbol stream (800), and generating a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate, wherein the plurality of parity symbol streams are generated from the plurality of constituent encoders associated thereto and the parity symbol streams from one of the plurality of constituent encoders correspond to the parity symbol streams from another one of the plurality of constituent encoders; a quad-symbol mapper(630) for quad-mapping the plurality of systematic symbol streams to one symbol stream; a channel interleaver (816 a) for interleaving the quad-mapped systematic symbol stream and the plurality of parity symbol streams from the plurality of constituent encoders, quaddemapping the quad-mapped systematic symbol stream, interlacing symbol streams in the plurality of parity symbol streams corresponding to each other from among the interleaved parity symbol streams, and serial-concatenating the quaddemapped systematic symbol stream and the interlaced parity symbol streams; and a duo-binary turbo code generator (822) for repeating the serial-concatenated symbol stream, and selecting a predetermined number of symbol streams from the repeated symbol streams according to the given code rate and selection information thereby generating QC-DBTC codes.

Full Text

BACKGROUND OF THE INVENTION
Field of the Invention:
The present invention relates generally to an apparatus and method for
generating Forward Error Correction (FEC) codes in a wireless data communication
system. More particularly, the present invention relates to an apparatus and method for
generating FEC codes having a variable rate.
Description of the Related Art:
In general, wireless data communication systems are classified as a Mobile
Communication System (MCS), Wireless Local Area Network (WLAN), Wide Area
Network (WAN) or Metropolitan Area Network (MAN), all of which are based on
mobile communication technology. For the Mobile Communication System, systems for
high-speed data transmission are also being developed independently by 3rd Generation
Partnership Project-2 (3GPP2), a standardization group for a synchronous Code Division
Multiple Access (CDMA) mobile communication system, and 3rd Generation Partnership
Project (3GPP), a standardization group for an asynchronous Universal Mobile
Telecommunications System (UMTS) mobile communication system. Also, for WLAN,
WAN and MAN, various attempts are also being made to transmit radio data at a high
rate in the area of IEEE 802.11 to IEEE 802.16 standardization.
A description will now be made of Adaptive Modulation & Coding (AMC) as
attempted in the foregoing communication standards. Also, a description will be made of
an IEEE 802.16a system, a CDMA2000 1x EV-DV (Evolution with Data and Voice)
system based on the CDMA mobile communication system, and a High speed Portable
Internet (HPi) system currently being developed in South Korea for high-speed data
transmission in a 2.4 GHz band, all of which comprise the most substantially advanced
systems in the related technical field.
First, an IEEE 802.16a system will be described. The IEEE 802.16a system is a
system using Orthogonal Frequency Division Multiple Access (OFDMA).
FIG. 1 is a block diagram illustrating the structures of physical channels for
transmitting high-rate data in an IEEE 802.16a system using Orthogonal Frequency
Division Multiplexing (OFDM). Referring to FIG. 1, all of the physical channels
transmitted to users Userl, User2, •••, Userm have the same structure. Therefore, in FIG.
1, the same elements are assigned the same reference numerals, and different letters such
as a, b, •••, m are added to the ends of the reference numerals as indicators for indicating
the respective users and their associated physical channels. Parameters used in the
physical channels for the users Userl, User2, •••, Userm can have either the same values
or different values. For example, the respective physical channels can be different from
one another in input packet size, code rate, modulation order and transmission duration.
A description will now be made of a physical channel for a first user Userl, by way of
example.
In a physical channel, data Userl_Data to be transmitted to a first user Userl is
input to a Cyclic Redundancy Check (CRC) adder 101a, and the CRC adder 101a adds a
CRC to the input user data Userl_Data so that a reception side can detect an error
occurring due to noises in a channel transmission process. The CRC-added user data is
input to a tail bit adder 103a, and the tail bit adder 103a adds tail bits to the CRC-added
user data. The CRC is an error correction code used for correcting an error occurring due
to noises in a channel transmission process, and is generally used for Forward Error
Correction (FEC). Generally, convolutional codes or turbo codes are used for the FEC
used in a wireless communication system. These codes use tail bits which are
termination bits for terminating the corresponding codes at a '0' state on a trellis diagram.
Therefore, the tail bit-added data is FEC-encoded by an FEC encoder 105a. As this is
well disclosed in the related references, a detailed description thereof will be omitted
herein.
Next, in order to match the number of output signals of the FEC encoder 105a
to the number of modulation symbols allocated to each user, a symbol repetition &
puncturing part 107a performs symbol repeating and puncturing on the FEC-encoded
data. The symbols that underwent repetition and puncturing are input to a channel
interleaver 109a for converting a burst error occurring in the channel into a random error,
and the channel interleaver 109a channel-interleaves the input symbols. The channel-
interleaved symbols are input to a modulator 111a, and the modulator 111a modulates
the channel-interleaved symbols. The modulated symbols are input to a subcarner or
subchannel mapper and an NOS or NOOS mapper 120. The subcarrier or subchannel
mapper and the NOS or NOOS mapper 120 performs subcarrier or subchannel mapping,
and NOS (Number of Slots) or NOOS (Number of OFDM Symbols) mapping on the
modulated symbols for a transmission duration allocated to each user. The subcarrier or
subchannel mapper and the NOS or NOOS mapper 120 simultaneously processes data
for all users. The symbols output from the subcarrier or subchannel mapper and the NOS
or NOOS mapper 120 are input to an inverse fast Fourier transform (IFFT) 130, and the
IFFT 130 performs inverse fast Fourier transform on the input symbols. In this way, data
for each user is converted into one carrier signal and delivered to a radio frequency (RF)
unit (not shown).
In the foregoing description, "NOS" or "NOOS" designates a transmission
duration allocated to each user, and is variable according to a size of user data. Therefore,
an increase in NOS or NOOS causes an increase in transmission time allocated to one
packet. In addition, "subchannel" designates a set of subcarriers used in Orthogonal
Frequency Division Multiplexing (OFDM). It is not necessary that the subcarriers
constituting one subchannel should always be arranged in a regular sequence in a
frequency domain, and it is typical that multiple subcarriers constitute one subchannel
according to a particular pattern. For example, when a given frequency bandwidth is
divided into 2048 orthogonal frequencies, if there are 1st to 2048th subcarriers, one
subchannel can be configured with 4 subcarriers of 1st, 8th, 16th, 32nd and 64th subcarriers.
The configuration of a subchannel and the number of subcarriers constituting the
subchannel are subject to change according to standards.
FIG. 2 is a block diagram illustrating structures of physical channels for
transmitting data to a user in a current HPi high-rate data system. FIG. 2 is substantially
identical in structure to that of FIG. 1 except that the structure of FIG. 2 does not add
CRC and tail bits. This is because the CRC function can be performed in a Medium
Access Control (MAC) layer. Therefore, elements 205r 207. 209, 211. 220 and 230 in
FIG. 2 correspond to the elements 105, 10". 109. Ill, 12'-' and 130 ^ FIG. 1,
respectively. When the structures of both l-'IGs. 1 and 2 have multiple modulators and
multiple FF.C code rates, they require a scheme for determining a code rate and a
modulation order for guaranteeing each user the best performance.
As illustrated in FIGs. 1 and 2, in a physical channel for a packet transmission
service, a modulator is necessary. In addition, FEC codes are used in order to overcome
data errors caused by noises occurring in a radio communication channel. However, in
the current physical channel for a packet transmission service, FEC codes with a fixed
rale are generally used and in particular, the best codes for a given rate are used. This is
because the physical channel for a packet transmission service has a characteristic of a
stationary channel, such as an Additive White Gaussian Noise (AWGN) channel.
Therefore, there is less necessity to take the FEC codes using an adaptive rate into
consideration. For example, IEEE 802.16a, a high-rate wireless data sen ice standard,
does not guarantee mobility of a mobile station and uses only 6 FEC code rates. A
detailed description of the standard is well disclosed in the IEEE 802.16a physical
channel standard, the entire contents of which are incorporated herein by reference.
While the mobile communication system uses binary turbo codes, the IEEE 802.16a uses
duo-binary turbo codes.
The duo-binary turbo codes will now be described in greater detail. FIG. 3 is a
block diagram illustrating an apparatus for generating rate R=l:2 duo-binary turbo codes,
and F-TG. 4 is a block diagram illustrating an apparatus for generating R=1/3 duo-binary
turbo codes.
As illustrated in FIG. 3, an R-l/2 duo-binary turbo encoder receives 2
information symbols A and B in parallel. The 2 information symbols A and B received in
parallel are input in common to a first constituent encoder 301 and a turbo interleaver
302. The turbo interleaver 302 interleaves the 2 parallel input information symbols A and
B. and outputs the interleaved information symbols to a second constituent encoder 30?.
The 2 parallel input information symbols A and B are output intact as systemic
symbols, and the first constituent encoder 301 and the second constituent encoder 3'>3
generate parity symbols CI and C2. respectively, using the 2 input information symbols
A and B. As a result, the 2 input information symbols are output intact as systematic
svmbols. and each constituent encoder generates one parity symbol. Therefore, a code
rate of the encoder is 1 2.
An R=I 3 duo-binary turbo encoder of FIG. 4 receives 2 information symbols A
and B in parallel. The 2 parallel input information symbols A and B are input in common
to a first constituent encoder 401 and a turbo interleave!' 402. The turbo interleaver 402
interleaves the 2 parallel input information symbols A and B, and outputs the interlca\ed
information symbols to a second constituent encoder 403. The 2 parallel input
information symbols A and B are output intact as systematic symbols, and the first
constituent encoder 401 and the second constituent encoder 403 generate parity symbol
pairs C1UCI2 and C21;C22, respectively, using the 2 input information symbols A and
B. As a result, the 2 input information symbols are output intact as systematic symbols,
and each constituent encoder generates two parity symbols. Therefore, a code rate of (lie
encoder is 1.3.
A description will now be made of an encoding method performed in the duo-
binary turbo encoders of FIGs. 3 and 4. It will be assumed that a si^e of an information
symbol to be encoded is Nf F.P. and K FP/2 information symbol pairs that are generated
by halving the size N_EP information symbol are denoted by A i and B i (wherein i-0,
I,---, N_EP:2), respectively. In this case, the duo-binary turbo encoder encodes a symbol
pair A_i and B_i by a first constituent encoder 301 (or 401) and outputs a parity symbol
Cl (or a parity symbol pair CI 1;C12) as the encoding result. Next, the turbo inlerleaver
302 (or 402) interleaves the N_EP.'2 information symbol pairs A i and B i. and outputs
the interleaved information symbol pairs to a second constituent encoder 303 (or 403).
The second constituent encoder 303 (or 403) encodes the input information symbol pairs,
and outputs a parity symbol C2 (or a parity symbol pair C21 ;C22) as the encoding result.
As a result, for N l:P input information symbols, the R-I/2 duo-binary turbo encoder
outputs 2\N_EP codeword symbols and the R-1-3 duo-binary turbo encoder outputs
3N_EP codeword symbols.
It is generally known to those skilled in the art that the duo-binary turbo codes
are slightly superior to the binary turbo codes in performance gain at a high code rate
When compared with the binary turbo codes whose information symbol size is N_EP,
the duo-binary turbo codes whose information symbol side is also N EP. are reduced to
1.2 in trellis length, that is. frame length, contributing lo a 1 2 reduction in decoding
delay. Disadvantageously , however, the duo-binary turbo codes are inferior lo the binary
turbo codes in performance at a lower code rale. In addition, the duo-binary turbo codes
are higher than the binary turbo codes in terms of decoding complexity, because 4
branches arc used for each state in a trellis diagram.
However. CDMA2000 Ix EV-DY (Evolution with Data and Voice,), a
synchronous mobile communication standard, guarantees mobility of a mobile station.
For a system lo guarantee mobility, not only should data error caused by noises
occurring in a wireless communication channel be taken into consideration, but also
various schemes for overcoming a data error caused by fading should be taken into
consideration. For example, in order for a transmitter to actively cope with a dynamic
change in signal-to-noise ratio tSNR) occurring in a fading channel environment, a
packet modulation scheme of transmitting the same transmission packet at all times and
an AMC scheme of varying a code rate of FEC codes are extensively considered. For
example, in CD.MA2000 lx FA'-DV, Quasi-Complementary Turbo Codes (QCTC) are
used for a physical channel as a scheme for freely supporting a variable code rate. The
QCTC designates a set of turbo codes with various code rates selected by a symbol
selector after code symbols, encoded from a given mother code according lo a specific
rule, are rearranged as shown in FIG. 5.
With reference to FIG. 5, a description will now be made of an operation of
QCTC selected as a standard for a CDMA2000 lx FA'-DV system. When an information
stream 500 is input to a turbo encoder 510 having a rate R=l.-5, the turbo encoder 510
performs turbo coding on N_EP input information symbols using a mother code. As a
result, the turbo encoder 510 generates 5xN_EP code symbols. The generated code
symbols are demultiplexed into 5 sub-blocks by a code symbol separator 512. The
separated code symbols are denoted by reference numeral 514. The code symbols 514
are divided into a systematic symbol group (or sub-block X) and a plurality of parity
symbol groups (or sub-blocks Y0, Yl, Y'O and Y'l). The respective symbol groups
undergo Partial Bit Reversal Order (PBRO) interleaving. Here, the respective sub-blocks
undergo independent interleaving. This is called "sub-block interleaving." Reference
numerals 516a, 516b, 516c, 516d and 516e denote independent devices for performing
the PBRO interleaving.
Among the PBRO-interleaved symbols, systematic symbols are output intact,
and the PBRO-interleaved parity symbols are interlacedly rearranged by interlacers 518a
and 518b. The rearrangement is achieved in such a manner that two symbols are
interlaced once. That is, the interlacer 518a forms a new group by interlacing parity
symbols Y0 and Y'O. Similarly, the interlacer 518b interlacedly rearranges parity
symbols Yl and Y'l generated in each sub-block, thereby forming a new group.
Therefore, each group generated by interlacing has a size of 2xN_EP.
Next, the sub-block comprised of interleaved systematic symbols and the 2
interlaced parity groups are arranged in a regular order and then concatenated, thus
generating one new sequence. Here, this operation is denoted by "QCTC Symbols" and
reference numeral 520. Through a series of the processes described above, symbol
rearrangement for generating QCTC codes is completed. Next, a QCTC symbol selector
522 generates QCTC codes having various code rates by selecting random symbols from
5xN_EP symbols. A conventional binary QCTC design criteria is to take performance
improvements of a received signal in a fading channel into consideration. The QCTC
design criteria are characterized by optimizing not only code performance, but also
channel interleaving performance. The channel interleaving is generally achieved by
sub-block interleaving and interlacing.
According to the current HPi standard, there are some 120 possible different
combinations of modulation schemes and FEC code rates. However, there is no
proposed scheme lor genc.ating and determining FEC codes supporting the possible
combinations, that is. turbo codes having various code rates. Particularly an
OFDM OFDMA svstem has no proposed method for varying an FEC code rate
according to a relation between, a modulation scheme and an FEC code rate
corresponding to each data rate. In addition, when Hybrid Automatic Repeat Request
(HARQj is used, there is no proposed scheme for generating various redundancies.
For the binary turbo codes used in a mobile communication system, that is,
binary turbo codes defined in the CDMA2000 Ix F.V-DY standard, QCTC has been
proposed as a scheme for providing various codes in the foregoing environments.
However, QCTC is basically optimized for binary turbo codes. Therefore, separate
optimization is required when non-binary turbo codes such as duo-binary turbo codes are
used as mother codes. In particular, the use of the duo-binary turbo codes requires
symbol classification and interleaving in which a characteristic of systematic symbols
are taken into consideration.
Accordingly, a need exists for an apparatus and method for generating desired
codes and for decoding the desired codes in a high-rate wireless data system.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus and
method for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC).
and an apparatus and method for decoding the QC-DBTC codes in a high-rate wireless
data system in which various packet sizes are used for data transmission.
It is another object of the present invention to provide an apparatus and method
for generating duo-binary turbo codes having various code rates, and an apparatus and
method for decoding the duo-binary turbo codes in an OFDMA high-rate wireless packet
data communication system in which HARQ is used.
It is another object of the present invention to provide an apparatus and method
for generating duo-binary turbo codes, and an apparatus and method for decoding the
duo-binary turbo codes in an OFDMA high-rale wireless packet th.ua communication
svstem in which various packet sizes arc used, and wherein one of multiple modulation
schemes and one of multiple FEC coding schemes are selected according to a channel
stale, a buffer state, the number of available subchannels (or subcarriersi, the number of
OFDM symbols, and a transmission duration.
In accordance with a first aspect of the present invention, there is provided an
apparatus for generating subpackets. The apparatus comprises a encoder for encoding
information symbols, wherein the information symbols are fed alternatively to two input
ports of the encoder; a symbol separator for demultiplexing all of the encoded symbols
into two systematic symbol sunblocks and two pairs of parity symbol subblocks; a
channel interleaver for separately interleaving the subblocks; a symbol group generator
for generating the first symbol-by-symbol multiplexed sequence of one pair of the
interleaved parity symbol subblocks, the second symbol-by-symbol multiplexed
sequence of another pair of the interleaved parity symbol subblocks and two systematic
sequences of two interleaved systematic symbol subblocks: and a symbol selector for
selecting a predetermined number of symbols from the two systematic sequences, the
first symbol-by-symbol multiplexed sequence and the second symbol-hy-syinbol
multiplexed sequence .
In accordance with a second aspect of the present invention, there is provided a
method for generating subpackets. The method comprises the steps of: encoding
information symbols, wherein the information symbols are fed alternatively to two input
ports of an encoder; demultiplexing all of the encoded symbols into two systematic
symbol subblocks and two pairs of parity symbol subblocks; separately interleaving the
subblocks; generating the first symbol-by-symbol multiplexed sequence of one pair of
the interleaved parity symbol subblocks, the second symbol-by-symbol multiplexed
sequence of another pair of the interleaved parity symbol subblocks and two systematic
sequences of two interleaved systematic symbol subblocks; and selecting a
predetermined number of symbols from (he two systematic sequences, the first symbol-
by-symbol multiplexed sequence and the second symbol-by-symbol multiplexed
sequence.
In accordance with a third aspect of the present invention, there is provided an
apparatus for generating Quasi-Complementary Duo-Binary Turbo ('odes (QC-DBTO.
The apparatus comprises a duo-binary turbo encoder having a plurality of constituent
encoders for receiving an information symbol stream, and lor generating a plurality or
systematic symbol streams and a plurality ol"parity symbol streams according to a given
code rate, wherein the parity symbol streams are generated from the constituent encoders
associated thereto and the parity symbol si reams from one of the constituent encoders
correspond to the parity symbol streams from another one of the constituent encoders; a
quad-symbol mapper for quad-mapping the systematic symbol streams to one symbol
stream; a channel interleaver for independently interleaving the quad-mapped systematic
symbol stream and the parity symbol streams from the constituent encoders, quad-
demapping the quad-mapped systematic symbol stream, interlacing symbols in the parity
symbol streams corresponding to each other from among Ihe interleaved parity symbol
streams, and serial-concatenating the quad-demapped systematic symbol stream lo the
interlaced parity symbol streams; and a duo-binary turbo code generator for repeating
Ihe serial-concatenated symbol stream, and for selecting a predetermined number of
symbols from the repeated symbol stream according to a code rale and selection
information thereby generating QC-DBTC codes.
In accordance with a fourth aspect of the present invention, there is provided a
method for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC).
The method comprises the steps of: receiving an information symbol stream and
generating a plurality of systematic symbol streams and a plurality of parity symbol
streams according to a given code rate; separating the generated symbol streams into
systematic symbol streams and parity symbol streams; quad-mapping the separated
systematic symbol streams to one symbol stream; independently interleaving the quad-
mapped symbol stream and the parity symbol streams; quad-demapping the interleaved
systematic symbol stream, interlacing the parity symbol streams in pairs; concatenating
the interlaced parity symbol streams lo the quad-demapped systematic symbol stream;
and selecting symbols to be transmitted according to a given data rate from ihe
concatenated symbols.
I:i accordance with a f'lKh aspect oi"th.- present invention, there is provided an
apparatus tor generating code symbols by encoding an informal ion symbol stream
according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code
(QC-DBTC) encoder and, selecting all or some of die code symbols lo be transmitted
from among the generated code symbols. The apparatus comprises a QC-DBTC encoder
lor receiving an information symbol stream and generating QC-DlifC symbols
according to a predetermined code rate: a separator for separating output symbols of (he
QC-DBTC encoder into a plurality of systematic symbol streams and a plurality of
parity s\nibol streams, the systematic symbol sLreams being connected into one symbol
stream; a plurality of inlerleavers for independently interleaving the parity symbol
streams; a systematic symbol stream interleave!' for interleaving the connected
systematic symbol stream; an interlaeer for interlacing the parity symbol streams in
pairs; a concatcnator for serial-concatenating an output of the systematic symbol stream
intcrleaver to an output of the interlaeer; and a symbol selector for selecting symbols to
be transmitted according to a given data rate from the concatenated symbols.
In accordance with a sixth aspect of the present invention, there is provided a
method for generating code symbols by encoding an information symbol stream
according lo a given code rate using a Quasi-Complementary Duo-Binary Turbo Code
(QC-DBTC) encoder and selecting all or some of the code symbols to be transmitted
from among the generated code symbols. The method comprises the steps of receiving
an information symbol stream and generating QC-DBTC symbols according to a
predetermined code rate; separating output symbols of the QC-DBTC encoder into a
plurality of systematic symbol streams and a plurality of parity symbol streams, the
systematic symbol streams being connected into one symbol stream; independently
interleaving the parity symbol streams; interleaving the connected systematic symbol
stream; interlacing the parity symbol streams in pairs; serial-concatenating the
interleaved systematic symbol stream to the interlaced parity symbol streams; and
selecting symbols to be transmitted according to a given data rate from the concatenated
symbols.
In accordance with a seventh aspect of the present invention, there is provided
ail apparaius lor generating code symbols by encoding an in formation symbol stream
according to a given code rate using a Quasi-Complementary Duo-Binary Turbo Code
(QC-DBTC) encoder and selecting all or some of the code symbols to be transmitted
from among the generated code symbols. The apparatus comprises a QC-DBTC encoder
having a plurality ct" constituent encoders for receiving an information symbol si ream,
and for generating a plurality of systematic symbol streams and a plurality of parity
symbol streams according to a given code rate, wherein the parity symbol streams arc
generated from the constituent encoders associated thereto and the parity symbol streams
from one of the constituent encoders correspond to the parity symbol streams from
another one of the constituent encoders; a separator for separating a;i output of the QC-
DBTC encoder into systematic symbol streams and parity symbol streams; a plurality of
interleavers for independently interleaving the systematic symbol streams and the parity
symbol streams; an imerlacer for interlacing in pairs, the parity symbol pairs generated
from different constituent encoders; a concatenator for serial-concatenating the
interleaved systematic symbol streams to the interlaced parity symbol streams; and a
symbol selector for selecting symbols to be transmitted according to a given data rate
from the concatenated symbols.
In accordance with an eighth aspect of the present invention, there is provided a
method for generating code symbols by encoding an information symbol stream
according to a given code rale using a Quasi-Complementary Duo-Binar\ Turbo Code
(QC-DBTC) encoder and selecting all or some of the code symbols to be transmitted
from among the generated code symbols. The method comprises the steps of receiving,
by the QC-DBTC encoder, the an information symbol stream, and generating a plurality
of systematic symbol streams and a plurality of parity symbol streams according to a
given code rate, wherein the parity symbol streams arc generated from the constituent
encoders associated thereto and the parity symbol streams from one of the constituent
encoders correspond to the parity symbol streams from another one of the constituent
encoders; separating an output of the QC-DBTC encoder into systematic symbol streams
and parity symbol streams; independently interleaving the systematic symbol streams
and the parity symbol streams; interlacing the parity symbol pairs in pairs; concatenating
the interleaved systematic symbol streams to the interlaced parity symbol streams; and
selecting symbols to bo trans mined according to a given data rate, from the concatenated
symbols.
In accordance with a ninth aspect of the present invention, there is provided an
apparatus for decoding all or some of the received code s\mbois generated by encoding
an information symbol stream according to a gi\en code rale using a Quasi-
Complementary Duo-Binary Turbo Code (QC-DBTC) encoder. The apparatus comprises
a selector for inserting a predetermined code symbol in a position corresponding to a
punctured symbol among received symbols; a deinlerlacer for deinlcrlacing parity
symbols among the symbols generated by the selector; a quad-symbol mapper for quad-
mapping systematic symbols among the symbols generated by the selector; a plurality of
deinlerleavers for independently deinterlcaving the quad-mapped systematic symbol
streams and the deintcrlaced parity symbol streams; a quad-symbol dernapper for quad-
demapping the deiuterleaved systematic symbol stream; a code symbol concatcnator for
concatenating an output of the quad-symbol dernapper to the deiuterleaved parity
symbol streams; and a QC-DBTC decoder for QC-DBTC decoding the concatenated
symbol streams.
BRIEF DESCRIPTION OF THeIdRAWINGS
The above and other objects, features and advantages of the present invention
will become more apparent from the following detailed description when taken in
conjunction with the accompanying drawings in which:
FIG. I is a block diagram illustrating structures of physical channels for
transmitting high-rate data to a user in an 1EEH 802.16a system using Orthogonal
Frequency Division Multiplexing (OFDM);
FIG. 2 is a block diagram illustrating structures of physical channels for
transmitting data to a user in a current HPi high-rate data system;
FIG. 3 is a block diagram illustrating an apparatus for generating rate R¦¦-1/2
duo-binary turbo codes;
FIG. 4 is a block diagram illustrating an apparatus for generating R=1.3 duo-
binary turbo codes;
FIG. 5 is a block diagram illustrating a QCTC symbol generator it: a
CDMA2U00 lxEV-DYs> stern:
FIG. 6 i.s a block diagram illustrating a structure of a QC-DBTC encoder having
a code rate R-1 3 and using duo-binary turbo codes according to an embodiment of the
present invention.;
FIG. 7 is a block diagram illustrating a structure of a receiver in a QC-DBTC
system according to an embodiment of the present invention;
F!G 8 is a block diagram illustrating a structure of a transmitter in a QC-DBTC
system according to another embodiment of the present invention; and
FIG 9 is a block diagram illustrating a structure of a transmitter in a QC-DBTC
system according to another embodiment of the present invention.
Throughout the drawings, like reference numerals will be understood to refer to
like parts, components and structures.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
Several exemplary embodiments of the present invention will now be described
in detail with reference to the annexed drawings. In the following description, a detailed
description of known functions and configurations incorporated herein has been omitted
for conciseness.
FIG. 6 is a block diagram illustrating a structure of a QC-DBTC encoder having
a code rate R=l/3 and using duo-binary turbo codes according to an embodiment ol'the
present invention. With reference to FIG. 6, a detailed description will now be made of a
structure and operation of a QC-DBTC encoder having a code rate R-l/3 and using duo-
binary turbo codes according to an embodiment of the present invention. In FIG. 6. a
turbo encoder 610 is substantially identical in structure to that of the turbo encoder
described with reference to FIG. 4. FIG. 4 is a block diagram illustrating an apparatus for
generating R 1 \3 duo-binary turbo codes. Therefore, an internal structure of the turbo
encoder 610 will be described with reference to FIG. 4.
The QC-DBTC encoder illustrated in FIG. 6 is similar in structure to a
conventional QCTC encoder using binary turbo codes except for the inclusion or" a
process of processing .systematic symbols. This is required because in the case of diie-
binary turbo codes, as illustrated in FIGs. 3 and 4, N_EP systematic symbols are divided
into systematic symbol streams A and B. each comprised of N HP Z systematic symbols.
Respective symbols A i and B 1 are encoded in pairs by a first constituent encoder 401.
or encoded in pairs by a second constituent encoder 403 after being turbo-interleaved by
a turbo interleave!" 402. That is, each of information stream pairs A and B is defined as
an information stream pair defined by one transition process on a trellis diagram of each
constituent encoder, and a size of the symbol streams is defined as N_EP.'2. Therefore,
the QC-DBTC encoder receiving the information stream pairs performs symbol
classification based on the symbol pairs A i and B_i as illustrated in FIG 6. Thai is, A_ i
and B i are mapped to quad-symbols before being block-interleaved.
The encoding process will now be described in detail. For convenience, the
description will be made herein with reference lo rale R=l 3 duo-binary turbo codes.
However, the encoding process can also be applied to duo-binary turbo codes having a
code rate I."2 or other code rales without a change in structure or encoding scheme of the
duo-binary turbo codes. The change in code rate simply increases the number of parity
symbol groups so that the code rate is reduced.
Jfncodinu Process
Step I: Output Symbol Classification of Duo-Binarv Turbo Codes
Referring lo FIG 6, the turbo encoder 610 using R-l. 3 duo-binary turbo codes
as mother codes, performs turbo coding on N_EP input information symbols. The turbo
coding process is substantially identical to the conventional duo-binary turbo coding
process. Therefore, the duo-binary turbo encoder 610 generates 3xN__EP code symbols.
Reference numeral 612 shows a process of separating output symbols of the duo-binary
turbo encoder 610 into systematic symbols and parity symbols, and then concatenating
the separated symbols. Among the code symbols generated in this manner, systematic
symbols are divided into two systematic symbol streams A and B, each comprised of
N_HP.'2 symbols, and parity symbols are divided into four parity symbol streams CI 1,
CI2, C21 and C22, each comprised of N_EP/2 symbols, as illustrated in FIG. 6. It can be
noled that the number of sub-blocks of systematic symbols in the QC-DBTC coding
scheme is higher by one than in the conventional QCTC coding scheme of FIG. 5 A
mapping relation of the input systematic symbols wil[ now be described. If input
systematic sunbols are denoted by S(,k) (wherein k"0. 1. 2. 3.--. N HP-1), A i and B i
arc defined as in equation (1) and Equation (2). respectively, shown below.

Step 2: Ouad-Svmbol Mapping of Systematic Symbols
As illustrated in FIG. 6. the systematic symbol streams A and B are mapped to
quad-symbols in accordance with a quad-symbol mapping table described in greater
detail below. The quad-symbol mapping is performed by a quad-symbol mapper 630 in
such a manner that A i and B_i arc mapped to m i (wherein i" (). 1, 2,--, K EP/2-1).
This is equivalent to calculating A i and B i in accordance with liquation (1) and
Equation (2). Therefore, a newly generated systematic symbol stream M has a si/e of
N_EP 2. There are various possible mapping rules between A i, B_i, and mi. Herein, a
mapping rule for mapping A_i and B_i to mi by binary expression will be used as a
typical example of the possible mapping rules. Regardless of the mapping rule used, it is
important that the new systematic symbol stream M has a si/e of N_ FP.-2 by quad-
symbol mapping like the conventional binary QCTC', and that each quad-symbol is
mapped to an i"! systematic symbol pair A i and B_i. A quad-symbol mapping table is
illustrated below in Table 1.

Step 3: Classification of Parity Symbols
Next, the code symbols arc separated into a systematic symbol group (or sub-
block M) and a plurality of parity symbol groups (or sub-blocks YO, VI. Y'O. and Y'l),
and then demultiplexed into 5 sub-blocks. Here, this operation is defined as '"code
symbol separation", and is denoted by reference numeral 614 in FIG. 6. The code symbol
separator 614 is substantially identical in operation to the conventional QCTC symbol
separator 514. An operation performed by the code symbol separator 614 can be
expressed as in Equation (3) to Equation (6) shown below.

Step 4: Sub-block Interleaving and Interlacing
Next, the respective sub-blocks undergo independent interleaving, and this is
called '"sub-block interleaving". The sub-block interleaving is achieved by (he PBRO
intcrlcavers 616a. 616b, 616c, 616d, and 616e. Here, all of the sub-blocks have the same
size of NEP.-2. Subsequently, parity symbols YO and Y'O generated in each sub-block
are interlaced and then rearranged, generating a new group. Similarly, parity symbol Yl
and Y'l generated in each sub-block arc also interlaced and then rearranged, generating
a new group. Here, each of (he groups, or parity symbol streams, has a size o'\ N FP Z.
The interlacing is achieved b\ interlacers 61 Sa and 6i Sb.
Step 5: Quad-Symbol Inverse Mapping of Systematic Symbols
Next. N F.P--2 systematic symbols are calculated from a systematic symbol
stream M' newly generated by sub-block interleaving, by demapping (inverse-mapping)
a quad-symbol back to binary symbols A i' and B i' in accordance with Table 1.
Referring to Table 1, A i and B i can be regarded as A_i' and B_i\ respectively, for
example, m_i=3 is mapped to (A i. B_i)~(l,l). As described above, there are various
possible mapping rules, and the present invention has no limitation on the mapping rules.
The mapping of m_i can be expressed as in Equation (7) below.

The quad-demapping in accordance with Equation (7; or other methods is
achieved by a quad-symbol demapper 640.
Step 6: QC-DBTC Symbol Concatenation
Next, a sub-block comprised of interleaved systematic symbols and 2 interlaced
parity groups are rearranged in a regular order and then concatenated, thus generating
one new sequence. Here, this operation is denoted by "QC-DBTC Symbols" and
reference numeral 620 in FIG. 6. Through a series of the processes described above,
symbol rearrangement for generating QC-DBTC codes is completed. The QC-DBTC
symbol rearrangement can be expressed as in Equation (8) below.

In Equation (8), {a|b} denotes a new sequence obtained by serial-concatenating
two sequences 'a' and 'b' and ITRa,b) denotes mutual-interiacing of'two sequences 'a"
and 'b'. ThaL is. the sequences 'a' and "b" are interlaced in the order of a_ 0. b 0. a i.
b .1, a 2. b.2. -, a M. h_M.
Step "¦ QC-DBTC Symbol Selection
Ne\i, a QC-DBTC symbol selector 622 generates QC-DBTC codes Inning
various code rates by selecting random symbols from 3xN HI' symbols. A scheme for
generating the QC-DBTC codes having various code rates is well disclosed in Korean
Patent Application No. P2001-0007357, entitled "Code Generating Apparatus and
Method in a Code System," filed by the applicant, the entire content of which is
incorporated herein by reference.
As described above, QC-DBTC is different from the conventional binary QCTC
in Step 2 and Step 5. The reason for using the quad-symbol mapping is as follows.
First, the use of the quad-symbol mapping makes a si/e of the systematic
symbol groups be equal to a size of the parity symbol groups. Therefore, a transmitter
includes only one sub-block interleaving device. That is, the use of the same sub-block
size contributes to a simplification of the parameters and algorithm for sub-block
interleaving. Generally, PBRO interleaving is used as the sub-block interleaving.
Second, as the use of the quad-symbol mapping makes a si/e of the systematic
symbol groups be equal to a si/c of the parity symbol groups, a receiver also includes
only one sub-block interleaving device. The receiver preferably implements sub-block
interleaving using an inverse function of the interleaving used in the transmitter, and
generally, the use of an inverse function for interleaving causes an increase in
implementation complexity of deinterleaving. In addition, the use of different sub-block
sizes causes an increase in implementation complexity in proportion thereto. Therefore,
the use of the same sub-block size enables the use of a single inverse function.,
contributing to a reduction in complexity of the receiver.
Third, the use of the quad-symbol mapping can improve a channel interleaving
depth as compared with a scheme lor separately sub-block-interleaving s\stcma:;e
symbol streams A and B. It is well disclosed in related references t!;ai an increase in
channel interleaving depth generally improves interleaving perform:*:.-:e. In particular,
the channel interleaving depth is an important performance parameter in a mobile
communication system, and as noted above in regard to the conventional binary QCTC.
QCTC has a structure of integrating FEC coding and channel interleaving into one
scheme. Therefore, even though QCTC has the same coding gain, it is preferable
because of its structure to improve performance of channel interleaving. In this context.
the quad-symbol mapping structure can extend a channel interleaving area of systematic
symbols up to N_EP. However, the scheme for separately sub-block-interleaving
systematic symbol streams A and B is limited to N_EP,2 in terms of channel interleaving
area.
FIG. 7 is a block diagram illustrating a structure of a receiver in a QC-DBTC
system according to an embodiment of the present invention. With reference to FIG. I7, a
detailed description will now be made of a structure and operation of a receiver in a QC-
DBTC system according to an embodiment of the present invention.
The receiver performs an inverse process of QC-DBTC used in the transmitter,
and restores N_EP systematic symbols from received codeword symbols. With reference
to FIG. 7. a description will now be made of a process of restoring systematic symbols. A
QC-DBTC symbol selector 710 converts received symbols q.,-,, qi, ¦¦¦, qy.;.i to quad-
symbols comprised of parity symbols and systematic symbols. The quad-symbols are
denoted by reference numeral 712. Because the quad-symbols are separately comprised
of systematic symbols and parity symbols, the systematic symbols are output intact and
the parity symbols are divided into interlaced symbols 7L4a and 714b. The interlaced
symbols 714a and 714b arc separated into corresponding parity symbols through a
deinterlacing process. The systematic symbols are mapped to quad-symbols by a quad-
symbol mapper 730. The parity symbol streams separated through the deinterlacing
process and the systematic symbol stream are input to their associated PBRO processors
7!6a, 716b, 716c. 716d, and 716c, and the PBRO processors 716a, 716b. 716c, 7l6d,
and 716e PBRO-rcarrange the input symbols. The output symbols 718 of the PBRO
processors ~16a. 71 Ob. T16c, 7 Kid, and 7 I 6c arc equal to the output symbols of the code
symbol separator 6! 4 of FIG 6.
li should be noted herein that, because N__LP systcrriatic symbols q k iwherein
k=0, I, 2, 3.--. N_EP-1) have real values, the receiver, unlike the transmitter, cannot
quad-symbol-map the systematic symbols to (0,0), (0,1). (1,0), (1.1) as shown in Tabic 1.
Therefore, symbol positions (q_k, q k- 1) (where k=0, 2. 4,--. N FP-2) corresponding to
A_i' and B_F are concatenated into one symbol pair (q_k, q_ k ¦¦ i). wherein the symbol
pair is regarded a quad-symbol and size-N_EP.-2 PBRO interleaving is achieved. Thai is,
what is preferably done is to simply match the symbol positions of q_k and q k • 1. An
example of such a mapping rule is illustrated in Table 2.

In the same manner, parity symbols are divided into 4 partly blocks by
deinlerlacing, and the parity blocks arc divided into V0, Yl, Y'O and Y'l, respectively,
and then converted to CI I, CI2, C21 and C22, by PBRO sub-block deinterleaving. Also,
the systematic symbols M' are restored to their original order by PBRO sub-block
deinterleaving.
Next, a quad-symbol demapper 740 converts m_i (wherein i¦¦--(), 1, 2. ,-¦-, N! FP-
!) to (A i, B i) through an inverse process of the transmitter. Next, all of 3N_FP code
symbols obtained by concatenating A, B, CTI, CI2, C21 and C22 are input to a duo-
binary turbo encoder 722. For reference, when a code rate is higher than 1.3, the number
of svmbols actually transmitted is less than 3N EP, and in this case, an erasure symbol is
added to q i corresponding to a symbol position where no symbol is transmitted and a
QC-DBTC reception operation is performed in the foregoing process.
FIG 8 is a block diagram illustrating a structure of a transmitter in a QC-DBTC
system according to another embodiment of the present invention. In FIG. 8, only the
scheme for extending a si^e oi"the systematic symbols to NEP is described in detail.
As illustrated in Fit.,, i, the scheme is substantially the same as the conventional
QCTC scheme in structure, hut different in that the scheme of l-'IG. 8 uses a binary turbo
encoder. Also, compared with the structure of FIG. 6. the structure of FIG 8 does not
include a quad-symbol mapper and a quad-symbol demapper. The structure of l-'IG. 8 is
substantially identical to the structure of FIG 6 except for the absence of a quad-symbol
mapper and a quad-symbol demapper, and only those differences in structure and
function between them will be described. As can be understood from FIG 8, systematic
symbols among the code symbols output from a turbo encoder 810 are doubled in terms
of size of a PBRO sub-block interleavcr 816a associated with the systematic symbols,
while all of the PBRO sub-block interlcavers 616a to 616c for the conventional QCTC
codeword have same size. Systematic symbol streams A and B are alternately arranged
in the order of A_0, B_0, A_l, B_l, A_2, B .2, -, A then input to the PBRO sub-block interleave!' 816a. Such a structure is advantageous in
that channel interleaving is performed on a pcr-binary symbol basis, thai is. on a per-bit
basis, thereby improving randomness of channel interleaving. However, this scheme is
disadvantageous in that, because the sub-block for systematic symbols is different in si/.e
from the sub-blocks for parity symbols, a transmitter and a receiver both require two
PBRO sub-block interleaving devices. However, because a channel interleaving depth is
extended to N EP in the QC-DBTC scheme illustrated in FIG. 6, a difference between
the extended channel interleaving depth and a bit-basis channel interleavcr depth of FIG.
8 is negligible.
In another alternative embodiment, only a binary turbo encoder is used while a
structure of a QCTC code generation apparatus remains unchanged. In this embodiment,
because the number of systematic symbols output from the binary turbo encoder is
doubled unlike that in the QCTC scheme, the number of sub-block interlcavers is
extended to 2 (MO and Ml). Therefore, all of the sub-block interlcavers have the same
size of N EP.2, like those in FIG. 6. Such a scheme is illustrated in l-'IG. 9. Here, only
the differences between the structure and function of FIG. 9 and FIG. 6 will be described.
The scheme of I'M. 9 has two PBRO sub-block interleave-!* for systematic
symbols. In FIG. 9. sub-block imerleavers 916al and 916a2 for systematic symbols lia\e
the same size as thai, ol' sub-block inter!cavers 9i6b. 9'.6c, 916*1 ant! 916d for purity
symbols. Therefore, the systematic symbol streams A and B are sequentially arranged in
their associated sub-blocks MO and Ml. subjected to independent PBRO sub-block
interleaving, and then sequentially arranged in a QC-DBTC symbol stream.
Such a structure is advantageous in that channel interlea\ing is performed on a
pcr-binary symbol basis, that is, on a per-bit basis, and all of the sub-blocks can use the
same-sized PBRO interleaving devices. However, this scheme is disadvantageous in lhal,
because the sub-blocks for the systematic symbols have a small size of N HP. 2 and are
arranged in parallel in a QC-DBTC symbol stream, a channel interleaving depth is
limited to N EP2 as compared with the conventional scheme of FIG. 6.
As described above, the present invention can generate codes having various
code rates in a high-rate wireless data system in which a duo-binary turbo code for
selecting one of multiple modulation schemes and one of multiple FHC coding schemes
before transmission is used as a mother code. In MARQ, the present invention can
provide various sub-codewords and redundancies with a simple QC-DBTC encoder,
thereby maximizing transmission efficiency of the system.
While the invention has been shown and described with reference to certain
exemplary embodiments thereof, it will be understood by those skilled in the art lhal
various changes in form and details may be made therein without departing from the
spirit and scope of the invention as defined by the appended claims.
We Claim:
1. An apparatus for generating Quasi-Complementary Duo-Binary Turbo
Codes (QC-DBTC), comprising:
a duo-binary turbo encoder (810) having a plurality of constituent
encoders for receiving an information symbol stream (800), and generating a
plurality of systematic symbol streams and a plurality of parity symbol
streams according to a given code rate, wherein the plurality of parity symbol
streams are generated from the plurality of constituent encoders associated
thereto and the parity symbol streams from one of the plurality of constituent
encoders correspond to the parity symbol streams from another one of the
plurality of constituent encoders;
a quad-symbol mapper(630) for quad-mapping the plurality of systematic
symbol streams to one symbol stream;
a channel interleaver (816 a) for interleaving the quad-mapped systematic
symbol stream and the plurality of parity symbol streams from the plurality of
constituent encoders, quaddemapping the quad-mapped systematic symbol
stream, interlacing symbol streams in the plurality of parity symbol streams
corresponding to each other from among the interleaved parity symbol
streams, and serial-concatenating the quaddemapped systematic symbol
stream and the interlaced parity symbol streams; and
a duo-binary turbo code generator (822) for repeating the serial-
concatenated symbol stream, and selecting a predetermined number of
symbol streams from the repeated symbol streams according to the given
code rate and selection information thereby generating QC-DBTC codes.
2. The apparatus as claimed in claim 1, wherein the quad-mapped
systematic symbol stream output from the quad-symbol mapper is 1/2 the
size of the plurality of systematic symbol streams.
3. The apparatus as claimed in claim 1, wherein the quad-mapped
systematic symbol stream output from the quad-symbol mapper is equal
in size to the QC-DBTC codes.
4. The apparatus as claimed in claim 1, wherein the quad-mapped
systematic symbol stream output from the quad-symbol mapper is equal
in size to the plurality of parity symbol streams.
5. The apparatus as claimed in claim 1, wherein the channel interleaver
comprises:
a plurality of interleavers (816b to 816e) for interleaving the quad-
mapped systematic symbol stream and the plurality of parity symbol streams
output from the plurality of constituent encoders;
a quad-symbol demapper (640) for quad-demapping the quadmapped
systematic symbol stream;
an interlacer (818) for interlacing the interleaved parity symbol streams;
and
a symbol concatenator (820) for serial-concatenating the quaddemapped
symbol streams and the interlaced parity symbol streams.
6. The apparatus as claimed in claim 1, wherein a code rate of the duo-
binary turbo encoder is 1/3.
7. A method for generating Quasi-Complementary Duo-Binary Turbo Codes
(QC-DBTC), comprising the steps of: receiving an information symbol
stream and generating a plurality of systematic symbol streams and a
plurality of parity symbol streams according to a given code rate;
Quad-mapping the plurality of systematic symbol streams to one
symbol stream;
interleaving the quad-mapped symbol stream and the plurality of
parity symbol streams;
quad-demapping the interleaved systematic symbol stream;
interlacing the plurality of parity symbol streams in pairs;
serial-concatenating the interlaced parity symbol streams and the
quad-demapped systematic symbol stream; and
repeating the serial-concatenated symbol stream, and selecting a
predetermined number of symbol streams from the repeated symbol
streams according to the given data rate.
8. The method as claimed in claim 7, wherein the interleaving step
comprises the steps of:
interleaving the quad-mapped systematic symbol stream and the plurality
of parity symbol streams;
quad-demapping the quad-mapped systematic symbol stream;
interlacing the interleaved parity symbol streams; and
serial-concatenating the quad-demapped systematic symbol stream and
the interlaced parity symbol streams.
9. An apparatus for generating code symbols by encoding an information
symbol stream according to a given code rate using a Quasi-
Complementary Duo-Binary Turbo Code(QC-DBTC) encoder and selecting
all or some of code symbols to be transmitted from among the generated
code symbols, the apparatus comprising;
a QC-DBTC encoder (810) for receiving an information symbol stream
(800) and generating QC-DBTC symbol streams according to a
predetermined code rate;
a separator (812) for separating the generated QC-DBTC symbol
streams into a plurality of systematic symbol streams and a plurality of
parity symbol streams, the systematic symbol streams being connected
into one symbol stream;
a plurality of interleaves (816b to 816e) for interleaving the plurality
of parity symbol streams, respectively;
a systematic symbol stream interleaver (816a) for interleaving the one
systematic-symbol stream;
a plurality of interlacers (818a,818b) for interlacing the plurality of
parity symbol streams in pairs;
a concatentor (820) for serial-concatenating the interleaved systematic
symbol stream and the interlaced parity symbol streams, and
a symbol selector (822) for repeating the serial-concatenated symbol
stream, and selecting a predetermined number of symbol streams from the
repeated symbol streams according to the given data rate and selection
information thereby generating QC-DBTC codes.
lO.The apparatus as claimed in claim 9, wherein the separator interlaces the
plurality of systematic symbol streams into one systematic symbol stream,
ll.The apparatus as claimed in claim 9, wherein the systematic symbol
stream interleaver is two times larger in size than one of the plurality of
interleavers for interleaving the parity symbol streams.
12. A method for generating coded symbols by encoding an information
symbol stream according to a given code rate using a Quasi-
Complementary Duo-Binary Turbo Code (QC-DBT-C) encoder and
selecting all or some of code symbols to be transmitted from among the
generated code symbols, the method comprising the steps of:
receiving an information symbol stream and generating QC-DBTC
symbols, streams according to a predetermined code rate;
separating the generated QC-DBTC symbol streams into a plurality of
systematic symbol streams and a plurality of parity symbol streams,
interlacing the plurality of systematic symbol streams into one systematic
symbol stream;
interleaving the plurality of parity symbol streams, respectively;
interleaving the one systematic symbol stream;
interlacing the plurality of parity symbol streams in pairs;
serial-concatenating the interleaved systematic symbol stream and the
interlaced parity symbol streams; and
repeating the serial-concatenated symbol stream, and selecting a
predetermined number of symbol streams from the repeated symbol streams
according to the given code rate and selection information thereby generating
QC-DBTC codes.
13. An apparatus for decoding all or some of the received code symbols
generated by encoding an information symbol stream according to a given
code rate using a Quasi-Complementary Duo-Binary Turbo Code (QC-
DBTC) encoder, the apparatus comprising:
a selector (710) for inserting a predetermined code symbol streams in a
position corresponding to a punctured symbol stream among received
symbols;
a deinterlacer (714a, 714b) for deinterlacing a plurality of parity symbols
streams among the symbol streams generated by the selector;
a quad-symbol mapper (730) for quad-mapping a plurality of systematic
symbols among the symbol streams generated by the selector;
a plurality of deinterleavers (716a to 716e) for deinterleaving the quad-
mapped systematic symbol streams and the deinterlaced parity symbol
streams, respectively;
a quad-symbol demapper (740) for quad-demapping the deinter-leaved
systematic symbol streams;
a code symbol concatenator (720) for concatenating the quad-symbol
demapped systematic symbol streams and the deinterleaved parity symbol
streams; and
a QODBTC decoder (722) for QC-DBTC decoding the concatenated
symbol streams.

The invention relates to an apparatus for generating Quasi-Complementary Duo-
Binary Turbo Codes (QC-DBTC), comprising a duo-binary turbo encoder (810)
having a plurality of constituent encoders for receiving an information symbol
stream (800), and generating a plurality of systematic symbol streams and a
plurality of parity symbol streams according to a given code rate, wherein the
plurality of parity symbol streams are generated from the plurality of constituent
encoders associated thereto and the parity symbol streams from one of the
plurality of constituent encoders correspond to the parity symbol streams from
another one of the plurality of constituent encoders; a quad-symbol mapper(630)
for quad-mapping the plurality of systematic symbol streams to one symbol
stream; a channel interleaver (816 a) for interleaving the quad-mapped
systematic symbol stream and the plurality of parity symbol streams from the
plurality of constituent encoders, quaddemapping the quad-mapped systematic
symbol stream, interlacing symbol streams in the plurality of parity symbol
streams corresponding to each other from among the interleaved parity symbol
streams, and serial-concatenating the quaddemapped systematic symbol stream
and the interlaced parity symbol streams; and a duo-binary turbo code generator
(822) for repeating the serial-concatenated symbol stream, and selecting a
predetermined number of symbol streams from the repeated symbol streams
according to the given code rate and selection information thereby generating
QC-DBTC codes.

Documents:

02629-kolnp-2005-abstract.pdf

02629-kolnp-2005-claims.pdf

02629-kolnp-2005-description complete.pdf

02629-kolnp-2005-drawings.pdf

02629-kolnp-2005-form 1.pdf

02629-kolnp-2005-form 2.pdf

02629-kolnp-2005-form 3.pdf

02629-kolnp-2005-form 5.pdf

02629-kolnp-2005-international publication.pdf

2629-KOLNP-2005-ABSTRACT 1.1.pdf

2629-KOLNP-2005-CLAIMS 1.1.pdf

2629-KOLNP-2005-CORRESPONDENCE 1.1.pdf

2629-KOLNP-2005-CORRESPONDENCE.pdf

2629-KOLNP-2005-FORM 27.pdf

2629-KOLNP-2005-FORM-27.pdf

2629-kolnp-2005-granted-abstract.pdf

2629-kolnp-2005-granted-claims.pdf

2629-kolnp-2005-granted-correspondence.pdf

2629-kolnp-2005-granted-description (complete).pdf

2629-kolnp-2005-granted-drawings.pdf

2629-kolnp-2005-granted-examination report.pdf

2629-kolnp-2005-granted-form 1.pdf

2629-kolnp-2005-granted-form 18.pdf

2629-kolnp-2005-granted-form 2.pdf

2629-kolnp-2005-granted-form 3.pdf

2629-kolnp-2005-granted-form 5.pdf

2629-kolnp-2005-granted-gpa.pdf

2629-kolnp-2005-granted-reply to examination report.pdf

2629-kolnp-2005-granted-specification.pdf

2629-kolnp-2005-granted-translated copy of priority document.pdf

2629-KOLNP-2005-OTHERS.pdf

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Patent Number

238707

Indian Patent Application Number

2629/KOLNP/2005

PG Journal Number

08/2010

Publication Date

19-Feb-2010

Grant Date

17-Feb-2010

Date of Filing

19-Dec-2005

Name of Patentee

SAMSUNG ELECTRONICS CO., LTD.

Applicant Address

416, MAETAN-DONG, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO

Inventors:

#	Inventor's Name	Inventor's Address
1	SANG-HYUCK HA	#121-1003, JUGONG 1-DANJI APT., 1314 GWONSEON-DONG, GWONSEON-GU, SUWON-SI GYEONGGI-DO
2	YOUNG-MO GU	#411-704, POONGLIM APT., YEONKKOTMAEUL, JEONGJA-DONG, JANGAN-GU
3	MIN-GOO KIM	#102-902, HYUNDAI HOME TOWN, YEHYEONMAEUL, 705, SEOCHEON-RI, GIHEUNG-EUP, YONGIN-SI, GYEONGGI-DO

PCT International Classification Number

H03M 13/37

PCT International Application Number

PCT/KR2005/000184

PCT International Filing date

2004-01-20

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	10-2004-0004246	2004-01-20	Republic of Korea