Title of Invention	"A VERTICAL MOS STRUCTURE"
Abstract	This invention relates to a vertical MOS structure. The MOS structure has field oxide structures having a Z shape gate oxide structure secured therebetween. A source/drain is provided on the lower surface of the upper and lower arm of said Z-shaped gate structure. A poly structure is provided on the vertical component of said Z-shape gated oxide.

Full Text

This invention relates to a vertical MOS structure. Silicon MOS technology has made tremendous progress in last few years. MOS is one of the most fascinating devices ever known. Reduction of feature size to get more packing density and better performance is one of the focus areas for the research and development in this field. Although interconnection layers are successfully being stacked in the vertical direction, the attempts to develop vertical MOS structures are not yet successful. About a decade ago, vertical MOS structure using poly silicon had been tried. However, this could not find any practical use as the mobility of poly silicon is very low as compared to single crystal silicon. The reduction of channel length always impose challenges as per scaling rules. Problems due to drain induced barrier lowering (DIBL), channel length modulation, lowering of threshold voltage (VT), hot electron degradation, parasitic bipolar switch on (snap back) etc. have to be taken care during design and fabrication of the smaller channel length MOS devices. Several parameters have to be optimized to get best results. For example to obtain low value of leakage, higher V_ ^s to be targeted. Smaller junctiondepth (X .), lightly doped drain (LDD) structure, control of line width of gate (Poly), etc. are becoming complicated, as the channel length is going below 0.5 um, and generally being tackled by high cost equipments An object of this invention is to propose a new vertical MOS structure having several distinct advantages compared to conventional MOS structures. Another object of this invention is to propose a new vertical MOS structure having improved packing density and better performance. Yet another object of this invention is to propose a new vertical MOS structure which can be easily integrated with standard MOS technologies. According to this invention there is provided a vertical MOS structure characterised in that field oxide structures (1) having a Z shape gate oxide structure (3) secured therebetween, a source/drain (2) being provided on the lower surface of the upper 3(a) and lower arm 3(b) of said Z-shaped gate structure, a poly structure (4) being provided on the vertical component 3(c) of said Z-shaped gate oxide (3). In accordance with this invention field oxide structures are secured at the end of a gate oxide structure provided in the Z shape. A source/drain structure is provided on the lower surface of the upper and lower arms of the Z shape gate oxide structure. A poly structure provided on the vertical portion of the Z shape gate oxide structure and is extended on the upper surface of said gate oxide structure. riKSCRIPTlOHOr THE ACCOMPANYING DRAWINGS. A mask structure according to a preferred embodiment is herein described and illustrated in the accompanying drawings wherein: Fig. i shows the NMOS structure known in the art. Fig. 2 shows vertical NMOS structure and Fig. 3 shows sectional view of NMOS vertical structure. Referring to the drawings particularly fig. 1 the NMOS structure comprises field oxide structure 1 having source/drain structure 2. provided at the ends of the field oxide structure, which are facing towards each other. A gate oxide structure 3 is provided between the! source/drain structure 2 to connect, said structures 1 with each other. A poly structure 4 is provided on the| upper surface of the gate oxide structure 3. A spacer 5 is provided on both the sides of the poly and/or gate oxide 3. These features are as such known in the art and do not constitute the inventive features of this invention. Specifically according to this invention the NMOS structure comprises field oxide structure 1 provided on either ends of a Z shaped gate oxides structure 3. Source/drain structure 2 are provided on, the lower surface of the upper arm 3(a) and lower arm 3(b) of the gate oxide structure. A poly structure 4 is provided on one side of the vertical arm 3(c) of the Z shape gate oxide structure 3. The ends of the poly structure 4 being extended on the upper surface of the upper arm 3(a) and 3(b) of the gate oxide structure 3 near the vertical arm 3(c) of the structure 3. Reference is now made to fig. 3 wherein the topological diagram of mask layout is shown. A plurality of metal structures 6 having contacts 7 provided therewith are disposed in an active structure 8 which is disposed in a PMOS structure 9. The PMOS structure is disposed in an N tub 10 required only for PMOS structure. The gate structures 11 provided on both the sides of a etch mask 12 are disposed into said active structure 8 having a metal structure 6 provided between the gate structures 11. Although only a MOS structure/transistor is shown in the drawings. However, PMOS structure/transistor can also be realized. The process for the fabrication/manufacture is shown in the following table 1. Table-1: A Typical Process Flow lor Fabrication of Vertical NMOS structure. (Table Removed) Standard CMOS process parameter (except at serial # 11 & 16) can be used. In case, definition of N+of the vertical transistor is done during N+source/drain of the conventional transistor then only step at serial no. 11 will be different. After 17, conventional process flow can be used. However, as explained later LDD process which generally requries two masking steps will not be required. It is clear from Table i that this structure can easily be integrated with conventional CMOS process. The effective channel length will be decided by step height on silicon and junction depths of N+-. Therefore deep submicron channel length can be fabricated even without high precision state of the art lithography and etching tools. However, it must be noted that it is not possible to vary channel length of these structures once the process is defined. Transistor width of this structure can be defined by mask and can be varied. Therefore in some applications, which require larger channel lengths (more than the minimum), the vertical transistors have to be integrated with conventional ones and will need three extra masks, 1 for creating vertical step and 2 for N+- and P+ source drains. However, separate masks for N+ and P+ will not be required if these are done along with source—drain implant of conventional transistors. This may have some performance penalty. However, it must be noted that since LDD structures are not required for higher channel lengths, steps which generally includes 2 masks, can be* eliminated from the process. The topological diagrams giving the mask layout for a NMOS and PWOS vertical transistors are shown in fig. 2. The structure of the present invention has several advantages as given below: a) Improvement of the packing density as the channel length is denied in the vertical direction. b) Enhance DIBL and snapback resistance and therefore can have better performance as compared to conventional MOS structure, c) Deep submicron Left can be obtained without any limitation being imposed by the capabilities of lithography and etching tools, d) Elimination of some of the most critical process modules. WE CLAIM; 1. A vertical MOS structure characterised in that field oxide structures (1) having a Z shape gate oxide structure (3) secured therebetween, a source/drain (2) being provided on the lower surface of the upper 3(a) and lower arm 3(b) of said Z-shaped gate structure, a poly structure (4) being provided on the vertical component 3(c) of said Z-shaped gate oxide (3). 2. A vertical MOS Structure as claimed in claim 1 wherein the ends of said poly structure (4) are extended on the upper surface of said upper 3(a) and lower arms (3b) of the Z shaped gate oxide structure (3).

Documents:

2625-del-1997-abstract.pdf

2625-del-1997-claims.pdf

2625-del-1997-correspondence-others.pdf

2625-del-1997-correspondence-po.pdf

2625-del-1997-description (complete).pdf

2625-del-1997-drawings.pdf

2625-del-1997-form-1.pdf

2625-del-1997-form-19.pdf

2625-del-1997-form-2.pdf

2625-del-1997-form-3.pdf

2625-del-1997-form-5.pdf

2625-del-1997-form-6.pdf

2625-del-1997-gpa.pdf

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