Title of Invention	A NOVEL PROCESS FOR MANUFACTURING SILICON NANOSTRUCTURES IN SINGLE CRYSTALLINE SILICON AND SILICON NANOSTRUCTURES MADE THEREBY USEFUL FOR MAKING ELECTRONIC DEVICES.
Abstract	A novel process for manufacturing silicon nonostructures in single crystalline silicon useful for making electronic devices which comprises placing a conducting mesh mask above a single crystalline semiconductor substrate so as to extend mesh shadow on the said substrate, irradiating the said mesh mask with an ion beam of energy of at least 75 MeV to provide ion flux in the range of 5 x 108 - 5 x 109 ions.cm-2 sec-1 in the said substrate to obtain semiconductor nonostructure in single crystalline semiconductor substrate

Title of Invention

A NOVEL PROCESS FOR MANUFACTURING SILICON NANOSTRUCTURES IN SINGLE CRYSTALLINE SILICON AND SILICON NANOSTRUCTURES MADE THEREBY USEFUL FOR MAKING ELECTRONIC DEVICES.

Abstract

A novel process for manufacturing silicon nonostructures in single crystalline silicon useful for making electronic devices which comprises placing a conducting mesh mask above a single crystalline semiconductor substrate so as to extend mesh shadow on the said substrate, irradiating the said mesh mask with an ion beam of energy of at least 75 MeV to provide ion flux in the range of 5 x 108 - 5 x 109 ions.cm-2 sec-1 in the said substrate to obtain semiconductor nonostructure in single crystalline semiconductor substrate

Full Text	The present invention particularly relates lo a novel process for manufacturing silicon nanostructures in single crystalline silicon and silicon nanostructurcs made thereby useful for making electronic devices The invention provides a technology for fabrication of silicon nanostructures in crystalline silicon, at predetermined locations, by employing million electron Volt (MeV) ion irradiation. The energy supplied by the McV ions arc trapped at prescribed locations (irradiation interfaces) in a crystalline solid such that the size of the nanostructures depends upon the beam parameters and do not require any extraneous methods based on pattern delineation, employing masks. And therefore, the technique is suitable for the development of mask-less nano fabrication. The technique is intrinsic in nature and therefore leads to produce pure Si nanostructurcs in a single crystalline Si lattice. Nanostructures provide tunable electronic properties, based on their size, which is markedly different than bulk materials. Therefore their potential is well recognized for enhancing the capabilities of electronic devices, which can be fabricated employing nanostructures. For example, increased photoluminesccncc, reduced band gaps and atom-like electronic states would provide increased switching speed, low power consumption, and possibility for integrated opto-elcctro-mechanical devices. Fabrication of nanostructures in silicon have been reported in technical literature, using physical/chemical deposition techniques such as molecular beam epitaxy (MBE), chemical vapour deposition (CVD) etc. The idea lies on realising solid phase crystallization as a result of annealing at suitable temperatures. The structures produced by these techniques, by very nature, restrict their integration with the present silicon technology. Reference may be made to " Ordering and self-organization of nanocrystallinc silicon" by G.F. Grom, D.J. Lockvvood, J.P. McCafferey, H.J. Labbc, P.M. Fauchet, D. White Jr, J. Dicncr, D. Kovaley, F. Koch and I Tsybeskoy published in Nature, Vol. 407, pages 358 - 361 (2000) wherein nano silicon structures, encapsulated by insulating SiOa, with a control over their size and crystallographic orientation have been reported. The technique is based on using nanocrystallinc (nc) Si/SiO2 superlattices prepared by r-f sputtering and plasma oxidation followed by subsequent annealing. The work, particularly demonstrate the self organization of the embedded nanometer thick a-Si layer between SiO2 layers during solid phase crystallization. Indian patent refer as should be also mention The drawbacks are that the work is limited to the Si/SiO2 system and the conventional approach of physical deposition of the entire sample has been used. Hence, the method of realizing the nanostructures is extrinsic in nature. No results have been presented demonstrating electrical/electronic properties of the nanostructure. Sharpness of the interface has been claimed but no supporting result in the form of scanning tunnelling microscopy/atomic force microscopy (STM/AFM) etc. have been presented. Methodology for a possible device structures or incorporating into a possible device structure seems remote. Hence, the work can be termed as an effort to create isolated silicon nanostructures. Reference may be made to "Optical gain in silicon nanocrystals" by L. Pavesi, L. Dal Negro, C. Mazzoleni, G. Franzo and F. Priolo, published in Nature, Vol. 408, pages 440-444 (2000) where silicon nanocrystals have been produced by traditional incorporation of silicon atoms (ion implantation) inside a SiO2 matrix followed by high temperature thermal annealing so as to form nanocrystals of size 3 nm at a depth of 110 nm from the sample surface extending for a thickness of 100 nm. The drawbacks are that (1) the technique employed for the nanocrystal formation is extrinsic in nature where silicon atoms have been incorporated from outside and annealed to form the crystals in SiO2 environment therefore limiting its usage to the Si/SiO2 systems only; (2) The fabrication is limited to forming a sequence of dots only, which has inherent restrictions in forming a basic electronic device. The main object of the present invention is to provide a novel process for manufacturing silicon nanostructures in single crystalline silicon and silicon nanostructures made thereby useful for making electronic devices, which obviates the drawbacks as detailed above. Another object of the process of the present invention is to provide a process based on nonlinear MeV ion energy dissipation for realizing silicon nanostructures in single crystalline silicon. Yet another object of the process of the present novel process of the invention is to generate localized energy packets through the electronic energy loss mechanism, in selective regions of the crystalline silicon, by employing high energy ion irradiation. Still another object of the process of the present invention is to realize silicon nanostructures in crystalline silicon at predetermined locations employing localized energy packets. In the present invention a novel process based on nonlinear MeV ion energy dissipation for realizing silicon Nan structures in single crystalline silicon, comprises of making nanometer sized structures of silicon embedded in the silicon single crystalline material by the way of controlled irradiation of the said single crystalline silicon material, employing a suitable ion, accelerated to 75 million electron Volts (MeV) and above so as to release their energy by the way of electronic excitation only and make such structures at predetermined locations within the body of the single crystal in a way that it provides a modified silicon lattice consisting of man structures of silicon atoms contiguous with the original silicon periodic lattice through a sharp atomic interface, and whose size can be modified by way of altering beam parameters only such as ion energy, ion energy loss and ion flux, having modified electronic properties in these regions in the way of altered band graps, consistent with clusters of compressed silicon atoms skirted on both sides by the original silicon lattice, whose structure is such that they can be employed in traditional silicon devices. In the present invention, localized energy packets have been utilized for selective reordering the crystalline silicon so as to realize Nan structures with sharp interfaces and modified electronic properties. The device grade silicon Nan structures that have been realized in crystalline silicon by the novel process of the present invention are suitable for making electronic devices. Accordingly the present invention provides a novel process for manufacturing silicon nonstructural in single crystalline silicon useful for making electronic devices which comprises placing a conducting mesh mask above a single crystalline semiconductor substrate in such a manner so as to extend mesh shadow on the said substrate, irradiating the said mesh mask with an ion beam of energy of at least 75 MeV to provide ion flux in the range of 5 x 108 - 5 x 109 ions. Com-2 sec-1 in the said "substrate to obtain semiconductor man structure in single crystalline semiconductor substrate. In an embodiment of the present invention the mesh mask wire cross-section is in the range of 1600 um2-2500um2 and packing in the range of 30-90 wires per inch. In another embodiment of the present invention the mesh mask is made of wires having cross -section such as round, square, rectangular and polygonal. In yet another embodiment of the present invention the ratio of open: block portion o the mesh is in the range of 20:1 - 1:1. In yet another embodiment of the present invention the conducting mesh mask used is of materials such as Ni, Fe, Cu, Ag and Au. In yet another embodiment of the present invention the ion beam energy is in the range of 75-250 MeV. In still another embodiment of the present invention the ion beam used is a parallel beam. Accordingly the present invention provides silicon nanostructures made by the novel process of the present invention as detailed above. Ion irradiation of silicon is carried out employing ions with X+ charge state. This enables ions to be accelerated to an energy E as given by the following equation : where X is the charge of the ion and V is the terminal potential. The charge state of X+ is achieved by first accelerating a negatively charged species of the same ion to a positive terminal potential V. It is then stripped with a foil stripper made of carbon or gold where additional electrons are stripped to give a positively charged ion. These ions impart energy to the silicon crystal through a special arrangement of a metallic Ni wire mesh having square cross-section. The metallic wire mesh is fixed on a circular opening made of stainless steel, 0.5 mm thick, which masks the ion beam to irradiate a desired area of the sample. The ions impinge on the sample perpendicularly from the top and pass through an alumina sheet, primarily meant for visual inspection of the sample location, followed by a grid to suppress secondary electrons. The sample is held below this arrangement, fixed to a heavy copper sample holder but electrically insulated from it with sapphire or mica substrates. The Ni wire mesh, held onto the mask, consists of nickel wires having 40um square cross-section with a packing of 30 wires per inch which allows us to have regions transparent to the ions measuring 850µm x 850 µrn, placed next to regions of width 40 urn opaque to the ions. In order to characterize the samples, these are annealed at 1 1 50 K and STM pictures are revealed in air after etching the surface with an ctchant having the composition comprising of 1 part of HF and 19 parts of HNO3. In order to analyze the inicrfacc by STM/STS, the samples are given a Dash ctchant treatment, which comprises of HF:HNO3:CH3COOH in the ratio of 1:3:5 respectively for 1-2 minutes, to delineate the pattern on the sample surface. This helps to probe the desired location on the sample. In the novel process of the present invention a single crystalline lattice, in the presence of sufficient anisotropy, can support intrinsic localized modes (ILM) which has the possibility of transporting a large amount of energy through breather-like localized excitations. These arise from the concept of solitary waves, first discovered in water, and arise due to excitation of many-body processes. Though established in a continuous media, solilons in a discrete lattice, also called lattice solitons or breathers, have been proposed and shown as waves travelling without dispersion along quasi one-dimensional chains. These waves comprise several lattice atoms, compacted, and hence store and carry substantial energy. The special property of these objects, carrying energy and momentum, arise from the process that produces them. Physically, an impulsive force, capable of producing non-linear interatomic interactions, when suitably balanced by natural dispersion in a lattice, yields a travelling wave of compacted atoms, which proceeds without dispersion. The MeV ions are known to impart an impulsive force whose effect on the lattice depends on the microscopic properties of the system accepting the ion energy. The following picture emerges at this point. The McV ions force the lattice atoms to transfer energy from the irradiation site, outwards, while maintaining lattice order to a large extent. The irradiation interface, created in this experiment terminates these energy transfer mechanisms at the boundary, as conditions favourable to support many-body non-linear processes are no longer available. These show up like structures whose energy of formation is supplied by the MeV ions. The atoms of the periodic Si lattice act as pathways leading to energy transfer. Deposition of this energy results in artificial creation of silicon nanostructurcs, shaped like tips, with almost atomic level packing densities. This technique of transfer of energy leading to nanostructure formation has not been employed before. The novelty and inventive step of the process of the patent invention resides in making silicon nanostructures contiguous with single crystalline silicon in one single step. The following examples are given by way of illustration of the novel process of the present invention and therefore should not be construed to limit the scope of the present invention. EXAMPLE - 1 The sample of Si(lOO) was mounted on the sample holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen as silver (Ag) with 14+ charge state and energy of 200 MeV. This gives a range of 25 microns in Si(l00) so as to make it compatible with the silicon technology. The sample was irradiated to a fluence of 5 x 1011 ions cm"2. Ion flux was maintained at 5 x 108 ions scc-1cm -2. The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichloroethylcne, acetone and mcthanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior HF dip for the removal of native oxide traces. The scanned images were recorded using line plots. Figure 1 represents STM plot of the Si(100) surface irradiated by 200 MeV Ag ions, taken prior to annealing the sample. A part of the plot on the left is enhanced to show the 6-fold symmetry of the single crystalline Si surface, reconstructed, which is a minor distortion of the fee Si(100). The irradiation takes place in the single crystalline part of the sample on the left, and the irradiation front proceeds from the left to reach the irradiation interface. EXAMPLE -2 The sample of Si(100) was mounted on the sample: holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen as silver (Ag) with 14+ charge state and energy of 200 MeV. This gives a range of 25 microns in Si(100) so as to make it compatible with the silicon technology. The sample was irradiated to a flucncc of 5 x 1011 ions cm~2. Ion flux was maintained at 5 x 108 ions sec-1cm -2. The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichloroethylene, acetone and methanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior (IF dip for the removal of native oxide traces. The scanned images were recorded using line plots. The sample was annealed at 1150 K in air for two hours. After HF dip the sample was scanned for STM image' The sharp interface image was photographed. Figure 2 represents the STM scan of the 200 MeV Ag ion irradiated Si(100) surface. The irradiation front from the left, aided by temperature, proceeds to form an atomically sharp interface as seen in the STM plot. The irradiation region on the left maintains the 6-fold symmetry of the reconstructed single crystalline silicon. EXAMPLE -3 The sample of Si(100) was mounted on the sample holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen as silver (Ag) with 14+ charge state and energy of 200 MeV. This gives a range of 25 microns in Si(100) so as to make it compatible with the silicon technology. The sample was irradiated to a fluencc of 5 x K)" ions cm"2. Ion flux was maintained at 5 x 10 ions sec-1cm -2 . The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichloroethylene, acetone and methanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior MF dip for the removal of native oxide traces. The scanned images were recorded using line plots. The sample was annealed at 1150 K in air for two hours. After HF dip the sample was scanned to achieve scanning tunneling spectroscopy (STS) for electrical characterisation. Figure 3 represents scanning tunneling spectroscopy (STS) of the Si(100) sample from various regions near the irradiation interface. The band gap of the regions under scrutiny can be obtained by measuring the voltage difference for which the tunnelling current 1-0 so as to give EC-EV. Fig. 3a shows the spectroscopy of the single crystalline Si(100) lattice with 6-fold symmetry. The band gap obtained as mentioned above is 1.14 eV which is close to the reported band gap of pure single crystalline silicon. Fig. 3b shows the spectroscopy of the nanostructurcd silicon lattice. The band gap for the nanostructured silicon lattice, obtained following the method as mentioned above, is 0.4 eV, showing modified band gap and hence electronic property of the nanostructured silicon lattice. EXAMPLE - 4 The sample of Si(100) was mounted on the sample holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen to be oxygen (O) with 7+ charge and energy of 100 MeV. This gives a range of 100 microns in Si(100) so as to make it compatible with the silicon technology. The sample was irradiated to a fluence of 5x 1011 ft O I •) ions cm" . Ion flux was maintained at 5x108 ions scc-1 cm-2 . The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichlorocthylcne, acetone and methanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior 1 IF dip for the removal of native oxide traces. The scanned images were recorded using line plots and photography. The main advantages of the novel process of the present invention are : 1. Ultra pure nanostructures of silicon are realized. 2. Allows the fabrication of nanostructures in silicon showing modified electronic and electrical properties: 3. In case of elemental semiconductors, the technique has potentials for devising innovative structures with improved optical properties. Claim: 1. A novel process for manufacturing silicon nonostructures in single crystalline silicon useful for making electronic devices which comprises placing a conducting mesh mask above a single crystalline semiconductor substrate so as to extend mesh shadow on the said substrate, irradiating the said mesh mask with an ion beam of energy of at least 75 MeV to provide ion flux in the range of 5 x 108 - 5 x 109 ions.cm-2 sec-1 in the said substrate to obtain semiconductor nonostructure in single crystalline semiconductor substrate. 2. The novel process as claimed in Claim 1 wherein the mesh mask wire cross-section is in the range of 1600 µm2 - 2500µm2 and packing in the range of 30-90 wires per inch. 3. The novel process as claimed in Claim 1-2 wherein the mesh mask is made of wires having cross-section such as round, square, rectangular and polygonal. 4. A novel process as claimed in claim 1-3 wherein the ratio of open: block portion of the mesh is in the range of 20:1 - 1:1, 5. A novel process as claimed in Claim 1-4 wherein the conducting mesh mask used is of materials such as Ni, Fe, Cu, Ag and Au. 6. A novel process as claimed in Claim 1-5 wherein the ion beam energy is in the range of 75-250 MeV. 7. A novel process as claimed in Claim 1-6 wherein the ion beam used is a parallel beam. 8. Silicon Nan structures in single crystalline silicon useful for making electronic devices made by the novel process as claimed in Claim 1-7. 9. A novel process for manufacturing silicon Nan structures in single crystalline silicon substantially as herein described with reference to examples and drawings accompanying this specification. 10. Silicon nonstructural in single crystalline silicon useful for making electronic devices substantially as herein described with reference to the examples and drawings.

Full Text

The present invention particularly relates lo a novel process for manufacturing silicon nanostructures in single crystalline silicon and silicon nanostructurcs made thereby useful for making electronic devices
The invention provides a technology for fabrication of silicon nanostructures in crystalline silicon, at predetermined locations, by employing million electron Volt (MeV) ion irradiation. The energy supplied by the McV ions arc trapped at prescribed locations (irradiation interfaces) in a crystalline solid such that the size of the nanostructures depends upon the beam parameters and do not require any extraneous methods based on pattern delineation, employing masks. And therefore, the technique is suitable for the development of mask-less nano fabrication. The technique is intrinsic in nature and therefore leads to produce pure Si nanostructurcs in a single crystalline Si lattice.
Nanostructures provide tunable electronic properties, based on their size, which is markedly different than bulk materials. Therefore their potential is well recognized for enhancing the capabilities of electronic devices, which can be fabricated employing nanostructures. For example, increased photoluminesccncc, reduced band gaps and atom-like electronic states would provide increased switching speed, low power consumption, and possibility for integrated opto-elcctro-mechanical devices.
Fabrication of nanostructures in silicon have been reported in technical literature, using physical/chemical deposition techniques such as molecular beam epitaxy (MBE), chemical vapour deposition (CVD) etc. The idea lies on realising solid phase crystallization as a result of annealing at suitable temperatures. The structures
produced by these techniques, by very nature, restrict their integration with the present silicon technology.
Reference may be made to " Ordering and self-organization of nanocrystallinc silicon" by G.F. Grom, D.J. Lockvvood, J.P. McCafferey, H.J. Labbc, P.M. Fauchet, D. White Jr, J. Dicncr, D. Kovaley, F. Koch and I Tsybeskoy published in Nature, Vol. 407, pages 358 - 361 (2000) wherein nano silicon structures, encapsulated by
insulating SiOa, with a control over their size and crystallographic orientation have
been reported. The technique is based on using nanocrystallinc (nc) Si/SiO2
superlattices prepared by r-f sputtering and plasma oxidation followed by subsequent annealing. The work, particularly demonstrate the self organization of the embedded
nanometer thick a-Si layer between SiO2 layers during solid phase crystallization.
Indian patent refer as should be also mention
The drawbacks are that the work is limited to the Si/SiO2 system and the conventional
approach of physical deposition of the entire sample has been used. Hence, the
method of realizing the nanostructures is extrinsic in nature. No results have been
presented demonstrating electrical/electronic properties of the nanostructure.
Sharpness of the interface has been claimed but no supporting result in the form of
scanning tunnelling microscopy/atomic force microscopy (STM/AFM) etc. have been
presented. Methodology for a possible device structures or incorporating into a
possible device structure seems remote. Hence, the work can be termed as an effort to create isolated silicon nanostructures.
Reference may be made to "Optical gain in silicon nanocrystals" by L. Pavesi, L. Dal Negro, C. Mazzoleni, G. Franzo and F. Priolo, published in Nature, Vol. 408, pages 440-444 (2000) where silicon nanocrystals have been produced by traditional
incorporation of silicon atoms (ion implantation) inside a SiO2 matrix followed by high temperature thermal annealing so as to form nanocrystals of size 3 nm at a depth of 110 nm from the sample surface extending for a thickness of 100 nm.
The drawbacks are that (1) the technique employed for the nanocrystal formation is extrinsic in nature where silicon atoms have been incorporated from outside and annealed to form the crystals in SiO2 environment therefore limiting its usage to the Si/SiO2 systems only; (2) The fabrication is limited to forming a sequence of dots only, which has inherent restrictions in forming a basic electronic device.
The main object of the present invention is to provide a novel process for manufacturing silicon nanostructures in single crystalline silicon and silicon nanostructures made thereby useful for making electronic devices, which obviates the drawbacks as detailed above.
Another object of the process of the present invention is to provide a process based on nonlinear MeV ion energy dissipation for realizing silicon nanostructures in single crystalline silicon.
Yet another object of the process of the present novel process of the invention is to generate localized energy packets through the electronic energy loss mechanism, in selective regions of the crystalline silicon, by employing high energy ion irradiation. Still another object of the process of the present invention is to realize silicon nanostructures in crystalline silicon at predetermined locations employing localized energy packets.
In the present invention a novel process based on nonlinear MeV ion energy dissipation for realizing silicon Nan structures in single crystalline silicon, comprises of making nanometer sized structures of silicon embedded in the silicon single crystalline material by the way of controlled irradiation of the said single crystalline silicon material, employing a suitable ion, accelerated to 75 million electron Volts (MeV) and above so as to release their energy by the way of electronic excitation only and make such structures at predetermined locations within the body of the single crystal in a way that it provides a modified silicon lattice consisting of man structures of silicon atoms contiguous with the original silicon periodic lattice through a sharp atomic interface, and whose size can be modified by way of altering beam parameters only such as ion energy, ion energy loss and ion flux, having modified electronic properties in these regions in the way of altered band graps, consistent with clusters of compressed silicon atoms skirted on both sides by the original silicon lattice, whose structure is such that they can be employed in traditional silicon devices.
In the present invention, localized energy packets have been utilized for selective reordering the crystalline silicon so as to realize Nan structures with sharp interfaces and modified electronic properties.
The device grade silicon Nan structures that have been realized in crystalline silicon by the novel process of the present invention are suitable for making electronic devices.
Accordingly the present invention provides a novel process for manufacturing silicon nonstructural in single crystalline silicon useful for making electronic devices which comprises placing a conducting mesh mask above a single crystalline semiconductor substrate in such a manner so as to extend mesh shadow on the said substrate, irradiating the said mesh mask with an ion beam of energy of at least 75 MeV to provide ion flux in the range of 5 x 108 - 5 x 109 ions. Com-2 sec-1 in the said
"substrate to obtain semiconductor man structure in single crystalline semiconductor substrate.
In an embodiment of the present invention the mesh mask wire cross-section is in the range of 1600 um2-2500um2 and packing in the range of 30-90 wires per inch.
In another embodiment of the present invention the mesh mask is made of wires having cross -section such as round, square, rectangular and polygonal.
In yet another embodiment of the present invention the ratio of open: block portion o the mesh is in the range of 20:1 - 1:1.
In yet another embodiment of the present invention the conducting mesh mask used is of materials such as Ni, Fe, Cu, Ag and Au.
In yet another embodiment of the present invention the ion beam energy is in the range of 75-250 MeV.
In still another embodiment of the present invention the ion beam used is a parallel beam.
Accordingly the present invention provides silicon nanostructures made by the novel process of the present invention as detailed above.
Ion irradiation of silicon is carried out employing ions with X+ charge state. This enables ions to be accelerated to an energy E as given by the following equation :
where X is the charge of the ion and V is the terminal potential. The charge state of X+ is achieved by first accelerating a negatively charged species of the same ion to a positive terminal potential V. It is then stripped with a foil stripper made of carbon or gold where additional electrons are stripped to give a positively charged ion.
These ions impart energy to the silicon crystal through a special arrangement of a metallic Ni wire mesh having square cross-section. The metallic wire mesh is fixed on a circular opening made of stainless steel, 0.5 mm thick, which masks the ion beam to irradiate a desired area of the sample. The ions impinge on the sample perpendicularly from the top and pass through an alumina sheet, primarily meant for visual inspection of the sample location, followed by a grid to suppress secondary electrons. The sample is held below this arrangement, fixed to a heavy copper sample holder but electrically insulated from it with sapphire or mica substrates.
The Ni wire mesh, held onto the mask, consists of nickel wires having 40um square cross-section with a packing of 30 wires per inch which allows us to have regions transparent to the ions measuring 850µm x 850 µrn, placed next to regions of width 40 urn opaque to the ions.
In order to characterize the samples, these are annealed at 1 1 50 K and STM pictures
are revealed in air after etching the surface with an ctchant having the composition comprising of 1 part of HF and 19 parts of HNO3.
In order to analyze the inicrfacc by STM/STS, the samples are given a Dash ctchant treatment, which comprises of HF:HNO3:CH3COOH in the ratio of 1:3:5 respectively for 1-2 minutes, to delineate the pattern on the sample surface. This helps to probe the desired location on the sample.
In the novel process of the present invention a single crystalline lattice, in the presence of sufficient anisotropy, can support intrinsic localized modes (ILM) which has the possibility of transporting a large amount of energy through breather-like localized excitations. These arise from the concept of solitary waves, first discovered in water, and arise due to excitation of many-body processes.
Though established in a continuous media, solilons in a discrete lattice, also called lattice solitons or breathers, have been proposed and shown as waves travelling without dispersion along quasi one-dimensional chains. These waves comprise several lattice atoms, compacted, and hence store and carry substantial energy. The special property of these objects, carrying energy and momentum, arise from the process that produces them. Physically, an impulsive force, capable of producing non-linear interatomic interactions, when suitably balanced by natural dispersion in a lattice, yields a travelling wave of compacted atoms, which proceeds without dispersion. The MeV ions are known to impart an impulsive force whose effect on the lattice depends on the microscopic properties of the system accepting the ion energy.
The following picture emerges at this point. The McV ions force the lattice atoms to transfer energy from the irradiation site, outwards, while maintaining lattice order to a large extent. The irradiation interface, created in this experiment terminates these energy transfer mechanisms at the boundary, as conditions favourable to support many-body non-linear processes are no longer available. These show up like structures whose energy of formation is supplied by the MeV ions. The atoms of the
periodic Si lattice act as pathways leading to energy transfer. Deposition of this energy results in artificial creation of silicon nanostructurcs, shaped like tips, with almost atomic level packing densities. This technique of transfer of energy leading to nanostructure formation has not been employed before.
The novelty and inventive step of the process of the patent invention resides in making silicon nanostructures contiguous with single crystalline silicon in one single step.
The following examples are given by way of illustration of the novel process of the present invention and therefore should not be construed to limit the scope of the present invention.
EXAMPLE - 1
The sample of Si(lOO) was mounted on the sample holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen as silver (Ag) with 14+ charge state and energy of 200 MeV. This gives a range of 25 microns in Si(l00) so as to make it compatible with the silicon technology. The sample was irradiated to a fluence of 5 x 1011 ions cm"2. Ion flux was maintained at 5 x 108 ions scc-1cm -2. The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichloroethylcne, acetone and mcthanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior HF dip for the removal of native oxide traces. The scanned images were recorded using line plots. Figure 1 represents

STM plot of the Si(100) surface irradiated by 200 MeV Ag ions, taken prior to annealing the sample. A part of the plot on the left is enhanced to show the 6-fold symmetry of the single crystalline Si surface, reconstructed, which is a minor distortion of the fee Si(100). The irradiation takes place in the single crystalline part of the sample on the left, and the irradiation front proceeds from the left to reach the irradiation interface.
EXAMPLE -2
The sample of Si(100) was mounted on the sample: holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen as silver (Ag) with 14+ charge state and energy of 200 MeV. This gives a range of 25 microns in Si(100) so as to make it compatible with the silicon technology. The sample was irradiated to a flucncc of 5 x 1011 ions cm~2. Ion flux was maintained at 5 x 108 ions sec-1cm -2. The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichloroethylene, acetone and methanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior (IF dip for the removal of native oxide traces. The scanned images were recorded using line plots. The sample was annealed at 1150 K in air for two hours. After HF dip the sample was scanned for STM image' The sharp interface image was photographed. Figure 2 represents the
STM scan of the 200 MeV Ag ion irradiated Si(100) surface. The irradiation front from the left, aided by temperature, proceeds to form an atomically sharp interface as
seen in the STM plot. The irradiation region on the left maintains the 6-fold symmetry of the reconstructed single crystalline silicon.
EXAMPLE -3
The sample of Si(100) was mounted on the sample holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen as silver (Ag) with 14+ charge state and energy of 200 MeV. This gives a range of 25 microns in Si(100) so as to make it compatible with the silicon technology. The sample was irradiated to a fluencc of 5 x K)" ions cm"2. Ion flux was maintained at 5 x 10 ions sec-1cm -2 . The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichloroethylene, acetone and methanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior MF dip for the removal of native oxide traces. The scanned images were recorded using line plots. The sample was annealed at 1150 K in air for two hours. After HF dip the sample was scanned to achieve scanning tunneling spectroscopy (STS) for electrical characterisation. Figure 3 represents scanning tunneling spectroscopy (STS) of the Si(100) sample from various regions near the irradiation interface. The band gap of the regions under scrutiny can be obtained by measuring the voltage difference for which the tunnelling current 1-0 so as to give EC-EV. Fig. 3a shows the spectroscopy of the single crystalline Si(100) lattice with 6-fold symmetry. The band gap obtained as mentioned above is 1.14 eV which is close to the reported band gap of pure single crystalline silicon. Fig. 3b shows the spectroscopy of the nanostructurcd silicon lattice. The band
gap for the nanostructured silicon lattice, obtained following the method as mentioned above, is 0.4 eV, showing modified band gap and hence electronic property of the nanostructured silicon lattice.
EXAMPLE - 4
The sample of Si(100) was mounted on the sample holder and Ni wire mesh was fixed on the stainless steel mask so as to have the complete assembly in a compact form. The irradiation ion specie was chosen to be oxygen (O) with 7+ charge and energy of 100 MeV. This gives a range of 100 microns in Si(100) so as to make it compatible with the silicon technology. The sample was irradiated to a fluence of 5x 1011
ft O I •)
ions cm" . Ion flux was maintained at 5x108 ions scc-1 cm-2 . The ion beam was expanded to have a 7 mm circular shape so that the entire 5mm circular opening is irradiated uniformly. After irradiation, the sample was thoroughly cleaned using trichlorocthylcne, acetone and methanol followed by rinsing in D.I. water. Dash etchant treatment was given for 2 minutes in order to delineate the pattern on the sample. STM scanning was done in air with prior 1 IF dip for the removal of native oxide traces. The scanned images were recorded using line plots and photography.
The main advantages of the novel process of the present invention are :
1. Ultra pure nanostructures of silicon are realized.
2. Allows the fabrication of nanostructures in silicon showing modified electronic
and electrical properties:
3. In case of elemental semiconductors, the technique has potentials for devising
innovative structures with improved optical properties.

Claim:
1. A novel process for manufacturing silicon nonostructures in single crystalline silicon useful for
making electronic devices which comprises placing a conducting mesh mask above a single
crystalline semiconductor substrate so as to extend mesh shadow on the said substrate,
irradiating the said mesh mask with an ion beam of energy of at least 75 MeV to provide ion
flux in the range of 5 x 108 - 5 x 109 ions.cm-2 sec-1 in the said substrate to obtain
semiconductor nonostructure in single crystalline semiconductor substrate.
2. The novel process as claimed in Claim 1 wherein the mesh mask wire cross-section is in the
range of 1600 µm2 - 2500µm2 and packing in the range of 30-90 wires per inch.
3. The novel process as claimed in Claim 1-2 wherein the mesh mask is made of wires having
cross-section such as round, square, rectangular and polygonal.
4. A novel process as claimed in claim 1-3 wherein the ratio of open: block portion of the mesh is
in the range of 20:1 - 1:1,
5. A novel process as claimed in Claim 1-4 wherein the conducting mesh mask used is of
materials such as Ni, Fe, Cu, Ag and Au.
6. A novel process as claimed in Claim 1-5 wherein the ion beam energy is in the range of 75-250
MeV.
7. A novel process as claimed in Claim 1-6 wherein the ion beam used is a parallel beam.
8. Silicon Nan structures in single crystalline silicon useful for making electronic devices made by
the novel process as claimed in Claim 1-7.
9. A novel process for manufacturing silicon Nan structures in single crystalline silicon
substantially as herein described with reference to examples and drawings accompanying this
specification.
10. Silicon nonstructural in single crystalline silicon useful for making electronic devices
substantially as herein described with reference to the examples and drawings.

Documents:

326-del-2001-abstract.pdf

326-del-2001-claims.pdf

326-del-2001-correspondence-others.pdf

326-del-2001-correspondence-po.pdf

326-del-2001-description (complete).pdf

326-del-2001-drawings.pdf

326-del-2001-form-1.pdf

326-del-2001-form-18.pdf

326-del-2001-form-2.pdf

326-del-2001-form-3.pdf

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Patent Number

231612

Indian Patent Application Number

326/DEL/2001

PG Journal Number

13/2009

Publication Date

27-Mar-2009

Grant Date

06-Mar-2009

Date of Filing

23-Mar-2001

Name of Patentee

COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH

Applicant Address

RAFI MARG, NEW DELHI-110001, INDIA.

Inventors:

#	Inventor's Name	Inventor's Address
1	JAMIL AKHTAR	SEMICONDUCTOR DEVICES AREA, CENTRAL ELECTRONIC ENGINEERING, RESEARCH INSTITUTE, PILANI-333031, INDIA.
2	PRASENJIT SEN	SCHOOL OF PHYSICAL SCIENCES, JAWAHARLAL NEHRU UNIVERSITY, NEW DELHI-110067, INDIA.

PCT International Classification Number

H01L 21/265

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA