Title of Invention

"A DIRECT SEQUENCE SPREAD SPECTRUM TRANSCEIVER FOR WIRELESS PACKET DATA"

Abstract This invention relates to a Direct Sequence Spread Spectrum Transceiver for wireless packet data, using bootstrapped direct sequence wherein the said transceiver comprises a transmitter (14), a receiver (15), a data and control bus (16) and its controller for interfacing with the host machine, transmit radio circuitry connected to said transmitter at (3) for air interface, receiver radio circuits being connected to the said receiver (14) at (6), (8) and (10), and wherein the said transmitter (14) consists of a spreader (17), a direct sequence generator (18) and shift register (19) connected together and the said receiver (15) consists of a direct sequence generator (20), shift register (21), associative memory (22) connected together and wherein further the said direct sequence generator (18) comprises of feedback sequence generator register (23), a modulo two adder (22), register (24) with its bits ((T1,....TK, TM- 1 TM) connected to feedback positions ((Y1,....YK, YK+I YM) of said direct sequence generator (18) each bit YK being connected to XOR of bit YK+I and to the output of a two input AND gate, register (24) specifying the feedback tap position, register (25) providing masking bit input to the AND gates at the input of said modulo two adder (22), registers (26 to 32) capable of being loaded through port (13) with register (26) for intimating the label in the preamble to the bootstrapped DS generator, Register (27) and (30) being for updating the sequence generator register (23), registers(28) and (31) for updating the feedback tap register (24), and register (33) being a 2-bit mode register addressed and set through port (13).
Full Text FIELD OF INVENTION
This invention relates to a direct sequence spread spectrum transceiver for wireless packet data application wherein the transceiver uses a bootstrapped direct sequence.
PRIOR ART
Direct sequence spread spectrum (DSSS) can partition the wireless medium into several channels by using a different spreading sequence for each channel. This is termed as Spread Spectrum Multiple Access (SSMA) or Code Division Multiple Access (CDMA). SSMA receiver require a despreading code to be assigned to a receiver and receiver code to be synchronises to the one in the received signal.
In the known art, a SSMA receiver is assigned to despread either a fixed channel or a channel chosen by another protocol.
According to one of the technology known in the art, IEEE 802.lib Direct Sequence Spread Spectrum (DSSS) standard uses a single 11-chip Barker sequence for spreading but does not exercise its multiple access capability.
A limitation of the above is that though the short length (llchips) of the Barker sequence helps in fast synchronization but the auto-correlation function peak is only 11 and the period is 11 chips.
Another limitation of the above is that even though upto 11 separate channels can be supported, the above standard avoids the multiple access option completely.
Still another limitation of the above is that performance of IEEE 802.1 Ib LAN degrades when the number of transmitters increases even though communication may be between different pairs of users. The interference between the pairs of users is less when multiple access capability is used.
In another technology, C-200 VSAT network by Equatorial communication is used which has a separate receiver tuned to each spreading code.
A drawback of the above network is that as the number of spreading code increases, installing and maintaining the separate receivers "becomes impractical.
Another technology ALOHA Multiple Access uses a common code with a spreading gain of 31, similar to IEEE 802.11, for the multiple access of a wireless channel. But unlike IEEE 802.11, the different users are separated by a random timing mechanism.
A limitation of the above is that for deciding which user a packet has to be given, it has to be processed at a higher level of 2 or 3, looking at the contents of packet holder. At the air interface level 1, all the packets are with common spreading code and though they may not interfere with each other, it is not possible to determine to which users they are meant for at that level.
CDMA 2000 high rate packet data air interface uses CDMA for the reverse traffic from the access terminal to the access network. It uses two 42 bit long code marks to create a pseudo noise sequence to spread the reverse traffic data channel. These marks are derived from the Access Terminal Identifier (ATI) of the Access Terminal. Each Access Terminal is assigned a unique ATI by the Access Network in a connection set up protocol. Thus cdma2000 assigns the despreading code to a receiver by another protocol ahead of the packet data transfer protocol.
OBJECTS OF THE PRESENT INVENTION
An object of the present invention is to provide a direct sequence spread spectrum transceiver that uses Boot strapped Direct Sequence.
STATEMENT OF INVENTION
According to this invention there is provided A Direct Sequence Spread Spectrum Transceiver for wireless packet data, using bootstrapped direct
sequence wherein the said transceiver comprises a transmitter, a receiver, a data and control bus and its controller for interfacing with the host machine, transmit radio circuitry connected to said transmitter at for air interface, receiver radio circuits being connected to the said receiver at and wherein the said transmitter consists of a spreader, a direct sequence generator and shift register connected together and the said receiver consists of a direct sequence generator, shift register, associative memory connected together and wherein further the said direct sequence generator comprises of feedback sequence generator register, a modulo two adder, register with its bits
((T1, TK, TM-I TM,) connected to feedback positions
((Y1, YK, YK+1, YM) of said direct sequence generator, each bit YK
being connected to XOR of bit YK+1 and to the output of a two input AND gate, register specifying the feedback tap position, register providing masking bit input to the AND gates at the input of said modulo two adders, registers to 32) capable of being loaded through port with register for intimating the label in the preamble to the bootstrapped DS generator, Register and being for updating the sequence generator
register, registers and for updating the feedback tap register, and register beins a 2- bit mode register addressed and set through port.
DESCRIPTION OF FIGURES
The invention will now be illustrated with drawings, which is an illustrative embodiment of the present invention and is not intended to be taken restrictively to imply any limitation on the scope of the present invention. In the figures, a thin solid line indicated a path for a data bit stream, a dashed line indicates a control path consisting of one or more signal lines and a thick solid line indicates a path for a data vector of several bits. In the accompany drawings: -
Fig. 1: shows the construction of bootstrapped direct sequence
transceiver;
Fig.2: shows the Direct sequence generator used in the bootstrapped
direct sequence transceiver;
DESCRIPTION OF INVENTION w.r.t. DRAWINGS
Referring to fig. 1, the Direct Sequence spread spectrum transceiver of the present invention uses bootstrapped direct sequence and consists of a transmitter (14) and one or more receivers (15). A data and control bus (16) and its controller interface with the host machine. Transmit radio circuits for the air interface are connected to the said transmitter (14) at (3). Receiver radio circuits are connected to the said receiver (14) at (6), (8), (10). The bus and the radio circuits are built according to the known art. The said transmitter (14) consists of a simple spreader (17), a direct sequence generator (18), and a shift register (19). These components are connected as shown in fig.l. the said receiver (15) consists of a direct sequence generator (20), shift register (21) and associative memory (22), all connected together as shown in fig. 1.
Referring to fig.2, the said bootstrapped DS generator (18) has the main components as feedback sequence generator register (23) and a modulo two adder (22). All the registers are m bits long. The modulo two adder
also adds bits. Register (24) bits (Ti, TK, TM-i TM) are
connected to the AND gates at the feedback positions (Yi YK,
YK+1, Ym) of the said sequence generator (23). Register (24) specifies
the feedback tap position. Each bit YK is connected to the XOR of bit YK+I and the output of a two input AND gate. Each such AND gate is connected to Y1 as its first input and the K'th bit TK of register (24). Thus the feedback path from YI to YK is gated through an AND gate which ANDs it with TK and an XOR gate that XORs the output of the AND with
YK+I. Register (25) with bits (B1, B2 BK, BK+1 BM) is the
register providing the masking bit input to the AND gates at the input of the said modulo two adder (22). The Kth input to the said adder (22) is connected to the output of an AND gate. The first input of this AND gate is the Kth bit BK of B and the second input is YK. Registers (26 to 32) are m-bit registers that can be addressed and loaded through a port (13). Register (26) is for intimating the label in the preamble to the bootstrapped DS generator. The register (27) and (30) are for updating the sequence generator register (23) in the preamble phase and their non-preamble phase respectively. The registers (28) and (31) are for
pdating the feedback tap register (24) in the preamble phase and non-preamble phase respectively.
Register (33) is a 2-bit mode register addressed and set through port 13. (4) is the reset input to the bootstrapped DS generation.
METHOD OF WORKING
The packet data (1) for transmission is spread using the direct sequence (2) by the spreader (17). The spread transmit data (3) is processed by the radio section and comes out as air waves. The direct sequence (2) is generated by the direct sequence generator (18) later. Initially, on reset on control path (4), direct sequence generator (18) will generate the Preamble Spreading Sequence. The clocking of (18) will start with the first bit of the packet data on (1).
While the packet data (1) is being shifted into the spreader (17), it is shifted in parallel into the register (19). When the channel label in the packet is shifted into (19), it will be presented to (18) on (13). (18) will stop generating the Preamble Spreading Sequence and switch to a spreading sequence dependent on the label. Thus the rest of the packet after the preamble will be spread using the DS generated from the channel Label in the packet.
A Bootstrapped Direct Sequence receiver will always use the Preamble Spreading Sequence to start receiving the packets. After the channel label is received, the receiver will check whether the channel is valid for reception. If it is a valid receive channel, then the rest of the packet will be despread using the DS generated from the label.
The receivers are daisy chained. At any instant, the first free receiver on the daisy chain will be looking for the preamble of a received packet. If it finds a valid preamble, the same receiver will continue to receive the non-preamble of the packet. As soon as a receiver starts receiving the non-preamble, the next free receiver on the daisy chain will take over the function of looking for a new preamble. When a receiver completes taking in the non-preamble, it joins the pool of free receivers. The block diagram of the receiver (15) is shown in Fig.l. the initial function of receiver (15) is to generate and synchronize the Preamble Spreading Sequence with the received radio signal and despread the preamble of the packet. Within receiver (15), register (20) is the Bootstrapped DS generator, reset by signal on (5). The circuit presents the direct sequence (6) to the radio section for use in despreading. The radio section returns indication of receiver code synchronization on signal path (8). Absence of synchronization will be used to slip (20). When the despreading direct sequence (6) aligns with the spreading DS in the received signal, it will be indicated by the signal on (8). When (20) is synchronized, it need not be slipped further. After synchronization, the despread preamnle data (10) from the radio section is shifted to register (21). After all bits of the channel label in the preamble have been shifted into (21), it will be checked with an associative memory (22) which contains the labels of valid receive channels. If the label in (21) is present in (22), it is presented to (20) which will now seamlessly switch to generating the DS from the received label. The radio receiver will use the non-preamble DS presented to it on (6) to despread the non-preable part of the packet. The despread data will be shifted on (10) to the register (21). Using bus X, receiver (15) will transfer the received data in (21) to the host machine. When the packet is received fully, or the radio section signals on (8) that signal strength is low, receiver (20) uploads its (21) to the bus and makes itself free.
It is to be noted that present invention is susceptible to modifications changes and adaptations by those skilled in the art. Such, variant embodiments incorporating the concepts and features of the present invention, are intended to be within the scope of the present invention, which is further set forth under the following claims:




WE CLAIM;
1. A Direct Sequence Spread Spectrum Transceiver for wireless packet data, using bootstrapped direct sequence wherein the said transceiver comprises a transmitter (14), a receiver (15), a data and control bus (16) and its controller for interfacing with the host machine, transmit radio circuitry connected to said transmitter at (3) for air interface, receiver radio circuits being connected to the said receiver (14) at (6), (8) and (10), and wherein the said transmitter (14) consists of a spreader (17), a direct sequence generator (18) and shift register (19) connected together and the said receiver (15) consists of a direct sequence generator (20), shift register (21), associative memory (22) connected together and wherein further the said direct sequence generator (18) comprises of feedback sequence generator register (23), a modulo two adder (22), register (24)
with its bits ((Ti, TK, TM-I TM) connected to
feedback positions ((Yi, YK, YK+I, YM) of said direct
sequence genertor (18), each bit YK being connected to XOR of bit YK+I and to the output of a two input AND gate, register (24) specifying the feedback tap position, register (25) providing masking bit input to the AND gates at the input of said modulo two adder (22), registers (26 to 32) capable of being loaded through port (13) with register (26) for intimating the label in the preamble to the bootstrapped DS generator, Register (27) and (30) being for updating the sequence generator register (23), registers (28) and (31) for updating the feedback tap register (24), and register (33) being a 2- bit mode register addressed and set through port (13).
2. A direct sequence spread spectrum transceiver as substantially described and illustrated herein.

Documents:

1441-DEL-2003-Abstract-10-04-2008.pdf

1441-del-2003-abstract.pdf

1441-DEL-2003-Claims-10-04-2008.pdf

1441-del-2003-claims.pdf

1441-DEL-2003-Correspondence-Others-(13-02-2009).pdf

1441-DEL-2003-Correspondence-Others-10-04-2008.pdf

1441-del-2003-correspondence-others.pdf

1441-del-2003-correspondence-po.pdf

1441-del-2003-description (complete).pdf

1441-DEL-2003-Description (Complete)10-04-2008.pdf

1441-DEL-2003-Drawings-10-04-2008.pdf

1441-del-2003-drawings.pdf

1441-DEL-2003-Form-1-(13-02-2009).pdf

1441-del-2003-form-1.pdf

1441-del-2003-form-18.pdf

1441-del-2003-form-2.pdf

1441-DEL-2003-Form-26-(13-02-2009).pdf

1441-DEL-2003-Form-3-10-04-2008.pdf

1441-DEL-2003-Petition-137-(13-02-2009).pdf


Patent Number 229861
Indian Patent Application Number 1441/DEL/2003
PG Journal Number 10/2009
Publication Date 06-Mar-2009
Grant Date 20-Feb-2009
Date of Filing 20-Nov-2003
Name of Patentee THE SECRETARY, DEPARTMENT OF INFORMATION TECHNOLOGY
Applicant Address MINISTRY OF COMMUNICATIONS & INFORMATION TECHNOLOGY, GOVERNMENT OF INDIA, ELECTRONICS NIKETAN, 6 C.G.O. COMPLEX LODHI ROAD, NEW DELHI-110003
Inventors:
# Inventor's Name Inventor's Address
1 AJIT JOSHI CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING GULMOHAR CROSS ROAD, NO. 9, JUHU, MUMBAI-400049, MAHARASHTRA, INDIA.
2 VINOD KUMAR KOODATHINGAL CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING GULMOHAR CROSS ROAD, NO. 9, JUHU, MUMBAI-400049, MAHARASHTRA, INDIA.
PCT International Classification Number H04B 1/707
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA