Title of Invention	A SYSTEM FOR DIFFERENTIAL CURRENT PROTECTION INCLUDING HARMONIC RESTRAINT AND BLOCKING FOR A POWER TRANSFORMER
Abstract	The invention relates to a system for differential current protection including harmonic restraint and blocking for a power transformer comprising a means for developing a differential current value (16) from processed winding values which are representative of current transformer (CT) secondary current values obtained from the windings of a power transformer means for developing an operating current value (44) from said differential current value; means for developing a restraining current value (62) from said processed winding current values means for obtaining at least one even harmonic value of said differential current value (32). Means for comparing (54) the sume (76) of the restraining current value (62) and the even harmonic values (82) with the operating current value and for producing an output signal (87R1) which in turn emerges as useful in producing a trip signal when the operating current value is larger than said sum.

Title of Invention

A SYSTEM FOR DIFFERENTIAL CURRENT PROTECTION INCLUDING HARMONIC RESTRAINT AND BLOCKING FOR A POWER TRANSFORMER

Abstract

The invention relates to a system for differential current protection including harmonic restraint and blocking for a power transformer comprising a means for developing a differential current value (16) from processed winding values which are representative of current transformer (CT) secondary current values obtained from the windings of a power transformer means for developing an operating current value (44) from said differential current value; means for developing a restraining current value (62) from said processed winding current values means for obtaining at least one even harmonic value of said differential current value (32). Means for comparing (54) the sume (76) of the restraining current value (62) and the even harmonic values (82) with the operating current value and for producing an output signal (87R1) which in turn emerges as useful in producing a trip signal when the operating current value is larger than said sum.

Full Text	Description SYSTEM FOR POWER TRANSLATION DIFFERENTIAL PROTECTION Technical Field This invention relates generally to transformer internal fault protection for electric power transformers, and more specifically concerns differential protection for such a transformer which includes harmonic restraint and blocking capability. Background of the Invention It is important to first recognize and then take corrective action in response to the occurrence of internal faults in a power transformer. Prompt disconnection of the faulty transformer from the power system is necessary to avoid possible extensive damage to the transformer as well as to preserve power system stability and power quality. Several different techniques have been developed to detect internal transformer faults, which initially included phase overcurrent protection, differential protection using differential currents, and gas accumulator/rate of pressure rise protective techniques for arcing faults. Differential protection is currently widely used as protection against relay internal faults. In differential protection, operating currenc (IDP) (which may also be referred to as differential current), is compared with a restraining current (IaT). The operating current is defined as the phasor sum of currents entering che protected element {the transformer) as shown in the following equation and in Figure 1. In Figure 1, the power transformer 10 is protected by differential relay 11. CT1 and CT2 are current transformers. The operating current is proportional to the fault current fox transformer internal faults and approaches zero for non-faulted conditions. There are several equations for restraining current including the following equation. where k is a compensation factor, usually 1 or 0.5. A trip signal is gnerated if the operating current is greater than a selected percentage of the restraining current. Conventional differential protection arrangements may misoperate, however, in the presence of what are known as transformer inrush currents, which are the result of transients in the magnetic flux within the transformer. It has been recognized that the harmonic content of the differential current provides information which can help to differentiate actual internal faults from an inrush condition. Restraining techniques have been used which utilize all the harmonics of the differential current to distinguish inrush currents from internal fault conditions, so as to restrain a tripping action which would otherwise occur when there is in fact no internal fault. As indicated above, known differential restraining protection typically uses all of the harmonics, or a combination or selected odd and even harmonics, of the differential current. A blocking arrangement, which results in blocking of the trip signal, has also been used . in one blocking arrangement, a second harmonic of the differential current is used. Existing transformer differential relays thus use either all harmonic restraining or blocking techniques to distinguish between internal faults and inrush conditions. In addition, a fifth harmonic restraining technique has been used to prevent misoperation in response to transformer over-excitation, as opposed to internal faults. These restraining and/or blocking techniques have resulted in increased security relative to inrush and transformer over- excitation, but can result in a delay of ....................... tripping action for actual internal faults under certain conditions. Other techniquer, such xto recognition of wave shape distortion and recognition of the time interval during wnicn the differential current iff near zero, have been used still other techniques include recognition ot DC offset or asymmetry in the differential current and the comparison of the amplituded of positive and negative thresholds of differential current, with the selected thresholds being in two different—polarized elements. These techniques are often used as enhansments to the basic restraining and/or blocking functions described above. However, no combination of these techniques, have—been found which provide an adacuate solution, i.e accuracy for several opooifie inrush condition. Hence, there romaine an opportunity for significant improvement in distinguishing internal faults from inrush and over-excitation conditions for particular power system operating conditions. Disclosure of the Invention Accordingly, the present invention is for power transformer differential protection and comprises: means for developing a differential current value from processed current value which are representative of transformer (CT) secondary current values obtained from the windings of a power transformer; means for developing an operating current value from said differential current value; means for developing a restraining current value from said processed current values; means for obtaining even harmonic values of said differential current value; and means for comparing the sum of the restraining current values and the even harmonic values with the operating current value and for producing an output signal which in turn is useful in producing a trip signal when the operating current value to larger than said sum. Brief Description of thet Drawings* Figure 1 is a simplified prior art diagram illustrating the differential current for a protected element, such as a power system transformer. Figure 2 is a block diagram showing an initial current processing portion of the system of the present invention. Figure 3 is a block diagram responsive to the output values of Figure 1 to produce a restraining signal output using second and forth harmonics of the differential current. Figure 4 is a block diagram of a DC blocking logic circuit portion of the present invention. Figure 5 is a block diagram of the overall blocking logic portion of the system of the present invention. Figure 6 is a logic diagram which results in a tripping output signal from the system of the present invention. Figure 7 is a block diagram similar to that of Figure 3, with an added feature. Best Mode for Carrying Out the Invention The system of the present invention, which typically will be implemented as part, of a protective relay for a power transformer, includes preferably three differential element arrangements. Bach of the three differential elements/arrangements operates substantially identically, and can generally be considered as associated, respectively, as operating with the electric currents of a single phase (A, B or C) or a selected combination of phase currents, e.g. AB, BC and CA, for the three-phase power transformer. Accordingly, the following explanation is directed generally, except for a first portion which produces input values for all three differential elements, toward the structure and operation of one differential element arrangement. The other two differential element arrangements are substantially identical, both in structure and function, to the one element. Overall, the differential element arrangement of the present invention provides differential protection by means of an even harmonic restraining function and fifth harmonic and DC blocking functions. In addition, even harmonic blocking may be selected by the user as an alternative to even harmonic restraint. In applicants' invention/ the even harmonic restraining function may be used alone as a novel and unobvious alternative to existing differential protection systems, while fifth harmonic and DC blocking functions may be used individually with the even harmonic restraint function or used in combination with the even harmonic restraint function. Figure 2 shows a block diagram for the initial acquisition of the electrical current values from winding one of the power system transformer being protected, as well as the subsequent filtering, scaling and compensation thereof. Similar circuits are provided for the other windings. The input currents to the system of Figure 2 are the transformer secondary currents from winding 1 of the power transformer operating off the power line. These currents are shown generally at block 15 in Figure 2. These input currents are then applied to a system of analog low pass filters and analog-to-digital converters to produce filtered, digitized current samples. This arrangement is conventional and well- known and is represented in Figure 2 by a data acquisition block 16. The digitized current samples from data acquisition system 16 is applied to four digital band pass filters 17, 18, 20 and 22 and also to a DC filter 24. The outputs of these filters are then processed by identical conventional scaling circuits 28-28, with selected scale values, referred to as "tap" values, the outputs of which are passed to connection compensation circuits 30-30 to provide the output currents for winding 1 of the transformer. The output currents represented in blocks 31 through 34, are for the three differential elements and are referred to, respectively, as I1, I2, I3, from winding 1 of the transformer, including specifically the compensated fundamental, second harmonic, fourth harmonic and fifth harmonic values of the differential current, while the output currents represented in blocks 36 and 37 are the results of the DC filter 24 which receives the current samples from data acquisition block 16 and then forms one cycle sums of the positive (P) and negative (N) values of the samples. The output currents shown in blocks 31-27 are also referred to as processed winding currents. As indicated above, Figure 2 shows the acquisition and initial processing of the secondary currents from winding 1 of the transformer being protected, for all three differential element arrangements. The following explanation, however, concerns the structure and operation of only one differential element arrangement. Referring now to Figure 3, the processed winding current values I1W1F1C and I1W2F1C are applied to an adder 42. These signals are current values (I1) for the first differential element, specifically the compensated (C) fundamental quantity (F1) for windings 1 (W1) and 2 (W2) of the transformer. The output of adder 42 is converted to an absolute value by circuit 44, the output of which is the operating current value, IOPl. Wn is a shorthand representation for W1W2. This current value is applied to the plus input of a comparator 46. Applied to the minus input is a threshold value, identified as U87P. The value of U87P is selected to provide instantaneous overcurrent protection relative to the value of IOP1, a conventional and well-known protective relay function. The IOPl current value is also applied to the plue input of a comparator 50. Applied to the minus input of comparator 50 is a threshold current referred to as 087P. The value of O87P is a selected minimum pickup value necessary for a valid tripping function. Typically, this is a unitless value within a range of 0.1-1.2 multiples of the tap scale value. The output of comparator SO is applied as an enable input to a comparator 54. Comparator 54 will thus not produce an output unless the IOPl current is above a selected minimum value. The IOP1 operating current value is also applied to the plua input of comparator 54. The absolute values of the processed winding current values I1W1F1C and I1W2F1C, respectively, from Figure 2 are produced by circuits 58 and 60. The outputs of the absolute value circuits are applied to an adder 61. The output of adder 61 is scaled at block 62. While the scaler value in the embodiment shown is one-half, which is preferred, it could also be 1.0. The output of scaler 62 is the restraining current, referred to as IRT1. The restraining current IRTl is applied to one side of a switch 64 as well as the plus input of a comparator 68. Applied to the minus input of comparator 68 is a threshold value, referred to as IRS1. IRS1 in the embodiment shown is approximately 3 multiples of the tap scale value. The output of comparator 68 controls the position of switch 64. The two switch positions lead to circuits which modify the value of the restraining current by different slope characteristics to produce what is referred to as a restraint quantity. The slope characteristic generally defines the boundary between operation (trip) and restraining functions of the relay. The two possible slope modifications of ZRTl are shown in blocks 70 and 72. It is either a single slope modification (block 70) or a dual slope modification (block 72) . The output of blocks 70 and 72 is a restraint current quantity IRT/(9LP1, SLP2, IRSl) and is applied as an input to an adder 76. Referring still to Figure 3, the processed winding current values I1W1F2C and I1W2F2C from Figure 2, which are the compensated second harmonic current values of the currents from windings 1 and 2 of the transformer, are applied to an adder 77. The absolute value of the output of adder 76 is produced by circuit 78, which is then scaled (circuit 80) by a restraining factor referred to as 100/PCT2. Preferably, this value is approximately 15% but could be within the range of 5-50%. The output of scaler 80 is applied to an adder 82, as well as the plus input of a comparator 84. Similar circuits and circuit connections are provided for the fourth harmonic values of the currents from windings 1 and 2. The circuits include an adder 88, an absolute value circuit 90 and a sealer 92. The output of scaler 92 is applied to adder 82, as well as the plus input of a comparator 94. The minus inputs to comparators 84 and 94 in each case is the fundamental quantity of the differential current IOPl. The closing of switch 96 results in the circuit of Figure 3 operating in a restraining manner relative to producing a trip signal using the second and fourth (even) harmonics of the differential current. The output of adder 96 is applied as another input to adder 76, the output of which is applied to the minus input of comparator 54. The output of comparator 54, referred to aa 87R1, is a trip signal, if the blocking portion of the differential element is not asserted, as discussed hereafter. The tripping signal is an indication of an internal fault in the transformer, as opposed to inrush currents. In summary, when switch 96 is closed, the output of comparator 54 is in effect restrained by the even harmonic values of the differential current, preferably the second and fourth harmonic values, although additional even harmonic values can be used. With the even harmonic values, a greater IOPl than otherwise is necessary to produce a trip signal. Further, while the embodiment shown preferably uses both the second and fourth harmonics, it is possible to use just the second or some cases even the fourth harmonic alone in particular circumstances. Still referring to Figure 3, comparators 84 and 94 produce blocking signals, referred to as 2HB1 and 4HB1, respectively, which are the result of comparisons between the second and fourth harmonic values from windings 1 and 2 relative to the fundamental quantity of the operating current. The outputs of comparators 84 and 94 are used in the blocking circuit portions of the differential element when harmonic blocking is selected. The blocking signal for the system of the present invention is produced by the circuit of Pigure 5. The inputs to the circuit of Pigure S are four blocking signals, including signals 2HB1 and 4HB1, which are produced by the circuit of Figure 3, as discussed above. The third blocking signal, referred to as 5HB1 is the result of a comparison between the fifth harmonic value of the differential current relative to the fundamental current IOPl, similar to the comparisons which produced the 2HB1 and 4HB1 blocking signals. The blocking signal DCBLl is produced by the circuit of Figure 4. As shown in Figure 4, the sums of the positive (S+) and negative (S-) current samples over a current cycle are applied as inputs to a min/max circuit 100. A full cycle of differential current is shown at 101, while the positive and negative half-cycles thereof are shown pictorially in blocks 102 and 104. The positive and negative sum values are produced by the DC filter in Figure 2. The min/max circuit 100 determines the ratio of the minimum and the maximum of the positive and negative sums. If the maximum value is greater than a selected threshold value, the DC ratio (DCR) of the sums is calculated. This is accomplished by dividing the S+ and S- minimum sum values by the S+ and S- maximum sum values. The DCR signal is applied to the minus input of a comparator 102, while a threshold value, referred to as DCRF, is applied to the plus input of comparator 102. When the DCR value is less than the threshold value DCRF, the output of comparator 102 is a blocking signal referred to as DCBLl. Hence, the relay system blocking condition for DC blocking is in accordance with the following equation: DCR By defining DCR as the ratio of the minimum S+ and S- sum values to the maximum S+ and S- sum values, differential currents having similar positive or negative sums are accounted for. The DCRF value is typically 0.1, although it could be varied, such as within a range of 0.05-0.5. The DC blocking function helps to distinguish inrush currents from fault currents, since unipolar inrush currents typically have significantly larger positive or negative sums only. Referring again to Figure 5, the blocking portion of the differential element arrangement of the present invention produces a blocking signal output if any one of the individual blocking functions is present. If the even harmonic portion of Figure 3 is not in use for a restraining function, i.e. if switch 96 is in an open position, then switch 106 in Figure 5 closes automatically to produce the function of even harmonic blocking. In such an arrangement disclosed herein, the differential element arrangement operates in a blocking-only mode, without any even harmonic restraint function. The second harmonic and fourth harmonic blocking signals 2HB1 and 4HB1 from Figure 3, respectively, are applied to one side of switches 106 and 110. When switch 106 is in a closed position, either or both of the second and fourth harmonics can be used for blocking. Thie is accomplished by connecting switches 108 and 110 as inputs to an OR gate 112, the output of which is applied to one side of switch 106. Switch 106 is connected to OR gate 114, the output of which, if present, is the system blocking signal 87BL1. Switches 116 and 118 control the application of the fifth harmonic blocking signal, 5HB1, and the DC blocking signal, DCBL1 (the output of Figure 4), to OR gate 114. Hence, the blocking function of the differential element arrangement can be supplied by second, fourth and fifth harmonic.. signals which are the result of comparisons of those signals (scaled) with the operating current IOP1, as well as by the DC blocking signal DCBLl. If any of these individual blocking signals is present, the output of OR gate 114 is the blocking signal B7BL1. Figure 6 shows a circuit for combining the restraining function with the blocking function. The output of the circuit of Figure 6 produces the actual system tripping signal 87R, which is applied to a circuit breaker. The signal 87R indicates the presence of an internal fault. Figure 6 shows an "independent blocking" mode arrangement. In this arrangement, the restraining signals from the three differential elements in the system are supervised (overridden) by the blocking signals from the three differential elements. The restraining signal for each element is applied as one input to an associated AND gate while the other input is a NOT input for the blocking function for that particular element. Hence, for AND gate 126, the restraining signal 87R1 for the first differential element is applied to one input while the 87BL1 signal is applied to a NOT input thereof. AND gates 126 and 13O perform similar, independent functions for the other two differential elements in the system. The outputs of AND gates 126, 128 and 130 are applied to an OR gate 132, the output of which produces tripping signal 87R if there is a true or high output from any of the individual AND gates. The presence of the 87R tripping signal is on indication that there is an internal fault as opposed to an inrush or an over-excitation condition; the 87R signal results in the transformer being taken out of service. Figure 7 shows an alternative circuit similar to Figure 3, with an addition of one circuit 136. In Figure 7, if the second and fourth harmonics are to be used in the restraining circuit, then switch 96 is closed, as is the case with Figure 3; otherwise, it is open. Switch 140 is moved to position No. 1 if the DC current is larger than the RMS (root mean square) value of the fundamental quantity. otherwise, switch 140 is moved to position No. 2 and the overall circuit is identical in operation to that of Figure 3. In switch position No. l, the restraining quantity is multiplied by the value: Typically, k is a scale factor within the range of 0.5-3.0, preferably 1.5. IDC and IRMS are values from the differential current. When the DC component of the fundamental quantity ia greater than the RMS value of the fundamental quantity, the restraining output of the second and fourth harmonics is increaaed, i.e. given a boost. The above-described invention produces accurate results (distinguishing between a true internal transformer fault and selected other operating conditions, notably inrush and over-excitation, in a number of operating situations where previous arrangements have resulted in a misoperation. The use of the even harmonic currents to help in restraining the differential relay prevents misoperation in a number of cases. Adding fifth harmonic blocking and/or DC ratio blocking as supervision of the second and fourth harmonic restraining functions provides additional security. Further, the combination of even harmonic restraint with the DC ratio blocking provides a good compromise of speed and reliability. In summary, even harmonic restraining function improves security for inrush currents with low second harmonic content and further maintains dependability for internal faults where there is current transformer (CT) saturation. The use of the fifth harmonic blocking function in addition guarantees an appropriate relay response relative to over-excitation of the transformer, while the DC offset blocking function provides security for inrush conditions having very low total harmonic distortion. Hence, the present invention improves security and maintains dependability for particular transformer operating conditions, distinguishing appropriately between operating conditions which are not faults, and true internal transformer faults for which the transformer must be removed from service. Although a preferred embodiment of the invention has been disclosed here for purposes of illustration, it should be understood that various changes, modifications and substitutions may be incorporated without departing from the spirit of the invention, which is defined by the claims which follow. WE CLAIM: 1. A system for differential current protection including harmonic restraint and blocking for a power transformer, comprising: a. means for developing a differential current value (16) from processed winding values which are representative of current transformer (CT) secondary current values obtained from the windings of a power tranformer; b. means for developing an operating current value (44) from said differential current value; c. means for developing a restraining current value (62) from said processed winding current values; d. means for obtaining at least one even harmonic value of said differential current value (32); characterized by comprising i. means for comparing (54) of the sum (76) of the restraining current value (62) and the even harmonic values (82) with the operating current value and for producing an output signal (87R1) which in turn emerges as useful in producing a trip signal when the operating current value is larger than said sum. 2. The system as claimed in claim 1, comprising means for enabling (50) the comparing mean; when the operating current value is above a selected threshold value (087P). 3. The system as claimed in claim 2, wherein the selected threshold value is within the range of 0.1 —1.2. 4. The system as claimed in claim 1, wherein the restraining current value is the sum (61) of the absolute values of two differential current values, multiplied by a selected scale factor (62), and additionally multiplied by a selected slope characteristic, wherein the scale factor is one of 0.5 or 1.0 and wherein the selected slope characteristic is a selected one of a single slope characteristic (70) and a dual slope characteristic (72). 5. A system as claimed in claim 4, wherein the slope characteristic is determined (68) by the value of the restraining current value (62) relative to a selected threshold value (IRS1). 6. A system as claimed in claim 1, wherein said even harmonic values comprise the second harmonic value. 7. A system as claimed in claim 7, wherein said even harmonic values comprise the second and fourth harmonic values. 8. A system as claimed in claim 7, wherein the second (78) and fourth (90) harmonic values are absolute values, multiplied by first (80) and second (92) selected scale values, respectively. 9. A system as claimed in claim 8, wherein the first scale value (80) is within the range of 5 - 50% and the second scale value (92) is within the range of 5 - 50%. 10. A system as claimed in claim 1, wherein the operating current value (44) is the absolute value of the sum (42) of the differential currents for all of the transformer windings. 11. A system as claimed in claim 1, comprising means for blocking said output signal from operating as a tripping signal if the fifth harmonic of the differential current is larger than the operating current value. 12. A system as claimed in claim 1, comprising means for blocking (87BL1) said output signal from operating as a trip signal if the ratio of the minimums of the positive and negative one-cycle sample sums of the differential current to the maximums of said positive and negative one-cycle sample sums is below a threshold of 0.1. 13. A system as claimed in claim 12, comprising means for blocking (5HB1) said output signal from operating as a trip signal if a scaled fifth harmonic of the differential current is greater than the operating current value. 14. A system as claimed in claim 1, wherein said second (84) and fourth (94) harmonic values are used to block trip signals in the event that said harmonic values are not used to produce said output signals and said harmonic values are larger than the operating current value (IOP1). 15. A systems s claimed in claim 13, wherein said system operates on all three phases of the power system signal, and wherein the system produces an output signal and a blocking signal for each phase or combination of phases. 16. A system as claimed in claim 15, wherein the output signals and the blocking signals for each phase are processed independently relative to producing a tripping signal. The invention relates to a system for differential current protection including harmonic restraint and blocking for a power transformer comprising a means for developing a differential current value (16) from processed winding values which are representative of current transformer (CT) secondary current values obtained from the windings of a power transformer means for developing an operating current value (44) from said differential current value; means for developing a restraining current value (62) from said processed winding current values means for obtaining at least one even harmonic value of said differential current value (32). Means for comparing (54) the sume (76) of the restraining current value (62) and the even harmonic values (82) with the operating current value and for producing an output signal (87R1) which in turn emerges as useful in producing a trip signal when the operating current value is larger than said sum.

Full Text

Description
SYSTEM FOR POWER TRANSLATION DIFFERENTIAL PROTECTION
Technical Field
This invention relates generally to transformer
internal fault protection for electric power transformers, and
more specifically concerns differential protection for such a
transformer which includes harmonic restraint and blocking
capability.
Background of the Invention
It is important to first recognize and then take
corrective action in response to the occurrence of internal
faults in a power transformer. Prompt disconnection of the
faulty transformer from the power system is necessary to avoid
possible extensive damage to the transformer as well as to
preserve power system stability and power quality.
Several different techniques have been developed to
detect internal transformer faults, which initially included
phase overcurrent protection, differential protection using
differential currents, and gas accumulator/rate of pressure rise
protective techniques for arcing faults. Differential
protection is currently widely used as protection against relay
internal faults. In differential protection, operating currenc
(IDP) (which may also be referred to as differential current),
is compared with a restraining current (IaT). The operating
current is defined as the phasor sum of currents entering che
protected element {the transformer) as shown in the following
equation and in Figure 1.

In Figure 1, the power transformer 10 is protected by
differential relay 11. CT1 and CT2 are current transformers.
The operating current is proportional to the fault current fox
transformer internal faults and approaches zero for non-faulted
conditions. There are several equations for restraining current
including the following equation.

where k is a compensation factor, usually 1 or 0.5. A trip signal
is gnerated if the operating current is greater than a selected
percentage of the restraining current.
Conventional differential protection arrangements may
misoperate, however, in the presence of what are known as
transformer inrush currents, which are the result of transients
in the magnetic flux within the transformer.
It has been recognized that the harmonic content of the
differential current provides information which can help to
differentiate actual internal faults from an inrush condition.
Restraining techniques have been used which utilize all the
harmonics of the differential current to distinguish inrush
currents from internal fault conditions, so as to restrain a
tripping action which would otherwise occur when there is in fact
no internal fault.
As indicated above, known differential restraining
protection typically uses all of the harmonics, or a combination
or selected odd and even harmonics, of the differential current.
A blocking arrangement, which results in blocking of the trip
signal, has also been used . in one blocking arrangement, a
second harmonic of the differential current is used. Existing
transformer differential relays thus use either all harmonic
restraining or blocking techniques to distinguish between
internal faults and inrush conditions. In addition, a fifth
harmonic restraining technique has been used to prevent
misoperation in response to transformer over-excitation, as
opposed to internal faults.
These restraining and/or blocking techniques have resulted
in increased security relative to inrush and transformer over-
excitation, but can result in a delay of .......................
tripping action for actual internal faults under certain
conditions.
Other techniquer, such xto recognition of wave shape
distortion and recognition of the time interval during wnicn the
differential current iff near zero, have been used still other
techniques include recognition ot DC offset or asymmetry in the
differential current and the comparison of the amplituded of
positive and negative thresholds of differential current, with
the selected thresholds being in two different—polarized
elements. These techniques are often used as enhansments to
the basic restraining and/or blocking functions described above.
However, no combination of these techniques, have—been found
which provide an adacuate solution, i.e accuracy for several
opooifie inrush condition.
Hence, there romaine an opportunity for significant
improvement in distinguishing internal faults from inrush and
over-excitation conditions for particular power system operating
conditions.
Disclosure of the Invention
Accordingly, the present invention is for power
transformer differential protection and comprises: means for
developing a differential current value from processed current
value which are representative of transformer (CT) secondary
current values obtained from the windings of a power
transformer; means for developing an operating current value
from said differential current value; means for developing a
restraining current value from said processed current values;
means for obtaining even harmonic values of said differential
current value; and means for comparing the sum of the
restraining current values and the even harmonic values with the
operating current value and for producing an output signal which
in turn is useful in producing a trip signal when the operating
current value to larger than said sum.
Brief Description of thet Drawings*
Figure 1 is a simplified prior art diagram
illustrating the differential current for a protected element,
such as a power system transformer.
Figure 2 is a block diagram showing an initial
current processing portion of the system of the present
invention.
Figure 3 is a block diagram responsive to the output
values of Figure 1 to produce a restraining signal output using
second and forth harmonics of the differential current.
Figure 4 is a block diagram of a DC blocking logic
circuit portion of the present invention.
Figure 5 is a block diagram of the overall blocking
logic portion of the system of the present invention.
Figure 6 is a logic diagram which results in a
tripping output signal from the system of the present invention.
Figure 7 is a block diagram similar to that of Figure
3, with an added feature.
Best Mode for Carrying Out the Invention
The system of the present invention, which typically
will be implemented as part, of a protective relay for a power
transformer, includes preferably three differential element
arrangements. Bach of the three differential
elements/arrangements operates substantially identically, and
can generally be considered as associated, respectively, as
operating with the electric currents of a single phase (A, B or
C) or a selected combination of phase currents, e.g. AB, BC and
CA, for the three-phase power transformer. Accordingly, the
following explanation is directed generally, except for a first
portion which produces input values for all three differential
elements, toward the structure and operation of one differential
element arrangement. The other two differential element
arrangements are substantially identical, both in structure and
function, to the one element.
Overall, the differential element arrangement of the
present invention provides differential protection by means of
an even harmonic restraining function and fifth harmonic and DC
blocking functions. In addition, even harmonic blocking may be
selected by the user as an alternative to even harmonic
restraint.
In applicants' invention/ the even harmonic
restraining function may be used alone as a novel and unobvious
alternative to existing differential protection systems, while
fifth harmonic and DC blocking functions may be used
individually with the even harmonic restraint function or used
in combination with the even harmonic restraint function.
Figure 2 shows a block diagram for the initial
acquisition of the electrical current values from winding one of
the power system transformer being protected, as well as the
subsequent filtering, scaling and compensation thereof. Similar
circuits are provided for the other windings.
The input currents to the system of Figure 2 are the
transformer secondary currents from winding 1 of the power
transformer operating off the power line. These currents are
shown generally at block 15 in Figure 2. These input currents
are then applied to a system of analog low pass filters and
analog-to-digital converters to produce filtered, digitized
current samples. This arrangement is conventional and well-
known and is represented in Figure 2 by a data acquisition block
16. The digitized current samples from data acquisition system
16 is applied to four digital band pass filters 17, 18, 20 and
22 and also to a DC filter 24. The outputs of these filters are
then processed by identical conventional scaling circuits 28-28,
with selected scale values, referred to as "tap" values, the
outputs of which are passed to connection compensation circuits
30-30 to provide the output currents for winding 1 of the
transformer.
The output currents represented in blocks 31 through
34, are for the three differential elements and are referred to,
respectively, as I1, I2, I3, from winding 1 of the transformer,
including specifically the compensated fundamental, second
harmonic, fourth harmonic and fifth harmonic values of the
differential current, while the output currents represented in
blocks 36 and 37 are the results of the DC filter 24 which
receives the current samples from data acquisition block 16 and
then forms one cycle sums of the positive (P) and negative (N)
values of the samples. The output currents shown in blocks
31-27 are also referred to as processed winding currents.
As indicated above, Figure 2 shows the acquisition
and initial processing of the secondary currents from winding 1
of the transformer being protected, for all three differential
element arrangements. The following explanation, however,
concerns the structure and operation of only one differential
element arrangement.
Referring now to Figure 3, the processed winding
current values I1W1F1C and I1W2F1C are applied to an adder 42.
These signals are current values (I1) for the first differential
element, specifically the compensated (C) fundamental quantity
(F1) for windings 1 (W1) and 2 (W2) of the transformer. The
output of adder 42 is converted to an absolute value by circuit
44, the output of which is the operating current value, IOPl.
Wn is a shorthand representation for W1W2. This current value is
applied to the plus input of a comparator 46. Applied to the
minus input is a threshold value, identified as U87P. The value
of U87P is selected to provide instantaneous overcurrent
protection relative to the value of IOP1, a conventional and
well-known protective relay function.
The IOPl current value is also applied to the plue
input of a comparator 50. Applied to the minus input of
comparator 50 is a threshold current referred to as 087P. The
value of O87P is a selected minimum pickup value necessary for a
valid tripping function. Typically, this is a unitless value
within a range of 0.1-1.2 multiples of the tap scale value. The
output of comparator SO is applied as an enable input to a
comparator 54. Comparator 54 will thus not produce an output
unless the IOPl current is above a selected minimum value. The
IOP1 operating current value is also applied to the plua input
of comparator 54.
The absolute values of the processed winding current
values I1W1F1C and I1W2F1C, respectively, from Figure 2 are
produced by circuits 58 and 60. The outputs of the absolute
value circuits are applied to an adder 61. The output of adder
61 is scaled at block 62. While the scaler value in the
embodiment shown is one-half, which is preferred, it could also
be 1.0. The output of scaler 62 is the restraining current,
referred to as IRT1. The restraining current IRTl is applied to
one side of a switch 64 as well as the plus input of a
comparator 68. Applied to the minus input of comparator 68 is a
threshold value, referred to as IRS1. IRS1 in the embodiment
shown is approximately 3 multiples of the tap scale value. The
output of comparator 68 controls the position of switch 64. The
two switch positions lead to circuits which modify the value of
the restraining current by different slope characteristics to
produce what is referred to as a restraint quantity. The slope
characteristic generally defines the boundary between operation
(trip) and restraining functions of the relay. The two possible
slope modifications of ZRTl are shown in blocks 70 and 72. It
is either a single slope modification (block 70) or a dual slope
modification (block 72) . The output of blocks 70 and 72 is a
restraint current quantity IRT/(9LP1, SLP2, IRSl) and is
applied as an input to an adder 76.
Referring still to Figure 3, the processed winding
current values I1W1F2C and I1W2F2C from Figure 2, which are the
compensated second harmonic current values of the currents from
windings 1 and 2 of the transformer, are applied to an adder 77.
The absolute value of the output of adder 76 is produced by
circuit 78, which is then scaled (circuit 80) by a restraining
factor referred to as 100/PCT2. Preferably, this value is
approximately 15% but could be within the range of 5-50%. The
output of scaler 80 is applied to an adder 82, as well as the
plus input of a comparator 84. Similar circuits and circuit
connections are provided for the fourth harmonic values of the
currents from windings 1 and 2. The circuits include an adder
88, an absolute value circuit 90 and a sealer 92.
The output of scaler 92 is applied to adder 82, as
well as the plus input of a comparator 94. The minus inputs to
comparators 84 and 94 in each case is the fundamental quantity
of the differential current IOPl. The closing of switch 96
results in the circuit of Figure 3 operating in a restraining
manner relative to producing a trip signal using the second and
fourth (even) harmonics of the differential current.
The output of adder 96 is applied as another input to
adder 76, the output of which is applied to the minus input of
comparator 54. The output of comparator 54, referred to aa
87R1, is a trip signal, if the blocking portion of the
differential element is not asserted, as discussed hereafter.
The tripping signal is an indication of an internal fault in the
transformer, as opposed to inrush currents.
In summary, when switch 96 is closed, the output of
comparator 54 is in effect restrained by the even harmonic
values of the differential current, preferably the second and
fourth harmonic values, although additional even harmonic values
can be used. With the even harmonic values, a greater IOPl than
otherwise is necessary to produce a trip signal. Further, while
the embodiment shown preferably uses both the second and fourth
harmonics, it is possible to use just the second or some cases
even the fourth harmonic alone in particular circumstances.
Still referring to Figure 3, comparators 84 and 94
produce blocking signals, referred to as 2HB1 and 4HB1,
respectively, which are the result of comparisons between the
second and fourth harmonic values from windings 1 and 2 relative
to the fundamental quantity of the operating current. The
outputs of comparators 84 and 94 are used in the blocking
circuit portions of the differential element when harmonic
blocking is selected.
The blocking signal for the system of the present
invention is produced by the circuit of Pigure 5. The inputs to
the circuit of Pigure S are four blocking signals, including
signals 2HB1 and 4HB1, which are produced by the circuit of
Figure 3, as discussed above. The third blocking signal,
referred to as 5HB1 is the result of a comparison between the
fifth harmonic value of the differential current relative to the
fundamental current IOPl, similar to the comparisons which
produced the 2HB1 and 4HB1 blocking signals. The blocking
signal DCBLl is produced by the circuit of Figure 4.
As shown in Figure 4, the sums of the positive (S+)
and negative (S-) current samples over a current cycle are
applied as inputs to a min/max circuit 100. A full cycle of
differential current is shown at 101, while the positive and
negative half-cycles thereof are shown pictorially in blocks 102
and 104. The positive and negative sum values are produced by
the DC filter in Figure 2. The min/max circuit 100 determines
the ratio of the minimum and the maximum of the positive and
negative sums. If the maximum value is greater than a selected
threshold value, the DC ratio (DCR) of the sums is calculated.
This is accomplished by dividing the S+ and S- minimum sum
values by the S+ and S- maximum sum values.
The DCR signal is applied to the minus input of a
comparator 102, while a threshold value, referred to as DCRF, is
applied to the plus input of comparator 102. When the DCR value
is less than the threshold value DCRF, the output of comparator
102 is a blocking signal referred to as DCBLl. Hence, the relay
system blocking condition for DC blocking is in accordance with
the following equation: DCR By defining DCR as the ratio of the minimum S+ and S-
sum values to the maximum S+ and S- sum values, differential
currents having similar positive or negative sums are accounted
for. The DCRF value is typically 0.1, although it could be
varied, such as within a range of 0.05-0.5. The DC blocking
function helps to distinguish inrush currents from fault
currents, since unipolar inrush currents typically have
significantly larger positive or negative sums only.
Referring again to Figure 5, the blocking portion of
the differential element arrangement of the present invention
produces a blocking signal output if any one of the individual
blocking functions is present. If the even harmonic portion of
Figure 3 is not in use for a restraining function, i.e. if
switch 96 is in an open position, then switch 106 in Figure 5
closes automatically to produce the function of even harmonic
blocking. In such an arrangement disclosed herein, the
differential element arrangement operates in a blocking-only
mode, without any even harmonic restraint function.
The second harmonic and fourth harmonic blocking
signals 2HB1 and 4HB1 from Figure 3, respectively, are applied
to one side of switches 106 and 110. When switch 106 is in a
closed position, either or both of the second and fourth
harmonics can be used for blocking. Thie is accomplished by
connecting switches 108 and 110 as inputs to an OR gate 112, the
output of which is applied to one side of switch 106. Switch
106 is connected to OR gate 114, the output of which, if
present, is the system blocking signal 87BL1. Switches 116 and
118 control the application of the fifth harmonic blocking
signal, 5HB1, and the DC blocking signal, DCBL1 (the output of
Figure 4), to OR gate 114. Hence, the blocking function of the
differential element arrangement can be supplied by second,
fourth and fifth harmonic.. signals which are the result of
comparisons of those signals (scaled) with the operating current
IOP1, as well as by the DC blocking signal DCBLl. If any of
these individual blocking signals is present, the output of
OR gate 114 is the blocking signal B7BL1.
Figure 6 shows a circuit for combining the
restraining function with the blocking function. The output of
the circuit of Figure 6 produces the actual system tripping
signal 87R, which is applied to a circuit breaker. The signal
87R indicates the presence of an internal fault. Figure 6 shows
an "independent blocking" mode arrangement. In this
arrangement, the restraining signals from the three differential
elements in the system are supervised (overridden) by the
blocking signals from the three differential elements. The
restraining signal for each element is applied as one input to
an associated AND gate while the other input is a NOT input for
the blocking function for that particular element. Hence, for
AND gate 126, the restraining signal 87R1 for the first
differential element is applied to one input while the 87BL1
signal is applied to a NOT input thereof. AND gates 126 and 13O
perform similar, independent functions for the other two
differential elements in the system. The outputs of AND gates
126, 128 and 130 are applied to an OR gate 132, the output of
which produces tripping signal 87R if there is a true or high
output from any of the individual AND gates.
The presence of the 87R tripping signal is on
indication that there is an internal fault as opposed to an
inrush or an over-excitation condition; the 87R signal results
in the transformer being taken out of service.
Figure 7 shows an alternative circuit similar to
Figure 3, with an addition of one circuit 136. In Figure 7, if
the second and fourth harmonics are to be used in the
restraining circuit, then switch 96 is closed, as is the case
with Figure 3; otherwise, it is open. Switch 140 is moved to
position No. 1 if the DC current is larger than the RMS (root
mean square) value of the fundamental quantity. otherwise,
switch 140 is moved to position No. 2 and the overall circuit is
identical in operation to that of Figure 3. In switch position
No. l, the restraining quantity is multiplied by the value:

Typically, k is a scale factor within the range of 0.5-3.0,
preferably 1.5. IDC and IRMS are values from the differential
current. When the DC component of the fundamental quantity ia
greater than the RMS value of the fundamental quantity, the
restraining output of the second and fourth harmonics is
increaaed, i.e. given a boost.
The above-described invention produces accurate
results (distinguishing between a true internal transformer
fault and selected other operating conditions, notably inrush
and over-excitation, in a number of operating situations where
previous arrangements have resulted in a misoperation. The use
of the even harmonic currents to help in restraining the
differential relay prevents misoperation in a number of cases.
Adding fifth harmonic blocking and/or DC ratio blocking as
supervision of the second and fourth harmonic restraining
functions provides additional security. Further, the
combination of even harmonic restraint with the DC ratio
blocking provides a good compromise of speed and reliability.
In summary, even harmonic restraining function
improves security for inrush currents with low second harmonic
content and further maintains dependability for internal faults
where there is current transformer (CT) saturation. The use of
the fifth harmonic blocking function in addition guarantees an
appropriate relay response relative to over-excitation of the
transformer, while the DC offset blocking function provides
security for inrush conditions having very low total harmonic
distortion.
Hence, the present invention improves security and
maintains dependability for particular transformer operating
conditions, distinguishing appropriately between operating
conditions which are not faults, and true internal transformer
faults for which the transformer must be removed from service.
Although a preferred embodiment of the
invention has been disclosed here for purposes of illustration,
it should be understood that various changes, modifications and
substitutions may be incorporated without departing from the
spirit of the invention, which is defined by the claims which
follow.
WE CLAIM:
1. A system for differential current protection including
harmonic restraint and blocking for a power transformer,
comprising:
a. means for developing a differential current value (16)
from processed winding values which are representative
of current transformer (CT) secondary current values
obtained from the windings of a power tranformer;
b. means for developing an operating current value (44)
from said differential current value;
c. means for developing a restraining current value (62)
from said processed winding current values;
d. means for obtaining at least one even harmonic value
of said differential current value (32); characterized
by comprising
i. means for comparing (54) of the sum (76) of the
restraining current value (62) and the even harmonic
values (82) with the operating current value and for
producing an output signal (87R1) which in turn emerges
as useful in producing a trip signal when the operating
current value is larger than said sum.
2. The system as claimed in claim 1, comprising means for
enabling (50) the comparing mean; when the operating current
value is above a selected threshold value (087P).
3. The system as claimed in claim 2, wherein the selected
threshold value is within the range of 0.1 —1.2.
4. The system as claimed in claim 1, wherein the
restraining current value is the sum (61) of the absolute values
of two differential current values, multiplied by a selected
scale factor (62), and additionally multiplied by a selected
slope characteristic, wherein the scale factor is one of 0.5 or
1.0 and wherein the selected slope characteristic is a selected
one of a single slope characteristic (70) and a dual slope
characteristic (72).
5. A system as claimed in claim 4, wherein the slope
characteristic is determined (68) by the value of the restraining
current value (62) relative to a selected threshold value (IRS1).
6. A system as claimed in claim 1, wherein said even
harmonic values comprise the second harmonic value.
7. A system as claimed in claim 7, wherein said even
harmonic values comprise the second and fourth harmonic values.
8. A system as claimed in claim 7, wherein the second (78)
and fourth (90) harmonic values are absolute values, multiplied
by first (80) and second (92) selected scale values,
respectively.
9. A system as claimed in claim 8, wherein the first scale
value (80) is within the range of 5 - 50% and the second scale
value (92) is within the range of 5 - 50%.
10. A system as claimed in claim 1, wherein the operating
current value (44) is the absolute value of the sum (42) of the
differential currents for all of the transformer windings.
11. A system as claimed in claim 1, comprising means for
blocking said output signal from operating as a tripping signal
if the fifth harmonic of the differential current is larger than
the operating current value.
12. A system as claimed in claim 1, comprising means for
blocking (87BL1) said output signal from operating as a trip
signal if the ratio of the minimums of the positive and negative
one-cycle sample sums of the differential current to the maximums
of said positive and negative one-cycle sample sums is below a
threshold of 0.1.
13. A system as claimed in claim 12, comprising means for
blocking (5HB1) said output signal from operating as a trip
signal if a scaled fifth harmonic of the differential current is
greater than the operating current value.
14. A system as claimed in claim 1, wherein said second
(84) and fourth (94) harmonic values are used to block trip
signals in the event that said harmonic values are not used to
produce said output signals and said harmonic values are larger
than the operating current value (IOP1).
15. A systems s claimed in claim 13, wherein said system
operates on all three phases of the power system signal, and
wherein the system produces an output signal and a blocking
signal for each phase or combination of phases.
16. A system as claimed in claim 15, wherein the output
signals and the blocking signals for each phase are processed
independently relative to producing a tripping signal.
The invention relates to a system for differential current
protection including harmonic restraint and blocking for a power
transformer comprising a means for developing a differential
current value (16) from processed winding values which are
representative of current transformer (CT) secondary current
values obtained from the windings of a power transformer means
for developing an operating current value (44) from said
differential current value; means for developing a restraining
current value (62) from said processed winding current values
means for obtaining at least one even harmonic value of said
differential current value (32). Means for comparing (54) the
sume (76) of the restraining current value (62) and the even
harmonic values (82) with the operating current value and for
producing an output signal (87R1) which in turn emerges as useful
in producing a trip signal when the operating current value is
larger than said sum.

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Patent Number

224162

Indian Patent Application Number

IN/PCT/2002/00716/KOL

PG Journal Number

40/2008

Publication Date

03-Oct-2008

Grant Date

01-Oct-2008

Date of Filing

27-May-2002

Name of Patentee

SCHWEITZER ENGINEERING LABORATORIES, INC.

Applicant Address

2350 NORTHEAST HOPKINS COURT, PULLMAN, WA 99163

Inventors:

#	Inventor's Name	Inventor's Address
1	GUZMAN-CASILLAS ARMANDO	525 NORTHEAST ROBEN STREET, PULLMAN, WA 99163
2	ALTUVE FERRER HECTOR	RICARDO MORALES 1072, COLONIA HACIENDS LOS MORALES, SAN NICOLAS DE LOS GARZA, MEXICO, NL 66490
3	ZOCHOLL STANLEY E	71 EAST RAMBLER, HOLLAND, PA 18966
4	BENMOUYAL GABRIEL	115 D'LGE, BOUCHERVILLE, QUEBEC J4B 6J2

PCT International Classification Number

H02H 7/045

PCT International Application Number

PCT/US00/42292

PCT International Filing date

2000-11-28

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	09/450,808	1999-11-29	U.S.A.