Title of Invention

"A TESTING DEVICE AND METHOD FOR MONITORING SALICIDE AND LOCAL INTERCONNECT PROCESS"

Abstract A testing device for monitoring salicide and local interconnect process comprising a plurality of transistor (T) provided in a plurality of rows (R) and columns (C) in order to form a matrix of transistors, the transistors are connected with each other to select each transistor by choosing a particular row and a particular column, the gate and drain of said transistor being shorted by TiN local interconnect.
Full Text This invention relates to a test structure for monitoring SALICIDE and local interconnect processes during development and production phases.
One o-f the major problems in a VLSI fabrication process is to identify the nature o-f faults associated with the technology and their exact, location. Faults result in yield degradation end their understanding is required so that the factors causing yield deqradation can be identified. The occurrence of faults need to be manitored and analysed in greater details when entirely new features art? introduced in the technology. Since the understanding of new features are Generally minimal, care-fully thought out structures should be incorporated in the test. chip and to be monitored during the development and production phases.
Monitoring of- SALICIDE process is done by measuring parameters such as sheet resistivity, contact resistance. diode leakages etc. Transistor characteristic can also sometime re-fleet the problem such as short between various silicided regions. The structures used for measurement of sheet resistivity, contact resistance and diode leakage have been shown in
Fig. 1. Fig 2 also be monitored by measuring sheet resistivity, contact resistance and diode leakage using approximate structures.
However, these structures cannot monitor occasional short between source (or drain) to gate due to SALICIDE process. Moreover, reliability of TiN local interconnect layer also cannot be monitored by individual structures described above. It is also not possible to pinpoint the exact fault location for a unreliable SALICIDE or local interconnect process.
An object of this invention is to propose a structure for monitoring the SALICIDE and local interconnect processes during development an production phases.
Another object of this invention is to propose a structure which can be used to generate date base for transistor parameters to establish the reliability of SALICIDE and TiN local interconnect technologies.
According to this invention there is provided a testing device for monitoring salicide and local interconnect process comprising a plurality of transistor (T) provided in a plurality of rows (R) and columns (C) in order to form a matrix of transistors, the transistors are connected with each other to select each transistor by choosing a particular row and a particular column, the gate and drain of said transistor being shorted by TiN local interconnect.
Further according to this invention there is provided a method for monitoring salicide and local interconnect process using the testing device comprising testing the isolation of all the rows (R) and columns (C) for shorts, repeating the testing step for entire matrix, accessing each transistor (T) by selecting corresponding row and column line and then measuring the current between gate of source for each transistor array, subjecting said transistors the step of testing to pass or fail a particular transistor by using a software program to find out the leakage value whether it falls within the pass criteria or not.
In accordance with this invention, a matrix of a plurality of transistors is prepared by providing a number of transistors arranged in a number of rows and by providing a number of columns so as to form a matrix such that each transistor can be selected by choosing a particular row and a particular line. The gate and drain of the transistors are shorted by in local interconnect.
Further in accordance with the process of this invention the monitoring of SAL1CIDE and local interconnect process during the development and production base; comprises in testing the isolation of all the rows and columns for short. The step of testing isolation is repeated for the entire matrix. Then each transistor is accessed by selecting corresponding row and column line. Leakage- correct between gate of source is measured for each transistor in the array and software program is used to past or fail the particular transistor depending upon whether the leakage value falls within the pass criteria or not..
A test structure for monitoring local interconnect process and a process of monitoring SALIC IDE and local interconnect process according to a preferred embodiment is herein described and illustrated where in: --
Fig.1 & to
Fig.3 shows the test structure* known in
the art. prior art.
Fig ,4 shows the schematic view of the test structure of the present, invention.
Referring to the drawings particularly Fig.4 the test, structure of the present, invention has a plurality
of transistors T provided in a rows P. and a plurality of transistors T provided in a columns 0 in order to farm a matrix o-f transistors T. For example the-transistors T are arranged in 9 rows, and 11 columns as shown in Fig.4. Then interconnections have been provided in such a way that each transistor can be selected by choosing a particular row and a particular column line. Six rows, and eleven columns,, ie. 66 transistors in total can be dedicated to only SAL1CIDE process. Other transistors in 5 rows and 11 columns, ie. 53 in total are use to monitor local interconnect process. Gate and drain of transistors are shorted by TiN local interconnect. The later set of transistors have both SAL 1C IDE and local interconnect. Test procedure consists o-f two steps. First, the isolation of all the rows and columns are tested for shorts and this test is repeated for the entire matrix. Then each transistor is accessed by selecting corresponding row and column line. Leakage current between gate to source is measured for each transistor in the array and a software program is used to pass or fail a particular transistor depending upon whether the leakage value fells within the pass criteria or not. According to the other embodiments several combination of process splits can be used to monitor each technology. For example, same? wafer runs can have? split such that, some wafers are process ith SALICIDE and others without it. Similarly, SALICIDE and local interconnect processes can be done simultaneously on the same wafer and compared. Therefore, this method can be use very successful1 y to isolate the failure. Tab lee 1 and 2 show part of & typical map date printout of the special test structure. For a good die, leakage value has to be within ( —) 1008PA and 1000PA. If the leakage values lie outside this limit, then the die will be considered as failed. Tables I & 2 corresponds to two wafers fabricated with different process parameters. In Table 1, all data lie within specifications indicating no shorts between gate to source. In Table 2, site 4 shows leakage correct of more than .1 uA indicating diode leakage or silicide short. Subsequent 1 y further analysis; was done a* per procedure described above. It was found that. 4 transistor in that array have diode leakage more than the specifications.
TABLE 1
(Table Removed)
TABLE 2

(Table Removed)






WE CLAIM;
1. A testing device for monitoring salicide and local interconnect process comprising a plurality of transistor (T) provided in a plurality of rows (R) and columns (C) in order to form a matrix of transistors, the transistors are connected with each other to select each transistor by choosing a particular row and a particular column, the gate and drain of said transistor being shorted by TiN local interconnect.
2. A method for monitoring salicide and. local interconnect process
using the testing device as claimed in claim 1 comprising
testlng the isolation of all the

rows (R) and columns (C) for shorts, repeating the testing step for entire matrix, accessing each transistor (T) by selecting corresponding row and column line and then measuring the current between gate of source for each transistor array, subjecting said transistors the step of testing to pass or fail a particular transistor by using a software program to find out the leakage value whether it falls within the pass criteria or not.
3. A testing device for monitoring salicide and local interconnect
process substantially as herein described and illustrated.
4. A method for monitoring salicide and local interconnect process substantially as herein described and illustrated.

Documents:

1850-del-1997-abstract.pdf

1850-del-1997-claims.pdf

1850-del-1997-correspondence-others.pdf

1850-del-1997-correspondence-po.pdf

1850-del-1997-description (complete).pdf

1850-del-1997-drawings.pdf

1850-del-1997-form-1.pdf

1850-del-1997-form-19.pdf

1850-del-1997-form-2.pdf

1850-del-1997-form-4.pdf

1850-del-1997-form-5.pdf

1850-del-1997-form-6.pdf

1850-del-1997-gpa.pdf

1850-del-1997-petition-138.pdf


Patent Number 219866
Indian Patent Application Number 1850/DEL/1997
PG Journal Number 28/2008
Publication Date 11-Jul-2008
Grant Date 13-May-2008
Date of Filing 02-Jul-1997
Name of Patentee THE SECRETARY, DEPARTMENT OF ELECTRONICS.
Applicant Address 6 CGO COMPLEX, NEW DELHI 110 003, INDIA.
Inventors:
# Inventor's Name Inventor's Address
1 DR J N ROY
PCT International Classification Number H01L 21/70
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA