Title of Invention

"A PULSE PLATING DEVICE USEFUL FOR PREPARATION OF SEMICONDUCTING THIN FILMS"

Abstract A pulse plating device useful for preparation of semi conducting thin films, which comprises microprocessor assembly essentially consisting of an at least 8-bit microprocessor with keyboard controller, random access memory, erasable programmable read only memory, interrupt controller an programmable peripheral interface, the output of the said microprocessor assembly being connected to the input of an at least 8-bit digital to analog converter, the output of the said digital to analog converter being connected through a potential and current controller to a three electrode electrochemical plating cell
Full Text The present invention relates to ^device useful a^a pulse plating anitffor -tbtosemiconducting Ifilirns".
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Hitherto, commercially available plating instruments like D.C power supplies , programmable pulse generators and pulse power supplies have been employed for the preparation of semiconducting films.
In the pulse plating method using d.c supplies , the switching on and switching off were controlled manually hence on / off time less than few seconds could not be acheived . Further different pulse shapes and reverse pulses could not be generated .
Commercially available programmable pulse generators coupled with either potentiostat or galvanostat have also been used earlier for the preparation of thin semiconducting films. Main drawback of these instruments is that different pulse shapes like pulsed pulse, pulse -on-pulse , staircase pulse , reverse pulse etc cannot be produced . On / off durations cannot be reduced below 100 milliseconds and duty cycles lower than 10 % cannpl be acheived . Further these pulse generators are costly.
Commercially available pulse power supplies are also used nowadays for plating purpose. In addition to the high cost (around 1.5 to ^ lakhs) they are not suitable for low current applications (less than 100 milliamps ) . Only peak currents values can be set in the instrument and average current utilised for the deposition can be calculated . Different pulse shapes like pulsed pulse , pulse -on -pulse , pulse -on- pulse reverse, superimposed pulse , staircase pulse etc cannot be produced and only reverse pulse is generated .
The main object of the present invention is to provide a device useful as a pulse plating unit for depositing thin semiconducting films which obviates the drawbacks as detailed above.
Another object of the present invention is to provide a microprocessor based pulse plating unit for depositing thin films semiconductor films which comprises of a microprocessor assembly with cpu, memory interfaces, digital to analog-convertet (DAC) , current / potential controller and three electrode electrochemical cell with suitable software to program the microprocessor.
Yet another object of the present invention is to provide a device capable of thin film deposition at low current levels of less than 100 milliamps, on / off durations below 100 milliseconds and duty cycles lower than 10%.
In an embodiment of the device of the present invention the microprocessor based pulse plating unit which generates pulses for the preparation o semiconductor thin films is shown in Figures 1 & 2 of the drawings accompanying this specification. The embodiment of the microprocessor based pulse plating unit of the present invention as shown in fig 1 & 2 consist of Microprocessor unit with Key Board controller, Random Access Memory. Erasable Programmable Read Only Memory. Interrupt controller, Programmable Peripheral Interface, Battery back up facility for memory and to digital to analog converter.
Accordingly the present invention provides a A pulse plating device useful for preparation of semi conducting thin films, which comprises a microprocessor assembly, the said microprocessor essentially consisting of an at least 8-bit microprocessor with keyboard controller, random access memory, erasable programmable read only memory, interrupt controller an programmable peripheral interface, characterized in that output of the said microprocessor assembly being connected to the input of an at least 8-bit digital to analog converter, the output of the said digital to analog converter being connected through a potential and current controller to a three electrode [reference(R), working(W), counter(c )] electrochemical plating cell so as to provide and maintain the potential sensed by the said reference and working electrode combination and the necessary current to maintain the deposition potential of the said counter and working electrode combination .
In an embodiment of the present invention the device may be powered with standard uninterrupted power supply.
In another embodiment of the present invention the potential and current controller used may be such as to be able to provide and maintain the potential sensed by the reference and working electrode combination and the necessary current to maintain the deposition potential of the counter and working electrode combination.
The required potential pulses of different shapes and duration are generated by the microprocessor using the software developed for that purpose. The square potential waveforms are available at the output ports (PP) of the microprocessor unit. The digital waveforms are converted
into analog potential signals by the digital to analog converter (DAC) and fed to the three electrode
\ electrochemical plating cell through a potential and current controller. The potential controller is used
here to maintain the potential sensed by the reference (R) and working electrode (W) combination and the necessary current to maintain the deposition potential is provided by the counter (C) and working electrode (W) combination.
The main purpose of reversing the current from cathodic to anodic condition for a small fraction of the total period is to remove semiconductor preferentially from areas that tend to
overplate during the cathiodic part of the cycle . It is then possible to prevent the development of dentrite growth . Required grain size can be obtained by suitably modifying the current density . It is cleart that adsorption and desorption as well as recrystallization phenomena will be quite diffrent from those in pulse plating.
Different pulse amplitude and pulse widths can be generated . Pulse widths could be varied from 50 microseconds to even hours and duty cycle as low as 0.0001% can be acheived. Pulse amplitudes can be set from - 2.00 V to +2.00 V . Current in the range from 100 mA to 1 A can be applied to the cell in the galvanostatic condition. Deposition times can be programmed in advance and after the present time is over the electrode can be removed from the electrolyte automatically by using stepper motor controls. This automatic deposition process avoids human errors. Semiconductors like CdSe , CdTe , Cd(Se, Te) , CdS , ZnSe , PbS have been deposited using this system.
This invention is described in detail in the following examples which are provided by way of illustration only and therefore should not be construed to limit the scope of the invention .
Example 1:
Potentiostatic condition:
The three electode cell contains 0.1 M cadmium sulphate with 25 mM of telurium di oxide as the electrolyte . To improve the electrolyte conductivity and for adjusting the pH ~ 2 to the required level 1 M sulphuric acid was added . Fig.1 of the drawings accompanying this specification represents the potentiostatic arrangement. The three electrodes are graphite as anode , saturated calomel electrode as reference and titanium as the cathode . The deposition being cathiodic , films get deposited on titanium substrate . CdTe films were deposited using the following conditions .
DEPOSITION POTENTIAL : - 680 mv versus SCE
DEPOSITION TIME : ONE HOUR
ON TIME : 1 SEC
OFF TIME : 15 SEC
DUTY CYCLE : 6.25 %
The deposited CdTe films were confirmed to be polycrystalline in nature by XRD studies. From optical absorption studies , the band gap of CdTe was found to be 1.52 eV. The uniform

thickness was found from Microscopic estimation by Universal microscope . Using Schierr's equation the uniform grain size of the films were estimated.
Example 2:
Galvanostatic condition:
In galvanostatic mode the constant current pulses from microprocesor are fed to the cell. Fig.2 of the drawings accompanying this specification represents the galvanostatic arrangements.PbS films were deposited using the following conditions. The plating bath consist of 0.33 M lead acetate and 0.05 M N - methylthiourea as the electrolyte.



DEPOSITION CURRENT DENSITY DEPOSITION TIME ON TIME OFF TIME DUTY CYCLE

50 mA/cm2 ONE HOUR 1 SEC 10 SEC 9%

Films were found to be polycryststalline PbS from XRD studies. From optical absorption studies, the band gap was found to be 0.42 eV. The uniform thickness was found from Microscopic estimation by Universal microscope . Using Schierr's equation the uniform grain size of the films were estimated.
EXAMPLE 3:
Pulse reverse deposition:
CdSe films were deposited under the following conditions . The plating bath consists of 0.5 M of cadmium sulphate with 0.1 M of selenium dioxide as the electrolyte . To improve the electrolyte conductivity and to adjusting the pH ~ 2 .1 by 1 M sulphuric acid was added.

CATHODIC POTENTIAL ANODIC POTENTIAL CATHODIC ON TIME ANODIC ON TIME OFF TIME DEPOSITION TIME DUTY CYCLE (cathodic) DUTY CYCLE (anodic )

- 900 mv versus SCE + 50 mv versus SCE 1 sec 50 m.sec 29 sec ONE HOUR 3.33 % 0.55 %

Films were found to be polycrystalline CdSe from XRD studies. From optical absorption studies, the band gap of CdSe was found to be 1.70 eV. The uniform thickness was found from Microscopic estimation by Universal microscope . Using Schierr's equation the uniform grain size of the films were estimated.
The main advantage of the device of the present invention are
1. The improved pulse plating unit is economical and can be constructed at a lower cost
compared to commercially available pulse generator.
2. Potential, Current controlled and pulse reverse deposition is possible with this set up.
3. Deposition can be done even at low current levels of the order of 100 microamps which is not
possible with commercially available generators.
4. Potential / current pulse of any duration from 100 microseconds to twelve hours and duty cycle
as low as 0.0001 % can be easily programmed.
5. The required plating time can be programmed in advance to avoid human supervision.



We Claim:
1. A pulse plating device useful for preparation of semi conducting thin films, which
comprises a microprocessor assembly, the said microprocessor essentially consisting of
an at least 8-bit microprocessor with keyboard controller, random access memory,
erasable programmable read only memory, interrupt controller an programmable
peripheral interface, characterized in that output of the said microprocessor assembly
being connected to the input of an at least 8-bit digital to analog converter, the output of
the said digital to analog converter being connected through a potential and current
controller to a three electrode [reference(R), working(W), counter(c )] electrochemical
plating cell so as to provide and maintain the potential sensed by the said reference and
working electrode combination and the necessary current to maintain the deposition
potential of the said counter and working electrode combination .
2. A device as claimed in caliml wherein the device is powered with standard uninterrupted
power supply.
3. A pulse plating device useful for preparation of semi conducting thin films substantially as
herein described with reference to the examples and drawings accompanying this
specification.

Documents:

3384-del-1998-abstract.pdf

3384-del-1998-claims.pdf

3384-del-1998-correspondence-others.pdf

3384-del-1998-correspondence-po.pdf

3384-del-1998-description (complete).pdf

3384-del-1998-drawings.pdf

3384-del-1998-form-1.pdf

3384-del-1998-form-19.pdf

3384-del-1998-form-2.pdf


Patent Number 215654
Indian Patent Application Number 3384/DEL/1998
PG Journal Number 12/2008
Publication Date 21-Mar-2008
Grant Date 29-Feb-2008
Date of Filing 13-Nov-1998
Name of Patentee COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH
Applicant Address RAFI MARG, NEW DELHI- 100 001, INDIA
Inventors:
# Inventor's Name Inventor's Address
1 VISWANATHAN SWAMINATHAN SENIOR RESEARCH FELLOW, CENTRAL ELECTROCHEMICAL RESEARCH INSTITUTE, KARAIKUDI 630 006, TAMILNADU
2 RANGARAJAN SRINIVASAN SCIENTIST, CENTRAL ELECTROCHEMICAL RESEARCH INSTITUTE, KARAIKUDI 630 006, TAMILNADU
3 VENKATASUBRAMANIA SUBRAMANIAN SCIENTIST, CENTRAL ELECTROCHEMICAL RESEARCH INSTITUTE, KARAIKUDI 630 006, TAMILNADU
4 KOLLEGAL RAMAKRISHNA MURALI SCIENTIST, CENTRAL ELECTROCHEMICAL RESEARCH INSTITUTE, KARAIKUDI 630 006, TAMILNADU
PCT International Classification Number C25D 5/56
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA