Title of Invention

A PROCESS FOR PREPARING A DOUBLE LAYER METALLIZED UNIT WITH POROUS SILICON TO PRODUCE LARGE AREA PATTERNED DISPLAY DEVICE.

Abstract Porous Silicon (PS) has been used in devices meant for light emission but the results are far from satisfactory mainly due to diffused and non-uniform nature of emitted light and in some cases the onset voltage and current are very high. The present invention aims at overcoming the above drawbacks and provides a process for preparing a double layer metallized unit with porous silicon to produce large area patterned display device, which comprises i) selecting a p-type wafer of (100) or (111) configuration as the starting material; ii) doping a selected part of the said wafer with boron, followed by-doping with phosphorous to form n+ p+ junction; iii) preparing porous silicon in a formation bath of 12-48% HF and CH3OH with suitable electrode(s) like graphite to form highly uniform porous silicon layer; iv) drying the thus formed porous silicon in a suitable liquid such as herein described to prevent surface cracking; v) oxidising the dried porous silicon layer by 10 vol H202 under optimum conditions such as herein described to stabilize the system; vi) depositing a thin layer (2) of metal like Al, In or Au by evaporation on top of the porous silicon strata (1); vii) forming another layer of metallic substance like Cu, Ag, Au, or Al having grid structure with optimum grid and spacing (3) on top of said thin metal layer by evaporation to form a double layer metal contact; viii) heat treating the material from step (vii) at around 450 - 500 for around 60 seconds under inert atmosphere of nitrogen and (ix) providing contact wire (4) from each segment leading to contact pad (5) for achieving uniform light emission from each one of daid segments.
Full Text The present invention relatesprocess for preparing a double layer metalized with porous silicon

to produce layer area patterned display deviceto a large area patterned display device More particularly this invention pertains to a large area Seven segment display device based on porous silicon which not only displays numerals, but is also capable of displaying patterns and / or alphabets of English, Greek or any other language on suitable display units associated with or attached to various other instruments, panels, boards, and the like substrates. This invention also includes within its ambit a process for preparing the aforesaid porous silicon (hereinafter referred to as "PS" in this specification for the sake of brevity) based display device.
Crystalline silicon (Si) happened to be most widely used semiconductor in present day electronics and computer technology, which is an indirect band - gap material having a band-gap of I.I eV at room tempenuure. Hence, it cannot emit luminescence in the visible region efficiently. This fact restricts use of silicon in opto-electronic applications, wheie compound semiconductors with direct band gap such as, for instance, GaAs, inP etc. are dominant materials in use at present. Difficulties stand in the way of combining such materials (e.g. GaAs, InP, etc.) with silicon -integrated circuit technology which have hindered turther developments and applications. However, porous silicon (PS), an electrochemical derivalive of crystalline silicon, has been found to behave like a direct - gap material and emit light in the visible region of the spectrum under ultra violet (UV) exposure or application of proper bias This su'pnsing observation of light emitting property of PS has served as the basis of the present indention which has led to the development of a novel large area display device capable of depiclmg any pattern or alphanumericat motifs.
Porous silicon (PS) based light emitting diodes (LED) have been known for sometime, Effects have been and are still being made by various scientific workers all over the world to develop PS-based LEDs for large area display applications. The basic features of devices deigned and used heretofore are:
i) using n- or p-type Si wafers as the starting material,
ii) forming junction(s) by employing diffusion technique,
iii) forming layer(s) of PS by electrochemical anodtzation of-the diffused wafer in HF-based electrotyte,

iv) depositing a transparent or semi-transparent metal film on the PS-layer and v) activating the metal layer which acts as the light emitter layer of the display device.
The above - described procedure followed till date suffer from a number of drawbacks which, inter alia, may be enumerated as follows :
a) The effective PS-layer formed in conventional anodization bath using cylindrical or flat
electrode invariably becomes laterally non-uniform. This result in non-uniform light
emission from the display device in case of large area (-5cm2) of illumination.
b) A single semi-transparent or very thin metal layer used for the top metal contact becomes
highly resistive due to smaller thickness. This high resistance causes norv-uniform carrier
injection resulting in diffused and non-uniform light emission.
c) In some devices comparatively thick metal layer has been used to minimize resistance,
but this causes decrease in transparency of the layer. In such devices light is emitted only
from the edges of the metal pads with significant decrease in power efficiency.
d) In some other devices the onset voltage and current are very high, rendering them in
compatible with present day Si-IC electronic devices.
The principal object of the present invention is to provide a novel large area patterned device which uses a double layer metallization to minimize non-uniformity in carrier injection leading to non-uniform light emission.
A still further object of this invention is to provide a novel device which is highly compatible with modem Si-IC technology and circuits in view of its operating voltage and current.
Another object of this invention is to provide a novel device which can be as large as 80 cm2 area, emitting light in the visible region whereby it is capable of being seen with the naked eye in dark and also in diffused light
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Yet another object of this invention is to provide a novel large area display device whjrh can be used for alphanumeric digital display unit in any suitable instrument.
A still another object of this invention is to provide a novel large area patterned display device wherein the display and its driver/logic circuit can be fabricated on a single wafor to provide a "system on chip (SOC)"
A yet further object of this invention is to provide a process for preparing a novel large area patterned display device based on porous silicon (PS) as enumerated above.
The foregoing objects are achieved by the present invention which relates to a novel porous silicon based large area patterned display device, which compfiseS in combination:-
a) a base of SiO2on silicon wafer:
b) a plurality of segments composed of porous silicon having" deposited thereon a
thin metal layer,
c) a thick metal grid formed on the thin metal layer:
d) contact wire from each segment leading to and connected with
e) contact pad.
This invention further relates to a process for preparing area 17
patterned display device as defined above which comprises -
i) selecting a p-type wafer of (100) or (101) orientation as the starting material, ii) doping a selected part of the said wafer with boron, followed by doping with phosphorous to form n p junction,
iii) preparing porous silicon (PS) in a formation bath/with suitable electrode(s)/to form highly uniform porous silicon layer,
iv) drying the thus formed porous silicon in a suitable liquid/to prevent surface cracking.
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v) oxidising the dried porous silicon layers/under optimum conditions/to stabilize the system,
vi) depositing a very thin layetfby evaporation on top of the porous silicon strata,
like Cu, Ag, Au or Al
vii) forming another layer of metallic substance/having grid structure having optimum grid and spacing on top of the said thin meta! layer by evaporation to form a double layer metal contact.
viii) heat treating the material from step (vii)under inert atmospheic/and
ix) providing contact from each segment leading to contact pad for achieving uniform light emission from each one of said segments.
The thin metal layer deposited on porous silicon segment is of the order of 25-30 nm and the thick metal grid formed on the thin layer is of the order of-500 nm. The former metallic layer may be of^silver or gold, silver being preferred for its greater malleability and ease of handling, n. The thick metallic layer formed over the thin layer may be obtained by using metals like Al, Au, Ag, Cu or any other similar metal capable of forming highly conducting layer. At the bottom of the device there is provided a screen-printed Ag-AI layer serving as the base for hotdingV serving as ohmic back contact. It is to be noted that the dimensions of the component parts are flexible, varying between fairly wide Hinges, depending on the overall dimensions of the final device.
Studies are in progress to assess the effects of addition of traces of metal /metal compoundts) to different segments for obtaining varying colour shades of emitted light, apart from the usunl yellow colour.
The formation bath employed for preparing porous silicon is comprised of 12-48% HF and CH3OH in which the wafer is dipped for i -5 minutes, using a current density of 2-20 mA / cm2 and electrode(s) of guard plate type. PS thus formed is dried in a suitable liquid like a low molecular weight alcohol such as ethanol, isopropand./etc. for preventing appearance of surface cracks.
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by H2O2 (tO vol.strength)
Oxidation of the dried silicon wafer is initially done/ynder wet condition at around 10OOC°0 for 1 hour more or less in presence of moisture. Oxidation of PS layer is conducted in a sueam of oxygen for around 10 mins under ambient condition of temperature and pressure.
Deposition of thin metal layer is carried out by using conventional vacuum evaporation technique. Formation of second metallic layer with optimum grid and spacing is conducted by photolithography followed by vacuum evaporation.
The device of this invention will now be more particularly described and illustrated with the help of the accompanying drawings in which -
Fig. 1, shows the top schematic view of the PS ~ large area seven segment display showing double layer metallization.
Fig, 2. shows the schematic cross sectional view of the device and
Fig, 3, depicts a flow-chart giving the details of the process for providing PS area patterned device,
In Fig. 1,(1) shows SiO2 on Si wafer, (2) is the thin metal layer on (1), (3) is the thick metal grid on thin metal layer of (2), (4) shows the contact wire and (5) stands for contact pad,
In Fig, 2 showing the cross-sectional view of the device of this invention (1), (2), (3) and(4) have trie same significance as given above, (6) shows the location of n+ Si, (6) is p+ Si, (7) siands for p Si and screen-printed Ag-Al layer serving as another electrode is;designabed by (8).
Flow chart diagram shown in Fig. 3 illustrates the detailed procedure for fabrication of large area patterned display device, included therein some of the standard procedures like cleaning of Si-wafer, screen printing with biack ink or wax, bakins, diffusion, removal oC etchant removal of black ink, removal of photoresist, heat treatment in inert atmosphere, etc. However, it is to be noted that these conventional steps employed in the present process form an integral part thereof and play a significant role.

To start with Si wafer of 100 or 111 configuration may be used. Oxidation of the cleaned wafer is conducted under wet condition at around 1000°C for a duration in the vicinity of around 1 hour. Dry oxidation of PS layer is carried out under ambient conditions for around 10 minutes. The width of the thin metallic film of Ag or Au varies between 25 and 30 nm. The thickness of the second metallic layer formed by photolithography followed by vacuum evaporation using a suitable mask is of the order of 500 nm. Metal(s) forming the thick layer may be highly conducting one, selected from the group of Ag, Al, Au and Cu, which is made to deposit on the thin metal film.
Electrochemical etching to form porous silicon on n+ p+ diffused is carrieo out by using a cunent density of 2-30 mA / cm2 in a HF-bath of 12-48% concentration for a duration varying between 1 and 5 minutes, using a guard plate type electrode.
The invention will be further described with the help of the following illustration Example which is given by way of illustration and not by way of limitation,
Example
A novel porous silicon based large area patterned display device fabricated according to the procedure enumerated before and also in the flow-sheet diagram of Fig 3 ofthe drawings has the following features.
i) SiO2on Si - wafer ~ -0.1 m
ii) Width of thin metal layer (of Ag) = - 30nm
iii) Thickness of metal grid on
thin layer of Ag = -500 run
iv) Dimensions of contact wire
Thickness * 500 nm
Width * -0.5 mm
v) Compact pad * ~ 7

vi) Contact width = - 0.1 mm
vii) Metal grid length = 3mm
viii) Width of SiO2, nSi
and pfSi layers = -1 urn
IX) Width of the device = -300 m
x) Dimensions of each segment = 2 cm long x 0.5 cm wide
xi) On-set voltage and current = In the ranges of 5 V an.ri 50 mA/cm2,
respectively.
As indicated earlier the advantages and special features of the device of the present invention may be summarized as follows :
i) The device can be made of a large area, e.g. 80 cm2,
ii) It emits light in the yellow region, which renders it visible even in foggy conditions.
iii) Light emitted from the device is perceptible to the eye in dark and also in diffused light.
iv) It can be used for alphanumeric digital display in any instrur:;en;
v) The display and its driver/logic circuit can be accommodated on n single wafer to fabricated a system on chip (SOC).
vi) It is highly compatible with well-established Si-IC technology and circuits for its low operating voltage and current.
While the invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without deviating or departing from the spirit and scope of this invention. Thus the disclosure contained herein includes within its ambit the obvious equivalent and substitates as well.
Having described the invention in detail with particular reference to the example given above and also the accompanying drawings, it will now be more specifically defined b> means of claims appended hereafter.
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I claim
1. A process for preparing a double layer metallized unit with porous silicon to produce
large area patterned display device, which comprises :-
i) selecting a p-type wafer of (100) or (111) configuration as the starting material,
ii) doping a selected part of the said wafer with boron, followed by doping with phosphorous to form n+p+junction;
iii) preparing porous silicon in a formation bath of 12-48% HF and CH3OH with suitable electrode(s) like graphite to form highly uniform porous silicon layer,
iv) drying the thus formed porous silicon in a suitable liquid such as herein described to prevent surface cracking;
v) oxidising the dried porous silicon layer by 10 vol H2O2 under optimum conditions such as herein described to stabilize the system;
vi) depositing a thin mete4 layer of metal like Al, In or Ag by evaporation on top of the porous silicon strata;
vii) forming another layer of metallic substance like Cu, Ag, Au or Ai having grid structure with optimum grid and spacing on top of said thin metal layer by evaporation to form a double layer metal contact;
viii) heat treating the material from step (vii) at around 450°-500° for around 60 teem As under inert atmosphere of nitrogen and
ix) providing contact wire from each segment leading to contact pad for achieving unllbi'ni light emission from each one of said segments.
2, A process as claimed in Claim 1, wherein formation of porous silicon is conducted in a balh of 12 - 4$% solution of HF and CH3OH using a current density of 2-30 mA / cm2 for around 1-5 minutes employing guard type plate electrode(s).
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3. A process as claimed in Claim 1, wherein initial oxidation of Si-wafer is conducted under wet condition at a temperature in the vicinity of 1000°C and for a period of around 1 hour.
A. A process as claimed in Claims I to 3, wherein the first thin layer of metallic silver is
formed by vacuum evaporation technique and the second layer of metallic silver, gold or
aluminium isdeposlted by photolithography followed by vacuum evaporation.
5. A process as claimed in Claims 1 to 4, wherein each segment measures 2cm long x 0.5
cm wide and the device may is made to cover a large area of 80 cm".
6. A process as claimed in Claims I to 5, wherein the display device and its driver circuit is
accommodated on a single wafer to obtain a system on chip (SOC).
7. A process as claimed in Claims 1 to 3, wherein the thin metal layer is of silver and
another melnl layer with grid structure deposited thereon is silver, gold or aluminium resulting in
the formation of a double layer metal contact.
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8. A process for preparing a double layer metallized unit with porous silicon to produce
large area patterned display device, substantially as hereinbefore described with reference to the
illustrative example and accompanying drawings.



Porous Silicon (PS) has been used in devices meant for light emission but the results are far from satisfactory mainly due to diffused and non-uniform nature of emitted light and in some cases the onset voltage and current are very high.
The present invention aims at overcoming the above drawbacks and provides a process for preparing a double layer metallized unit with porous silicon to produce large area patterned display device, which comprises
i) selecting a p-type wafer of (100) or (111) configuration as the starting material;
ii) doping a selected part of the said wafer with boron, followed by-doping with phosphorous to form n+ p+ junction;
iii) preparing porous silicon in a formation bath of 12-48% HF and CH3OH with suitable electrode(s) like graphite to form highly
uniform porous silicon layer;
iv) drying the thus formed porous silicon in a suitable liquid such as herein described to prevent surface cracking;
v) oxidising the dried porous silicon layer by 10 vol H202 under
optimum conditions such as herein described to stabilize the system;
vi) depositing a thin layer (2) of metal like Al, In or Au by evaporation on top of the porous silicon strata (1);
vii) forming another layer of metallic substance like Cu, Ag, Au, or Al having grid structure with optimum grid and spacing (3) on top of said thin metal layer by evaporation to form a double layer metal contact;
viii) heat treating the material from step (vii) at around 450 - 500 for around 60 seconds under inert atmosphere of nitrogen and
(ix) providing contact wire (4) from each segment leading to contact pad (5) for achieving uniform light emission from each one of daid segments.




Documents:

00388-kol-2003-abstract.pdf

00388-kol-2003-assignment.pdf

00388-kol-2003-claims.pdf

00388-kol-2003-correspondence.pdf

00388-kol-2003-description(complete).pdf

00388-kol-2003-drawings.pdf

00388-kol-2003-form-1.pdf

00388-kol-2003-form-18.pdf

00388-kol-2003-form-2.pdf

00388-kol-2003-form-3.pdf

00388-kol-2003-letters patent.pdf

00388-kol-2003-p.a.pdf

388-kol-2003-granted-abstract.pdf

388-kol-2003-granted-claims.pdf

388-kol-2003-granted-description (complete).pdf

388-kol-2003-granted-drawings.pdf

388-kol-2003-granted-form 2.pdf

388-kol-2003-granted-specification.pdf


Patent Number 208768
Indian Patent Application Number 388/KOL/2003
PG Journal Number 32/2007
Publication Date 10-Aug-2007
Grant Date 09-Aug-2007
Date of Filing 15-Jul-2003
Name of Patentee PROF. HIRANMAY SAHA
Applicant Address IC DESIGN AND FABRICATION CENTRE, DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, JADAVPUR UNIVERSITY, KOLKATA-700 032, WEST BENGAL, INDIA.
Inventors:
# Inventor's Name Inventor's Address
1 DR. SYED MINHAZ HOSSAIN IC DESIGN AND FABRICATION CENTRE, DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, JADAVPUR UNIVERSITY, KOLKATA-700 032, WEST BENGAL, INDIA.
2 PROF. HIRANMAY SAHA -DO-
PCT International Classification Number H 01 L 33/00
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA