Title of Invention

PRINT ENGINE/CONTROLLER AND PRINTHEAD INTERFACE CHIP INCORPORATING THE ENGINE/CONTROLLER

Abstract

A print engine/controller suited to use with a drop on demand print head. The print engine/controller works with compressed page data having both JPEG contone image layers and a bi-level image plane compressed using a Group 4 facsimile protocol. It receives compressed image plane's and effects expansion and printing in a pipeline fashion. It consists of a high speed serial interface (27) (such as a standard IEEE 1394 interface), a standard JPEG decoder (28), a standard Group 4 Fax decoder (39), a halftoner/compositor unit (29), a tag encoder (30) by which to place infrared tags into a printed page, a line loader/formatter unit 31 feeding an interface 32 to the print head (33). The decoders (28, 39) and encoder (30) are buffered to the halftoner/compositor (29).

Full Text

PRINT ENGINE/CONTROLLER AND PRINTHEAD INTERFACE CHIP INCORPORATING THE ENGINE/CONTROLLER FIELD OF THE INVENTION The invention relates to a print engine/controller (PEC) suitable for use with a range of printer products. The invention further relates to a print engine/controller implemented in a print head interface chip. BACKGROUND OF THE INVENTION A range of printer types have evolved wherein an image is constructed from ink selectively applied to a page in dot format. In US patent number 6045710 titled 'Self-aligned construction and manufacturing process for monolithic print heads* to the inventor Kii Silver brook there is set out an assessment of the prior art to drop on demand printers along with its manufacturing process. A micrpelectomechanical drop on denude print head hereafter referred to as a Member print head has been described in co-pending Intemarional Patent Applications filed simultaneously to the present application and hereby incorporated by cross reference: The Member print head is developed from print head segments that axe capable of producing, for example, 1600 dpi bi-level dots of liquid ink across the full width of a page. Dots are easily produced in isolation, allowing dispersed-dot dithering to be exploited to its fullest Color planes might be printed in perfect registration. allowing ideal dot-on-dot printing. The print head enables high-speed printing using microelectromechanical ink drop technology. Various methods, systems and apparatus relating to the present invention are disclosed in the following cop ending applications filed by die applicant or assignee of the present invention simultaneously with the present • application: NPAOOl, NPA002, NPA004, NPA005, NPA006, NPA007, NPA008. NPA009, NPAOIO, NPA012, NPA016. NPA017, NPA018, NPA019, NPA020, NPA021, NPA030, NPA035, NPA048, NPA075, NPAOOl, NPB002, NPK002, NPK003, NPK004, NPK005, NPMOOl. NPM002, NPM003. NPM004, NPP005, NPP006. NPP016, NPP017, NPNOOl, NPPOOl, NPP003, NPP007. NPP008, NPP018, NPSQOI. NPS003. NPS020. NPTOOl, NPT002, NPT003. NPT004, NPXOQU NPX003, NPX008, NPXOll, NPXOU, NPX016, U52. UM52, MJIO, MJ11. MJ12. MJ13, MJ14, MJ15. MJ34, MJ47. MJ58, MJ62, MJ63, MJ64, MJ65, MJ66, PAK04, PAK05, PAK06, PAK07. PAK08, PECOl. PEC02. PEC03, PPOl, PP02, PP03, PP04, PP07, PP08, PP09. PPIO. PPU. PP12, PP13, PPU, PP15, PP16, and PP17. The disclosures of these co-pending applications are incorporated herein by cross-reference. Each application is temporarily identified by its docket number. This will be replaced by the corresponding PCT Application Number when available. Performance of a print head such as the above is dictated by its engine/controller. High-speed printing is a matter of development of both the print head and its engine/controller. A page wide print head enabled by the above technology needs an engine/controller capable of feeding it high rates of drop control signals. A typical page layout may contain a mixture of images, graphics and text Because of the page-width nature of the above microelectromechanical print head, each page can be printed at a constant speed to avoid creating visible artifacts. This means that the printing speed need not be varied to match the input data rate. Document rasterizadon and document printing can be decoupled. To ensure the print head has a constant supply of data, a page should not be printed until it is fully rasterize. Ideally rasterization should be able to run ahead of the printer when rasterizing simple pages, buying time to rasterize more complex pages. The engine/controller determines the degree to which these functions might be realised. More speed at the print head depends on development of both print head and its engine/controller. The print engine/controller architecture needs to be designed to push large volumes of data to the print head at high speed. SUMMARY OF THE INVENTION In one form the invention resides in a print engine/controller comprising: a contone image decoder; a bi-level compression decoder, and a hair-toner/compositor and print head interface. The print engine/controller provides the final steps for producing a page from compressed page data appropriately foramen for it by a computer or print distribution system, the steps being: expanding the page inane, dithering the contone layer, composting the black layer over the contone layer, adding infrared tags to the infrared layer, and sending the resultant image to the print head. The print engine/controller preferably uses a high speed serial interface at which to receive compressed page data. Contone image planes are decoded by a JPEG decoder and they are scaled in the halftoner/compositor under control of a margin unit A Group 4 facsimile decoder decodes the bi-level image plane and it also is scaled in the halftone/compositor under control of die margin unit Optionally an infrared tag encoder serves to produce an infrared * image plane to place infrared ink printed tags into a printed page. The halftone/compositor includes a dither matrix access unit to supply dither data torn the compressed page data by which to dither the contone image plane. The invention further includes a print engine/controller chip to interface with an ink drop print head comprising an interface at which to receive compressed page data, a contone image decoder to decode any continuous tone image planes in the received compressed page data, a bi-level decoder to decode any bi-level image planes and dither day in the received compressed page data, a half-toner/compositor to composite any bi-level image plane over any continuous tone image plane, and a print head driver to output the composite to a print head. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating data flow and .the functions performed by the print engine controller. FIG. 2 shows the print engine controller in the context of the overall printer system architecture. FIG. 3 illustrates the print engine controller architecture. FIG. 4 illustrates die external interfaces to die halftoner/ unit (HCU) of FIG. 3. FIG. S IS a diagram showing internal circuitry to the HCU of FIG. 4. FIG. 6 shows a block diagram illustrating the process within the dot merger unit of FIG. S. RG. 7 shows a diagram illustrating the process widen the dot reorganization unit of FIG. 5. FIG. 8 shows a diagram illustrating the process within the line loader/format unit (LLFU) of FIG. 5. FIG. 9 is a diagram showing internal circuitry to generate color data in the LLFU of RG. 8. FIGs. 10 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typically 12 inch print head width is controlled by one or more PECs, as described below, to allow full-bleed printing of both A4 and Letter pages. Six channels of colored ink are the expected maximum in die present printing environment, these being: • CMY, for regular color printing. • K. for black text and other black printing. • IR (infrared), for tag-enabled applications. • F (fixative), to enable printing at high speed. Because the printer is to be capable of fast printing, a fixative will be required to enable the ink to dry before the next page has completed printing at higher speeds. Otherwise the pages might bleed on each other. In lower speed printing environment the fixative will not be required. A PEC might be built in a single chip to interface with a print head. It will contain four basic levels of functionality: • receiving compressed pages via a serial interface such as IEEE 1394 • a print engine for producing a page from a compressed form. The print engine functionality includes expanding the page image, dithering the contone layer, composting the black layer over the contone layer, optionally adding infrared tags, and sending the resultant image to the print head. « a print controller for controlling the print head and stepper motors. • two standard low-speed serial ports for communication with the two QA chips. Note that there must be two ports and not a single port to ensure strong security during the authentication procedure. In Figure 1 is seen the flow of data to send a document from computer system to printed page. A document is received at U and loaded to memory buffer 12 wherein page layouts may be ejected and any required objects might be added. Pages from memory 12 are rasterized at 13 and compressed at 14 prior to transmission to the print engine controller 10. Pages are received as compressed page images within the print engine controller 10 into a memory buffer IS, from which they are fed to a page expander 16 wherein page images are retrieved. Any requisite dithering might be applied to any contone layer at 17. Any black bi-level layer might. be composite over the contone layer at 18 together with any inward tags at 19. The consisted page data is printed at 20 to produce page 2L The print engine/controller takes the compressed page image and starts the page expansion and printing in pipeline fashion. Page expansion and printing is preferably pipelined because it is impractical to store a sizable bi4evel CMYK+IR page image in men The first stage of the pipeline expands a JPEG-compressed contone CMYK layer (see below), expands a Group 4 Fax-compressed bi-level dither matrix selection map (sec below), and expands a Croup 4 Fax-compressed bi-level black layer (see below), all in parallel. In parallel with this, the tag encoder encodes bi-level IR tag data from the compressed page image. The second stage dithers the contone CMYK layer using a dither matrix selected by the dither matrix select map, composites the bi-level black layer over the resulting bi-level K layer and adds the IR layer to the page. A fixative layer is also generated at each dot position wherever there is a need in any of C, M. Y, K, or IR channels. The last stage prints the bi-level CMYK+IR data through the print head via a print head interface (see below). In FIG. 2 is seen how the print engine/controller 10 fits within the overall printer system architecture. The various components of the printer system might include • a Prim Engine/Controller (PEC). A PEC chip 10, or chips, is responsible for receiving the compressed page images for storage in a memory buffer 24. data synchronize the various portions of the PEC chip during a print • provide a means of interfacing with external data requests (programming registers etc.) • provide a means of interfacing with print head segment low-speed data requests (such as reading the characterization vectors and writing pulse profiles) • provide a means of writing the portrait and landscape tag structures to external DRAM Since all of the image processing is performed by dedicated hardware, the CPU docs not have to process pixels. As a result, Ac CPU can be extremely simple. A wide variety of CPU known cores are suitable: it can be any processor core with sufficient processing power to perform the required calculations and control functions fast enough. An example of a suitable core is a Philips 8051 micro-controller running at about 1 MHz. Associated with the CPU core 3S may be a program ROM and a small program scratch RAM. The CPU communicates with the other units within the PEC chip via memory-mapped I/O. Particular address ranges may map to particular units, and within each range, to particular registers within that particular unit. This includes the serial 36 and parallel 91 interfaces. A small program flash ROM may be incorporated into the PEC chip. Its size depends on the CPU chosen, but should not be more than 8KB. Likewise, a small scratch RAM area can be incorporated into the PEC chip. Since the program code does not have to manipulate images, there is no need for a large scratch area. The RAM size depends on die CPU chosen (e.g. stack mechanisms, subroutine calling conventions, register sizes etc.), but should not be more than about 2 KB. A PEC chip using the above referenced segment based page wide print head can reproduce black at a full dot resolution (typically 16(30 dpi), but reproduces contone color at a somewhat lower resolution using half toning. The page description is therefore divided into a black bi-level layer and a contone layer. The black bi-level layer is defined to composite aver the contone layer. The black bi-level layer consists of a bitmap containing a 1 -bit opacity for each pixel. This black layer matte has a resolution ^at is an integer factor of the printer's dot resdlution. The highest supported resolution is 1600 dpi, i.e. the printer's full dot resolution. The contone layer consists of a bitmap containing a 32-bit CMYK color for each pixel, where K is optional. This contone image has a resolution that is an integer factor of the printer's dot resolution The highest supported resolution is 320 pip over 12 inches for a single PEC, i.e. one-fifth the printer's dot resolution. For higher contone resolutions multiple PECs are required, wide each PEC producing an strip of the output peg. The contone resolution is also typically an integer factor of the black bi-level resolution, to simplify calculations in die Rips. This is not a requirement, however. The black bi-level layer and die contone layer are both in compressed form for efficient storage in the printer's internal memory. [n FIG. 3 is seen the print engine architecture. The print engine's page expansion and printing pipeline consists of a Kith speed serial interface 27 (such as a standard IEEE 1394 interface), a standard JPEG decoder 28, a standard Group 4 Fax decoder, a custom halftoner/compositor unit 29, a custom tag encoder 30, a line loader/formatter unit 31, and a custom interface 32 to the print head 33. The decoders 28.88 and encoder 30 are buffered to the halftoner/compositor 29. The tag encoder 30 establishes an infrared tag or tags to a page according to protocols dependent on what uses might be made of the page and the actual content of a tag is not the subject of the present invention. The print engine works in a double buffered way. One page is loaded into DRAM 34 via DRAM interface 89 and day bus 90 from the high speed serial interface 27 while the previously loaded page is read from DRAM 34 and passed drought the print engine pipeline. Once the page has finished printing, dine the page just loaded becomes the page being printed, and a new page is loaded via the high-speed serial interface 27. At the first stage the pipeline expands any JPEG-compressed contone (CMYK) layer, and expands any of two Group 4 Fax-compressed bi-level data streams. The two streams are the black layer (although the PEC is actually color agnostic and this bi-Level layer can be directed to any of the output inks), and a matte for selecting between dither matrices for contone dithering (see below). At the second stage, in parallel with the first, is encoded any tags for later rendering in cither IR or black ink. Finally the third stage dithers the contone layer, and composites position tags and the bi-level spot layer over the resulting bi-level diced layer. The data stream is ideally adjusted to create smooth transitions across overlapping segments in the print head and ideally it is adjusted to compensate for dead nozzles in die print head. Up to 6 channels of bi-level data are produced from this stage. Note that not all 6 channels may be present on the print head. For example, the print head may be CMY only, with K pushed into the CMY channels and IR ignored. Alternatively, the poison tags may be printed in K if IR ink is not available (or for testing purposes). The resultant bi-level CMYK-IR dot-data is buffered and formatted for printing on the print head 33 via a set of line buffoon (see below). The majority of these line buffers might be ideally stored on the off-chip DRAM 34. The final stage prints the 6 chaimels of bi-level dot data via the print head interface 32. Compression is used in a priding system that employs the PEC. This is to reduce bandwidth requirements between a host and PEC, as well as to reduce memory requirements for page storage. At 267 pip, a Letter page of contone CMYK data has a size of 25MB. Using lossy contone compression algorithms such as JPEG (see below), contone images compress with a ratio up to 10:1 without noticeable loss of quality, giving a compressed page size of 2.5MB. At 800 dpi, a Letter page of bi-level data has a size of 7MB. Coherent data such as text compresses very well. Using lossless bi-level compression algorithms such as Group 4 Facsimile (see below), ten-point text compresses with a ratio of about 10:1, giving a compressed page size of 0.8MB. Once dithered, a page of CMYK contone image data consists of 114MB of bi-level data. The two-layer compressed page image format described below exploits the relative strengths of lossy JPEG contone image compression and lossless bi-level text . The fonnat is compact enough to be storage-efficient, and simple enough to allow straightforward real-time expansion during priding. Since text and images normally don't overlap, the normal worst-case page image size is 2.5MB (i.e. image only), while the normal best-case page image size is 0.8MB (i.e. text only). The absolute worst-case page intake size is 33MB ( , text over image). Assuming a quaver of an average page contains images, the average page image size is 1.2MB. A Group 3 Facsimile compression algorithm (see ANSI/EIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) can be used to losslessly compresses bi-level data for transmission over slow and noisy telephone lines. The bi-level data referents scammed black text and graphics on a white background, and the algorithm is tuned for this class of images (it is explicidy not tuned, for example, for halfioned bi-level images). The ID Group 3 algoid runlength-encodes each scanline and then Huffman-encodes the resulting runlengths. Runlengths in the range 0 to 63 are coded with terminating codes. Runlengths in the range 64 to 2623 are coded with make-up codes, each representing a multiple of 64, followed by a terminating code. Runlengths exceeding 2623 axe coded with multiple make-up codes followed by a terminating code. The Huffman tables are fixed, but are separately tuned for black and white nines (except for make-up codes above 1728, which are common). When possible, the 2D Group 3 algorithm encodes a scanline as a set of short edge deltas (0, ±1, ±2, ±3) with reference to the previous scanline. The delta symbols are entropy-encoded (so that the zero delta symbol is only one bit long etc.) Edges within a 2D-encoded line diet can't be delta-encoded are runlength-encoded, and are identified by a prefix. ID- and 2D-encoded lines are marked different. 10-encoded likes are generated at regular Intervals, whether actually required or not, to ensure that the decoder can recover from line noise with maximal image degradation. 2D Group 3 achieves compression ratios of up to 6:1 (see Urban, S J., Review of standards for electronic imaging for facsimile systems". Journal of Electronic Imaging, Vol.l(l), January 1992, pp.5-21). A Group 4 Facsimile algorithm (see ANSI/EIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) losslessly compresses bi-level data for transmission over error-free communications lines (i.e. the lines are truly error-free, or error-correction is done at a lower protocol level). The Group 4 algorithm is based on the 2D Group 3 aJgorithau with the essential modification that since transmission is assumed to be error-free, ID-concoct lines are no longer generated at regular intervals as an aid to error-recovery. Group 4 achieves compression ratios ranging from 20:1 to 60:1 for the CCITT set of test images. The design goals and performance of the Group 4 compression algorithm qualify it as a compression algorithm for the bi-level layers. However, its Huffman tables are tuned to a lower scanning resolution (100-400 dpi), and it encodes runlcngths exceeding 2623 awkwardly. At 800 dpi, our maximum runlcngth is currency 6400. Although a Group 4 decoder core would be available for use in PEC. it might not handle runlcngths exceeding those normally encountered in 400 dpi facsimile applications, and so would require modification. The (typically 1600 dpi) black layer is losslessly compressed using G4Fax at atypical compression ratio exceeding 10:1. A (typically 320dpi) dither matrix select layer, which matches the canton color layer, is losslessly compressed using G4Fax at a typical compression ratio exceeding 50:1. The Group 4 Fax (G4 Fax) decoder is responsible for decompressing bi-level data. Bi-level data is limited to a single spot color (typically black for text and line graphics), and a dither matrix select built-up for use in subsequent dithering of the contone data (decompressed by the JPEG decoder). The input to the G4 Fax decoder is 2 planes of bi-level data, read from the external DRAM. The output of the G4 Fax decoder is 2 planes of decompressed bi-level data. The decompressed bi-level data is sent to the Haiftoncr/Composiior Unit (HCU) for the next stage in the printing pipeline. Two bi-level buffers provides the means for transferring the bi-level data between the C4 Fax decoder and the HCU. Each decompressed bi-level layer is output to two line buffers. Each buffer is capable of holding a full 12 inch line of dots at the expected maximum resolution. Having two line buffers allows one line to be read by the HCU while the other line is being written to by the (34 Fax decoder. This is hnportant because a single bi-level line is typically less than 1600 dpi, and must therefore be expanded in both the dot and line dimensions. If the buffering were less than a full line, the G4 Fax decoder would have to decode the same line multiple times * once for each output 600dpi dotline. Spot color 1 is designed to allow high resolution dot data for a single color plane of the output image. While the contone layers provide adequate resolution for images, spot color 1 is targeted at applications such as text and line graphics (typically black). When used as text and line graphics, the typical compression radon exceeds 10:1. Spot color 1 allows variable resolution up to 1600dpi for maximum print quality. Each of the two line buffers is therefore total 2400 bytes (12 inches x 1600 dpi = 19,200 bits). The resolution of the dither matrix select map should ideally match the contone resolution. Consequently each of the two line buffers is therefore 480 bytes (3840 bits), capable of storing 12 inches at 320 dpi. When the map matches the contone resolutioxi, the typical compression ratio exceeds 50:1. In order to provide support for: • 800 dpi spot color 1 layer (typically black) • 320 dpi dither matrix select layer the decompression bandwidth requirements are 9.05 MB/sec for 1 page per second performance (regardless of whether the page width is 12 inches or 8.5 inches), and 20 MB/sec and 14.2 MB/sec for 12 inch and 8.5 inch page widths respectively during maximum printer speed performance (30,000 lines per second). Given that the decompressed data is output to a line buffer, the G4 Fax decoder can readily decompress a line from each of the outputs one at a time. The G4 Fax decoder is fed directly from the main memory via die DRAM interface. The amount of compression determines the bandwidth requirements to the external DRAM. Since G4 Fax is lossless, the complexity of the image impacts on the amount of data and hence the bandwidth, typically an 800 dpi black text/graphics layer exceeds 10:1 compression, so the bandwidth required to print 1 page per second is 0.78 MB/sec. Similarly, a typical 320 dpi dither select matrix compresses at more than 50:1, resulting in a 0.025 MB/sec bandwidth. The fastest printing speed configuration of 320 dpi for dither select matrix and 800 dpi for spot color I requires bandwidth of 1.72 MB/scc and 0.056 MB/sac respectively. Atotalbandwidthof 2 MB/sac should therefore be more than enough for the DRAM bandwidth. The G4 Fax decoding functionality is implemented by means of a G4 Fax Decoder core. A wide variety of G4Fax Decoder cores arc suitable: it can be any core with sufficient processing power to perform the required calculations and control fictions fast enough. It must be capable of handling nmlengths exceeding those normally encountered ia400 dpi facsimile applications, and so may require modification. A JPEG compression algorithm (see ISO/IEC 19018-1:1994. Information technology - Digital compression and coding of continuous-tone still images: Requirements and guidelines, .1994) glossily compresses a contone image at a specified quality level. It introduces perceptible image degradation at compression ratios below 5:1, and negligible image degradation at compression ratios below 10:1 (see Wallace, G.K., *The JPEG Still Picture Compression Standard", Communications of the ACM. Vol.34, No.4, April 1991, pp.30-44). JPEG typically Srst transforms the image into a color space that separates luminance and chrominance into separate color channels. This allows Chef chrominance chaimels to be sub sampled without appreciable toss because of the human visual system's relatively greater sensitivity to lucuciance than chrominance. After this first step, each color channel is coursed separately. The image is divided into 8x8 pixel blocks. Each block is then transformed into the frequency domain via a discrete cosine transform (DCT). This transformation has &e effect of concentrating image energy in relatively lower-frequency coefficients, which allows higher-frequency coefficients to be more crudely quintile. This quandzadon Is the principal source of compression in JPEG. Further compression is achieved by ordering coefficients by frequency to maximize the likelihood of adjacent zero coefficients, and then runlength-encoding runs of zeroes. Finally, the runlengths and non-zero frequency coefficients are entropy coded. Decompression is the inverse process of compression. The CMYK (or CMY) contone layer is compressed to a planar color JPEG byte stream. If luminance/chrominance separation is deemed necessary, either for the purposes of table sharing or for chrominance sub sampling, then CMYK is converted to YCrCb and Cr and Cbz are duly sub sampled. The JPEG byte stream is complete and self-contained. It contains all data required for decompression including unitization and Ruffian tables. The JPEG decoder is responsible for performing the on-the-fly decompression of the contone data layer. The input to the JPEG decoder is up to 4 planes of contone data. This mil typically be 3 planes, representing a CMY contone image, or 4 planes representing a CMYK contone image. Each color plane can be in a different resolution, although typically all color planes will be the same resolution. The contone layers are read from the external DRAM. The output of the JPEG decoder is the decompressed contone data, separated into planes. The decompressed contone image is sent to the halftone/compositor unit (HCU) 29 for the next stage in the printing pipeline. The 4-plane contone buffer provides the means for transferring the contone data between die JPEG decoder and the HCU 29. Each color plane of the decompressed contone data is output to a set of two line buffers (see below). Each line buffer is 3840 bytes, and is therefore capable of holding 12 inches of a single color plane's pixels at 320 ppi. The line buffering allows one line buck to be read by the HCU while the other line buffer is being written to by the JPEG decoder. This is important because a single contone line is typically less than 1600 ppi, and must therefore be expanded In both the dot and line dimensions. If the buffering were less than a full line, the JPEG decoder would have to decode the same line multiple times - once for each output 600dpi dotline. Although a variety of resolutions is supported, there is a tradeoff between the resolution and available bandwidth. As resolution and number of colors increase, bandwidth requirements also increase. In addition, &e number of segments being targeted by the PEC dips also affects the bandwidth and possible resolutions. Note that since the contone image is processed in a planar format, each color plane can be stored at a different resolution (for example CMY may be a higher resolution than the K plane). The highest supported contone resolution is !600ppi (matching the printer's full dot resolution). However there is only enough output line buffer memory to hold enough conionc pixels for a 320ppi line of lend 12 inches. If the full 12 inches of output was required at higher commune resolution, multiple PEC chips would be required, although it should be noted that the final output on the printer will still only be bi-level. With support for 4 colors at 320ppi» die decompression output bandwidth requirements axe 40 MB/sec for 1 page per second performance (regardless of whether the page width is 12 inches or 8.5 inches), and 88 MB/sec and 64 MB/sec for 12 inch and 8.5 inch page widths respectively during maximum printer speed performance (30.000 lines per second). The JPEG decoder is fed directly from the main memory via the DRAM interface. The amount of compression determines the bandwidth requirements to the external DRAM. M the level pf compression increases, die bandwidth decreases, but the quality of the final output image can also decrease. The DRAM bandwidth for a single color plane can be readily calculated by applying the compression factor to the output bandwidth. For example, a single color plane at 320 ppi with a compression factor of 10:1 requires I MB/sec access to DRAM to produce a single page per second. The JPEG functionality is implemented by means of a JPEG core. A wide variety of JPEG cores are suitable: it can be any JPEG core with sufficient processing power to perform the required calculations and control functions fast enough. For example, the BTG X-Match core has decompression speeds up to 140 Mbytes/sec. which allows decompression of 4 color planes at contone resolutions up to 400ppi for the maximum printer speed (30,000 lines at 1600dpi per second), and Soppy for I page/sec printer speed. Note that the core needs to oily support decompression, reducing the requirements that are imposed by more generalized JPEG compression/decompression cores. The size of the core is expected to be no more than 100,000 gates. Given that the decotnpressed data is output to a tine buffer, the JPEG decoder can readily decompress an entire line for each of the color planes one at a UM, thus saving on context switching during a line and simplifying the control of die JPEG decoder. 4 contexts must’ be kept (I context for each color plane), and includes current address in die external DRAM as well as appropriate JPEG decoding parameters In FIG. 4 die haiftoner/compositor unit (HCU) 29 combines the functions of half toning the contone (typically CMYK) layer to a bi*level version of the same, and composting die spotl bi-level layer over the appropriate halftone contone layer(s). If diere is no K ink in the printer, the HCU 29 is able to map K to CMY dots as appropriate. It also selects between two deduct matrices on a pixel by pixel basis, based on the corresponding value in the dither matrix select map. The input to the HCU 29 is an expanded contone layer (from the JPEG decoder imit) through buffer 37, an expanded bi-level spotl layer through buffer 38. an expanded dither-matrix-select bitmap at typically the same resolution as the contone layer through buffer 39, and tag data at fitly dot resolution through buffer 40. The HCU 29 uses up to two Didier matrices, read from the external DRAM 34. The output from the HCU 29 to the line loader/format unit (LLFU) at 41 is a set of printer resolution bi-level image lines in up to 6 color planes. Typically, the contone layer is CMYK or CMY. and die bi-level spotl layer is K. In FIG. S is seen the HCU in greater detail. Once started, die HCU proceeds until it detects an end-of-page condition, or until it is explicidy stopped via its control register. The; first task of the HCU is to scale, in the respective scale units such as the scale unit 43, all data, received in the buffer planes such as 42, to printer resolution both horizontally and vertically. The scale unit provides a means of scaling contone or bi-level data to printer resolution body horizontally and vertically. Scaling is achieved by replicating a data value an integer number of dames in both dimensions. Processes by which to scale data will be familiar to those skilled in the art. Two control bits are provided to die scale unit 43 by the margin unit 57: advance dot and advance line. The advance dot bit allows the state machine to generate multiple instances of the same dot data (useful for page margins and creating dot data for overlapping segments in the print head). The adyance line bit allows the state machine to control when a particular line of dots has been finished, thereby allowing truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-link logic. The input to the scale unit is a full line buffer. The line is used scale factor limes to effect vertical up-scaling via line replication, and within each line, each value is used scale factor times to effect horizontal up-scaling via pixel replication. Once the input line has been used scam factor times (the advance line bit has been set scale factor times), the input buffer select bit of the address is toggled (double buffering). The logic for the scale unit is the same for the 8-bit and 1-bit case, since the scale unit only generates addresses. Since each of the conionc layers can be a different resolution, they are scaled independently. The bi-level spotl layer at buffer 45 and the cutch matrix select layer at buffer 46 also need to be scaled. The bi-level tag dual at buffer 47 is established at the correct resolution and does not need to be scaled. The scaled-up dither matrix select bit is used by the dither matrix access unit 48 to select a single 8-bit value from the two dither matrices. The 8-bit value is output to the 4 comparator 44, and 49 to 51, which simply compare it 8-bit contone value. The generation of an actual dither matrix is dependent on the structure of the print head and the general processes by which to generate one will be familiar to those skilled in the art If the contone value is greater than or equal-to the 8-bit dither matrix value a 1 is output. If not, then ago is output These bits are then all Ended at 52 to 56 with an in Page bit from the margin unit 57 (whether or not the particular dot is inside the printable area of the page). The final stage in the HCU is the composting stage. For each of the 6 output layers there is a single dot merger unit, such as unit 58, each with 6 inputs. The single output bit from each dot merger unit is a combination of any or al I of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing purposes), black to be unnerved into cyan, magenta and yellow (if no black ink is present in the print head), and tag dot data to be placed in a visible plane. A fixative color plane can also be readily generated. The dot rear unit (DRU) 59 is responsible for taking the generated dot stream for a given color plane and organizing it into 32-bit quantities so that the output is in segment order, and in dot order within segments. Minimal reordering is required due to the fact that dots for overlapping segments are not generated in segment order. Two control bits are provided to the scale units by the margin unit 57: advance dot and advance line. The advance dot bit allows the state machine to generate multiple instances of the same dot data (useful for page margins and creating dot data for overlapping segments in the print head). The advance line bit allows the state machine to control when a particular line of dots has been finished, thereby allowing truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-line logic. The comparator unit contains a simple 8-bit ^'greater-than-or-equal** comparator. It is used to determine whether the 8-bit contone value is greater than or equal to the 8-bit dither matrix value. As such, the comparator unit takes two 8-bit inputs and produces a single 1-bit output In FIG. 6 is seen more detail of the dot merger unit It provides a means of mapping the bi-level doddered data, the spotl color, and the tag data to output inks in the actual print head. Each dot merger unit takes 6 1-bit inputs and produces a single bit output that represents the output dot for that col6r plane. The output bit at 60 is a combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing purposes), black to be merged into cyan, magenta and yellow (in the case of no black ink in the print head), and tag dot data to be placed in a visible plane. An output for fixative can readily be generated by simply combining all of the input bits. The dot merger unit contains a 6-bit Color Mask register 61 that is used as a mask against the 6 input bits. Each of the input bits is Landed with the corresponding ColorMask register bit, and the resultant 6 bits are then Rock together to form the final output bit In FIG. 7 is seen the dot report unit (DRU) which is responsible for taking the generated dot stream for a given valid, depending on how many colors are actually used in the print head. The physical placement of firing nozzles on the print head referenced above, nozzles in two offset . means that odd and even dots of the same color are for two different lines. The even dots are for line L, and the odd dots are for line L-2. In Addison. there is a number of lines between the dots of one color and the dots of another. Since the 6 color planes for Chef same dot position are calculated at one time by the HCU. there is a need to delay the dot data for each of the color planes until the same dot is positioned under the appropriate color nozzle The size of each buffer line depends on the width of the print head. Since a single PEC generates dots for up to 15 print head segment. a single odd or even buffer line is therefore 15 sets of 640 dots, for a total of 9600 bits (1200 bytes). For example, the buffers required for color 6 odd dots totals almost AS KBytes. The entire set of requisite buffers might be provided on the PEC chip when manufacturing techniques are capable. Otherwise, the buffers for colors 2 onward may be stored in external DRAM. This enables the PEC to be valid even though the distance between color planes may change in the future. It is trivial to keep the even dots for color 1 on PEC, since everything is printed relative to that particular dot line (no additional line buffers are needed). In addition, the 2 half-lines required for buffering color 1 odd dots saves substantial DRAM bandwidth. The various line buffers (on chip and in DRAM) need to be pre-loaded with all Os before the page is printed so that it has clean edges. The end of the page is generated automatically by die HCU so it will have a clean edge. In FIG 10 is seen a block diagram for Color N OESplit (see Exploit 70 of FIG. 9), and the block diagram for each of the two buffers £ and F, 71.72 in FIG. 9 can be found in FIGs. 10 and 11. Buffer £F is a double buffered mechanism for transferring data to the print head Interface (PHI) 32 in FIG. 3. Buffers £ and F therefore have identical structures. During the processing of a line of dots, one of the two buffers Is written to while the other is being read from. The two buffers are logically swapped upon receipt of the line-sync signal from the PHI. Both buffers E and F are composed of 6 sub-buffers. 1 sub-buffer per color, as shown in FIG. 11, the color 1 sub-buffer numbered 73. The size of each sub-buffer is 2400 bytes, enough to hold 15 segments at 1280 dots per segment. The memory is accessed 32-bits at a time, so there are 600 addresses for each sub-buffer (requiring 10 bits of address). All the even dots are placed before the odd dots in each color's sub-buffer. If there, is any unused space (for printing to fewer than 15 segments) it is located at the end of each color's sub-buffer. The amount of memory actually used from each sub-buffer is directly related to the number of segments actually addressed by die PEC. For a 15 segment print head diere are 1200 bytes of even dots followed by 1200 bytes of odd dots, with no unused space. The number of sub-buffers gainfully used is directly related to the of colors used in the print head. The maximum number of colors supported is 6. The addressing decoding circuitry for each of buffers E and F is such that in a given cycle, a single 32-bii access can be made to all 6 sub-buffers - either a read from all 6 or a write to one of die 6. Only one bit of the 32-bits read from each color buffer is selected, for a total of 6 output bits. The process is shown in FIG. 11. 15 bits of address allow the reading of a particular bit by means of 10-bits of address being used to select 32 bits, and 5-bits of address choose 1 -bit from those 32. Since all color sub-buffers share this logic, k single 15-bit address gives a total of 6 bits out, one bit per color. Each sub-buffer 73 to 78 has its own WriteEnable line, to allow a single 32-bit value to be written to a particular color buffer in a given cycle. The individual Writ Enables are generated by Ending the single Write Enable input with the decoded form of CoIorSelect The 32-bits of Detain on line 79 are shared, since only one buffer will actually clock the detain. Address generation for reading from buffers E and F is straightforward. Each cycle generates a bit address that is used to fetch 6 bits representing 1-bit per color for a particular segment. By adding 640 to the current bit address, we advance to the next segment's equivalent dot- We add 640 (not 1280) since the odd and even dots are separated in the buffer. We do this NumSegments times to retrieve the data representing the even dots, and transfer those bits to the PHI. When NumSegments = 15. the number of bits is 90 (15 x 6 bits). The process is then repeated for the odd dots. This entire even/odd bit generation process is repeated 640 times, incrementing the start address each time. Thus all dot values are transferred to the PHI in the order required by the print head in 640 x 2 x NumSegments cycles. When NumSegments = 15, the number of cycles is 19,200 cycles. Note that regardless of the number of colon actually used in the print head. 6 bits are produced in a given read cycle (one bit from each color's buffer). In addition, we generate the TWriteEnable control signal for writing to the 90-bit Transfer register 90 in FIG. 9. Since the LLFU starts before the PHI, we must transfer the first value before the Advance pulse from the PHI. We must also generate the next value in readiness for the first Advance pulse. The solution is to transfer the first value to the Transfer register after NumSegments cycles, and then to stall NumSegments cycles later, waiting for d\e Advance pulse to start the next NumSegments cycle group. Once the first Advance pulse arrives, the LLFU is synchronized to the PHL The read process for a single dotline is shown in the following pseudopodia: Done First = FALSE WantToXfers FALSE For DotlnSegmcnlO = 0 to 1279 ' Essence = NOT (EFSense) While read process is transacting data from E or F to the PHI, a write process is preparing the next dot-line in the other buffer. The data being written to E or F is color 1 data generated by the HCU, and color 2-6 data from buffer D (supplied from DRAM). Color I daub is written to EF whenever the Chum’s Output Valid flag is set, and color 2-6 data is written during other times from register C. Buffer Oi 81 in FIG. 9 is a 32-bit register used to hold a single HCU-generated set of contiguous 32 dots for color 1. While the dots are contiguous on the page, the odd and even dots arc printed at different times. Buffer AB 82 is a double buffered mechanism for delaying odd dot data for color 1 by 2 dodines. Buffers A and B therefore have identical stniciures. During the processing of a line of dots, one of the two buffers is read from and then written to. The two buffers arc logically swapped after the entire dot line has been processed. A single bit flag Absence determines which of the two buffers are read from and written to. The HCU provides 32-bits of color 1 data whenever the output valid control flag is set, which is every 32 cycles after the font flag has been sent for the line. The 32 bits dine a contiguous set of 32 dots for a single dot line -16 even dots (bits 0,2.4 etc.), and 16 odd dots (bits 1.3.5 etc.). The output valid control flag is used as a WriteEnable control for the OEi register 81. We process the HCU data every 20utputVaIid signals. The 16 even bits of HCU color 1 data are combined with the 16 even bits of register 0£| to make 32-bits of even color Idata. Similarly, the 16 odd bits of HCU color 1 data are combined with the 16 odd bits of register OEi to make 32-bits of odd color 1 data. Upon receipt of the first OutputValid signal of the group of two. we read buffer AB to transfer the odd dual to color 1.73 in FIG. 11 within buffer EF. Upon receipt of the second OutputValid signal of the group of two. we write the 32-bits of odd data to the same location in buffer AB that we read from previously, and we write the 32-bits of even data to color 1 within buffer EF. The HCU provides 32 bits of data per color plane whenever the OutputValid control flag is set. This occurs every 32 cycles except during certain startup dames. The 32 bits define a contiguous set of 32 dots for a single dot line -16 even dots (bits 0.2.4 etc.), and 16 odd dots (bits 1,3.5 etc.). While buffer OE, (83 in FIG. 10) is used to store a single 32-bit value for color 1, buffers Oi to 0E are used to store a single 32-bit value for colon 2 to 6 respectively. Just as the data for color 1 is split into 32-bits representing color 1 odd dots and 32-bits representing color 1 even dots every 64 cycles (once every two OutputValid flags), the remaining color planes are also split into even and odd dots. However, instead of being written directly to buffer EF. the dot data is delayed by a number of lines, and is written out to DRAM via buffer CD (84 in FIG. 9). While the dots for a given line are write to DRAM, the dots for a previous line are read from DRAM and written to buffer EF (71,72). This process must be done interleaved with the process writing color 1 to buffer EF. Every time an OutputValid flag is received from the HCU on line 85 in FIG. 10, the 32-bits of color N data are written to buffer ONE (83). Every second OutputValid fl^. the combined 64-bit value is written to color buffer N (86). This happens in parallel for all color planes 2-6. Color Buffer N (86) contains 40 sets of 64-bits (320 bytes) to enable the dots for two complete segments to be stored This allows a complete segment generation time (20 x 64 = 1280 cycles) for the previous segment's data (both odd and even dots) to be written out to DRAM. Address generation for writing is straightforward. The ColorNWritcEnable signal on line 87 is given every second OutputValid flag. The address starts at 0, and increments every second OutputValid flag until 39. Instead of advancing to 40, the address is reset to 6, thus proved the double-buffering scheme. This works so long as the reading does not occur during the OutputValid flag, and that the previous segment's data can be written to DRAM in the time it takes to generate a single segment's data. The process is shown in the following Wait until next Advance signal from PHI Note that the MaxHalfColors register is one less than the number of colors in terms of odd anvil even colors treated separately, but not including color 1. For example, in terms of a standard 6 color printing system there are 10 (colors 2-6 in odd and even), and so MaxHalfCoIors should be set to 9. The LLFU requires 2NumSegm€nts cycles to prepare the first 180 bits of data for the PHI. Consequently the print head should be started and the first Line Sync pulse must occur this period of time after the LLFU has stoned This allows the initial Transfer value to be valid and the next 90-bit value to be ready to be loaded into the Transfer register. The print head interface (PHI) is the means by which the processor loads the print head with the dots to be printed, and controls the actual dot printing process. It takes input from the LLFU and outputs data to the print head itself. The PHI will be capable of dealing with a variety of print head lengths and formats. The internal structure of the PHI should allow for a maximum of 6 colors, 8 segments per transfer, and a maximum of 2 segment groups. This should be sufficient for a 15 segment (8.5 inch) printer capable of printing A4/Letter at full bleed. Throughout the specification the aim has been to describe the prefenred embodiments of the invention without limiting the invention to any one embodiment or specific collection of features. Persons skilled in the art may realize variations from the specific embodiments that will nonetheless fall 1. A print engine/controller to drive an ink drop print head comprising: an interface at which to receive compressed page data; a contone image decoder to decode any compressed continuous tone image planes in the received compressed page data; a bi-level decoder to decode any compressed bi-level image pianos in the received compressed page data; a half-toner/compositor to dither any continuous tone image planes and composite bi-level image plane data with any output anew; and a print head driver to output the composite to a print head. 2. A print engine/controller as claimed in claim 1 wherein the interface is a high-speed serial interface. 3. . A print engine/controller as claimed in claim 1 wherein the contone image decoder is a JPEG decoder. 4. A print engine/controller as claimed in claim 1 wherein the contone in sage decoder outputs the separate color planes of the decoded image to separate buffers in a front end to the halftoner/compositor. 5. A print engine/controller as claimed in claim I wherein page data in each contone image plane is scaled in the halftoner/compositor. 6. A print engine/controller as claimed in claim 1 wherein the midlevel decoder is a Group 4 facsimile decoder. 7. A print engine/controller as claimed in claim I wherein the bi-level decoder decodes any compressed bi-level image plane in the received compressed image plane to respective buffers in a front end to the halftoner/compositor. 8. A print engine/controller as claimed in claim 1 wherein the page data in the bi-level image plane is scaled in Chef halftoner/compositor. 9. A print engine/controller as claimed in claim 1 further including an infrared tag encoder to produce an infrared image plane to place infrared ink printed tags into a printed page. 10. A print engine/controller to drive an ink drop print head comprising: a contone image decoder to decode any compressed continuous tone image planes in the received compressed page data; a bi-level decoder to decode any compressed bi-level image plane; and a halftoner/compositor including a dot merger unit controlled by a color mask to effect integration of the image planes wide what inks are provided in the print head. 11. A print engine/controller to drive an ink drop print head comprising: a contone image decoder to decode any compressed continuous tone image planes in the received compressed page data; a bi-level decoder to decode any compressed bi-level image plane; and a halftoner/compositor including a margin unit to apply margin data to the respective image planes during the composite process. 12. A print engine/controller clop to interface with an ink drop print head comprising: an interface at which to receive compressed page data; I a contone image decoder to decode any continuous tone image planes in the received compressed page data; a bi-level decoder to decode any bi-level image planes in the received compressed page data; a half-toner/compositor to dither any continuous tone image planes and composite bi-level image plane data with any output plane; and a print head driver to output the composite to a print head. An ink drop printer driven by a print engine/controller comprising: an interface at which to receive compressed page data; a contone image decoder to decode any continuous tone image planes in the received compressed page data; a midlevel decoder to decode any bi-level image planes in the received compressed page data; a half-toner/compositor to dither any continuous tone image planes and composite bi-level image plane data with any output plane; a print head driver to output the composite to a print head; and a print head. A method of operating an ink drop printer comprising: receiving compressed page data decoding any continuous tone image planes in die received compressed page data to generate output planes; decoding any bi-level image planes in the received compressed page data to generate an output plane; dithering any continuous tone image planes compositing any level image plane data with any output plane; and forwarding composite data to a print head. IS. A amount engine/controller to drive an ink drop point head, substantially as Hereinabove described and illustrated with reference to the accompanying drawings.

Documents:

in-pct-2002-1903-che-abstract.pdf

in-pct-2002-1903-che-claims filed.pdf

in-pct-2002-1903-che-claims grand.pdf

in-pct-2002-1903-che-correspondnece-others.pdf

in-pct-2002-1903-che-correspondnece-po.pdf

in-pct-2002-1903-che-description(complete) filed.pdf

in-pct-2002-1903-che-description(complete) grand.pdf

in-pct-2002-1903-che-drawings.pdf

in-pct-2002-1903-che-form 1.pdf

in-pct-2002-1903-che-form 19.pdf

in-pct-2002-1903-che-form 26.pdf

in-pct-2002-1903-che-form 3.pdf

in-pct-2002-1903-che-form 5.pdf

in-pct-2002-1903-che-other documents.pdf

in-pct-2002-1903-che-pct.pdf