Title of Invention  A HIGH SPEED DIFFERENTIAL ENCODER 

Abstract  A high speed differential encoder for quadratic phase shift keying (QPSK) data handling telemetry system, said high speed differential encoder comprising plurality of parallel differential encoder (PDE), each said parallel differential encoder (PDE) comprising a group (01 to Os) of differential encoders (DE) connected in parallel to receive a set containing predetermined number (1 to r) of input signal pairs (IQ) and to provide a set containing same number of encoded output signals (cx, 15) , characterized in that an additional group of differential encoders are provided for each of the parallel differential encoders (PDE), each of the output signals of each said parallel differential encoders (PDE) is fed with the last encoded output signal from the preceding group of encoded output signals to each of the said additional group of differential encoders (DE) to provide encoded output signals (cx, 15) and the last encoded output signals from the last group of output signals provided by the last parallel differential encoder is supplied through a storage element (8E), provided with a clock signal, to the first parallel differential encoder. 
Full Text  The invention relates to a high speed differential encoder for quadrature phase shift keying (QPSK) based data handling telemetry system. In earth observation mission, to transmit the imaging payload at high data rate, coherent QPSK moduation is employed. In coherent QPSK based data transmission systems for satellites, differential encoding is done on the data pair, prior to QPSK modulation for avoiding fourphase ambiguity at the receiver. When implemented in hardware, the speed of the differential encoder is limited because of the feed back path associated with it. The invention provides a differential encoder which will help designers to implement hardware that can improve the speed of differential encoder independent of integrated circuit technology. In quadrature phase shift keying (QPSK) based transmission system, depending upon the input pair of data bits comprising in phase input (I) and quadrature phase input (Q), the carrier phase will change and assumes any one of the possible phases namely 0°, 90°, 180° or 270°. At the receiving end, the demodulator will utilize the phase of modulated signal to identify the incoming data pair. Unfortunately demodulator will not be able to decide the phase of first received signal and will lock to any one of phase, leading to fourphase ambiguity. To avoid this ambiguity, differential encoding is done on data, prior to QPSK modulation at transmitting end. The function of QPSK differential encoder is to generate the pair of data bits depending on the outgoing and incoming pair of data bits by identifying its phase position in the carrier phase plane relative to outgoing differentially encoded data. This transmitted relative phase difference coded data, will avoid fourphase ambiguity at the receiver side. The Boolean equation for the above configuration can be represented as shown by the equations This implementation of the differential encoder (DE) takes data pairs serially and compares the previous data output that is stored in a storage element. The maximum delay of differentially encoded outputs will be the sum of multiplexer delay (dm) and storage element delay (d9). Hence this implementation can support maximum data rate of ^ = 1/ (dm + da). To increase the data rate still further, parallel differential encoding can be applied. The serial data pair stream is made to V parallel pairs and is given to Y DE blocks. The output of last stage is stored for next pair bits. This technique not only improves the speed of operation but also helps to operate at low data rates as well. The maximum speed of operation can be calculated as follows. For V data pair bits, the path delay is (r x dm + dB). Therefore delay for one data pair processing becomes dm if V is a large number. In other words the maximum frequency of operation is limited to l/dm. In a serial differential encoder frequency of operation is limited to 1/ (dm + d3). If the data rate has to be increased, then device with low propagation delay must be used. Very high data rate can be achieved by using bipolar emitter coupled logic integrated circuit but main problem in space application is thermal and power management. The parallel technique is helpful in this respect by operating at lower frequency with additional hardware. With the availability of space qualified field programmable gate arrays (FPGAS) the increase in hardware is not a critical issue. But operational speed in this technique is limited to the process technology of FPGA i.e one multiplexer delay. The high speed differential encoder according to the invention will help to implement the differential encoding that will give output less than one multiplexer delay. Current high resolution imaging mission has imposed constraints on payload data rates as well as handling of payload data. Even though the bandwidth of the space channel for remote sensing application allows the high payload telemetry data rate, the major bottleneck is to handle the base band data at that rate. The highspeed data rate can be handled by two approaches. First approach is to handle the data using highspeed technology. This approach calls for more power and complex thermal management and the existing device technology puts a limitation on this. The second and the most suitable approach is to handle the high frequency data at low frequency using parallel technique. Except for the differential encoding, the other blocks in the data handling system can be implemented effectively using second approach. Differential encoding speed is limited in the second approach due to feedback path associated with it and same will be implemented in separate architecture. The objective of the invention is to improve the data rate of the on board base band data handling system. The function of the data handling system is to format the payload image data into frames and differentially encode the formatted data suitable for transmission. Accordingly the present invention provides a high speed differential encoder for quadratic phase shift keying data handling telemetry system, said high speed differential encoder comprising plurality of parallel differential encoder, each said parallel differential encoder comprising a group of differential encoders connected in parallel to receive a set containing predetermined number of input signal pairs and to provide a set containing same number of encoded output signals; each of the output signals of each said parallel differential encoders being connected along with the last encoded output signal from the preceding group of encoded output signals through separate differential encoders to provide encoded output signals and last encoded output signals from the last group of output signals provided by the last parallel differential encoder is connected through a storage element provided with a clock signal, to the first parallel differential encoder. The high speed differential encoder will now be described with reference to the accompanying drawings. Figure 1 shows the schematic diagram of a known differential encoder (DE). Figure 2 shows the schematic diagram of a parallel differential encoder (PDE). Figure 3 shows the schematic diagram of a high speed differential encoder according to the invention. Figure 4 shows a schematic diagram of serial implementation of a typical differential encoder. Figure 5 shows the schematic diagram of the parallel implementation of a typical parallel differential encoder. Figure 6 shows the schematic diagram of the implementation of a typical high speed differential encoder. Figure 7 shows simulation results of a serial differential encoder, a parallel differential encoder and a high speed differential encoder. Figure 8 shows the expanded portion of the output delay for a typical parallel encoder. Figure 9 shows the expanded portion of the output delay for a typical parallel encoder. Figure 10 shows the expanded portion of the output delay for a typical high speed differential encoder. The maximum parallel input data rate possible for the above implementation scheme is limited to l/(r x dm), where Y is the number of parallel stages and 6dm' is the multiplexer delay. In fast architecture approach, *t* pair bits are made into V groups of V pair bits. The parallel differential encoding approach is applied for each group without storage element. The first group is encoded differentially using the last outgoing data. In the mean time remaining V1 'groups are also encoded differentially with the fixed zero phase. The first group gives out the V pair bits of differentially encoded data. The last stage output of the first group is again differentially encoded with the each stage of second group output. This results into differentially encoded data of second stage. The procedure is followed for the remaining !s 2f groups to get the remaining differentially encoded bits. The last stage of the s^ group is stored for the next operation. This approach reduces the operational delay to (r + s1 ) x dm for ft' pair bits where 't' is large. For one pair of bits the operation reduces to (1/ r)+( 1/ s )dm. When r >1 and s >1 the frequency of differential encoding will operate with the delay less than dm. The scheme is depicted in Fig 3. Figure 1 shows a differential encoder (DE) comprising a pair of multiplexers (MUX) each having a pair of inputs (In> Qn) and a pair of encoded outputs (a^ p „). A storage element (SE) with a clock signal (C) are connected to the out put of each multiplexers (MUX) for the implementation of the differential encoder (DE). Figure 2 shows a parallel differential encoder comprising plurality of differentiqal encoders (DEi, DE2. . . DEf) is connected in parallel with output of each differential encoder being connected to the input of the succeeding differential encoder along with pair of signals for encoding. The output of the last differential encoder (DEr) is connected through a storage element (SE) provided with a clock signal is connected to the input of the first differential encoder (DEi). Figure 3 shows a high speed differential encoder according to the invention in which pluralities of parallel differential encoders (PDE) are connected to receive plurality groups (Gi? G2, Gn) of plurality of pairs of signals (Ir, Qr) by plurality of parallel differential encoders. The first group of signals are encoded differentially using last out going encoded signal (01^ pr) and the subsequent group of signals are encoded differentially with fixed zero phase. The first group of signals (GO gives out r pairs of differentially encoded data. The output from the last stage of the first group (GO is again differentially encoded with data from each stage of second group (G2). The output (a^, p2r) from the last stage in second group (G2) is differentially encoded with data from each stage of third group (G3) and so on. The output (o^ pt) from the last group (Gs) is fed to the first parallel differential encoder of the first group (GO through a storage element (SE) provided with a clock signal ( C). Figures 4, 5 and 6 shows serial implementation of typical differential encoder, parallel implementation of typical parallel encoder and implementation of typical high speed differential encoder. The simulation results of the circuits shown in figures 4, 5 and 6 are shown in figure 7. Figure 8, 9 and 10 show the expanded portion of the output delay portions from figure 7 in respect of the serial differential encoder, parallel differential encoder and high speed differential encoder respectively. For the simulation of all the three approaches, the propagation delay for multiplexer, inverter and flipflop is set to lOOps each in the simulator. The maximum delay for serial implementation can come to delmax = 300p8 for the path Mux + Inv + FF. For Parallel approach delmax will be 32 x lOOps = 3.2 ns. For encoding of one pair the maximum delay for parallel approach comes to 3200ps/16==:200ps. For fast architecture approach maximum delay will be 14x1 OOps = 1.4ns. In this approach the maximum delay to encode one pair is 1400ps/16==87.5ps. The results in the fig.8, fig.9, fig.10 indicates output delay as 200 ps, 2.5ns and 1.2ns for serial differential encoder, parallel differential encoder and high speed differential encoder respectively. This is due to the select lines of multiplexer which can either select longest path that includes the inverter or shortest path without the inverter. Compared to the conventional parallel differential encoder (PDE) the high speed differential encoder according to the invention can be operated at more than twice the data rate and can be configured for low data rate to very high data rate applications. WE CLAIM : 1. A high speed differential encoder for quadratic phase shift keying (QPSK) data handling telemetry system, said high speed differential encoder comprising plurality of parallel differential encoder (PDE), each said parallel differential encoder (PDE) comprising a group (Gi to G2) of differential encoders (DE) connected in parallel to receive a set containing predetermined number (1 to r) of input signal pairs (IQ) and to provide a set containing same number of encoded output signals (a,p); each of the output signals of each said parallel differential encoders (PDE) being connected along with the last encoded output signal from the preceeding group of encoded output signals through separate differential encoders (DE) to provide encoded output signals (oc,(3) and last encoded output signals from the last group of output signals provided by the last parallel differential encoder is connected through a storage element (SE) provided with a clock signal, to the first parallel differential encoder. 2. The high speed differential encoder as claimed in claim 1, wherein each said parallel differential encoder are connected to operate at zero phase. 3. A high speed differential encoder for quadratic phase shift keying (QPSK) data handling telemetry system, substantially as hereinabove described and illustrated with reference to the accompanying drawings. 

447mas2001 claims duplicate.pdf
447mas2001 claims original.pdf
447mas2001 correspondence others.pdf
447mas2001 correspondence po.pdf
447mas2001 description complete duplicate.pdf
447mas2001 description complete original.pdf
447mas2001 description provisional.pdf
Patent Number  207522  

Indian Patent Application Number  447/MAS/2001  
PG Journal Number  44/2007  
Publication Date  02Nov2007  
Grant Date  14Jun2007  
Date of Filing  06Jun2001  
Name of Patentee  M/S. INDIAN SPACE RESEARCH ORGANISATION  
Applicant Address  ISRO HEADQUARTERS, ANTARIKSH BHAVAN, NEW BEL ROAD, BANGALORE 560094, KARNATAKA.  
Inventors:


PCT International Classification Number  H04 L27/00  
PCT International Application Number  N/A  
PCT International Filing date  
PCT Conventions:
