Title of Invention	A HIGH DENSITY HYBRID INTEGRATED CIRCUIT PACKAGE HAVING A FLIP-CON STRUCTURE AND A METHOD OF MANUFACTURING THE SAME
Abstract	The invention relates to a high density hybrid integrated circuit package. It comprises of an insulator substrate with a metalised pattern for interconnecting the integrated circuit configuration. An integrated circuit flip chip consists of plurality of semiconductor devices and is provided with gold stud bumps for providing inter-connections by thermal compression bonding. Gold stud bumps on the flip clip is bonded to the metalised portions on the ceramic substrate. An integrated circuit top chip consists of plurality of semiconductor devices fixed with an epoxy to the top portion of the flip chip. The electrical connections from the top chip to the metalised pattern on the substrate is taken through goldwires bonded to the top chip and the metalised pattern on the substrate.

Title of Invention

A HIGH DENSITY HYBRID INTEGRATED CIRCUIT PACKAGE HAVING A FLIP-CON STRUCTURE AND A METHOD OF MANUFACTURING THE SAME

Abstract

The invention relates to a high density hybrid integrated circuit package. It comprises of an insulator substrate with a metalised pattern for interconnecting the integrated circuit configuration. An integrated circuit flip chip consists of plurality of semiconductor devices and is provided with gold stud bumps for providing inter-connections by thermal compression bonding. Gold stud bumps on the flip clip is bonded to the metalised portions on the ceramic substrate. An integrated circuit top chip consists of plurality of semiconductor devices fixed with an epoxy to the top portion of the flip chip. The electrical connections from the top chip to the metalised pattern on the substrate is taken through goldwires bonded to the top chip and the metalised pattern on the substrate.

Full Text	The invention relates to a high density hybrid integrated circuit package having a flip con structure and a method of uanufaoturing the same If'lip fton est rue tare is a novel chip integration technique which provides about 90% increase in packaging densities in a hybrid integrated circuit. With small satellite missions becoming a reality and preliminary studies undergoing, it was felt that new packaging technologies which could provide higher functional integration in small volumes shall be pursued. So far users are provided with single layer and multilayer hybrid circuits using conventional chip and wire technology. Though some developmental work has been carried out in areas of multilayer structures and photo etchable high density interconnections for increasing interconnect densities» it did not provide major improvements. In a conventional hybrid integrated circuit, interconnections are carried out by wire bonding. In a flip chip assembly of hybrid integrated circuit, the chip is reversed and directly attached to a substrate in face down configuration. The interconnections between bond pads of chip and metalised conductor are provided through metallic bumps formed on the chip. The high density hybrid integrated circuit package according to the invention provides a three dimensional packaging by mounting two chips on over the other on a substrate. i Accordingly the present invention provides a high density hybrid integrated circuit package comprising an insulator substrate with a metaiised pattern for interconnecting the integrated circuit configuration an integrated circuit flip chip consisting of plurality of semiconductor devices and provided with gold stud bumps for providing inter-connect ions by thermal compression bonding> the said gold stud bumps on the flip clip being bonded to the metaiised portions on the ceramic substrate, an integrated circuit top chip consisting of plurality of semiconductor devices being fixed with an epoxy to the top portion of the flip chip and the electrical connections from the top chip to the metaiised pattern on the substrate being taken through goidwires bonded to the top chip and the metaiised pattern on the substrate. The invention also provides a method of manufacturing a high density hybrid integrated circuit package as described hereinabove, comprising the steps of preparing art insu later substrate with a metaiised pattern to form the desired integrated circuit configuration, preparing an integrated circuit flip chip and an integrated circuit top chip consisting of plurality of semiconductor devices, making gold stud bumps on the flip chip„ at \ aching, the V t ip ^bip by thermal compression bonding between the gold stud bumps on the flip chip and the corresponding connection points on the top chip to the respective connection points in the metalised pattern on the substrate, f ixing the top *-hip on top of the flip chip by means of an epoxy adhesive, bondiug go Id wire to the connect i on points on the top ohip to the respective connect ion points in the metalised pattern on the substrate to obtain the hybrid integrated circuit package f'rfiter ably 1:he space between the f 1 ip chip and the insulater substrate is fi 1 led with an epoxy and cured for a stab1e attachment between the flip chip and the substrate. The insulator substrate is preferably a ceramic substrate, Thus in be hybrid integrated circuit package according to the invention, the integrated circuit in the flip chip and the integrated n i rcu it in the top chip are mounted back to back. The connections from the integrated circuit in th flip chip is provided by chip bonding and the connections from the integrated circuit in the top chip is provided by wire bonding. t n order to make the interconnection between the flip chip and the substrate the chip is tempererily glued to a substrate with an adhesive. Then using gold wire and thermosonic wire bonder, the gold stud bumps are formed on the chip at the point of connections. Typically, the gold wire used is of about 1.0 mil diameter, 1 to 3% elongation and tensil strength of about 12 gms The gold stud bumps are made preferably keeping the temperature of the substrate at 12b to 150°C, bonding force i«at.v?een 40 to 100 gms and the bonding time between 40 to 80 millisecond The chip is removed from the substrate after the £oid stud bumps are formed on the chip, The f 3 ip chip with gold stud bumps are aligned with the metalised pattern on the subsirate which is heated preferably at a temperature of 240 to i!60°t mi:\ bonded to the respective connection points in the metalised pattern on the substrate by thermal compression bonding. The bonded chip is tested for interconnection integrity The method of chip bonding and wire bonding are well known in the art and the optimum parameters to obtain good result are well known tor person skilled in the art. Various thermal compression bonding machines and thermosonic wire bonders are used in the art. After the flip chip is bonded to the substrate» an epoxy is dispensed from the side to fill the space between the flip chip and the substrate. It is preferable to use a two part epoxy with a viscosity typically in the range of 1800 to 2000 ops, so that, the space between the flip chip and substrate is filled by capillary action. It is then cured at a temperature preferably in the range of 80 to 150°C for a period of 30 to 120 minutes in an oven The top chip is attached with non-conductive epoxy adhesive to the flip chip and cured preferably at a temperature in i be range of 80 to 150°C for 30 to 120 minutes in an oven. Interconnections from top chip to the metalised pattern on the substrate is done by thermogenic wire bonding using gold wire Typically 1.0 mil diameter gold wire having an elongation of i to 3%, tensile strength of 12 gms is used for wire bonding » Preferably substrate .temperature may be kept at 125 to 150°C, t»««n In order tn protect the wire bonding from mechanical stress the structure is preferably encapsulated using a known glob top enoapsulant. it provides additional heat desipation to the package The invention will now be described with reference to the accompanying drawings : }? ig 1 : shows the structure of a conventional wire bonded integrated circuit V ig 'A shows the structure of a conventional chip bonded integrated circui t Pig. 3 shows the structure of a high density hybrid integrated circuit package according to the invention. I*v ig 4 shows the process f low chart illustrating the anufacturing steps. The structure of integrated circuit package using wire bonding is shown in fig, J and that using chip bonding is shown in fig. 2 The connections from the integrated circuit chip (2 > to the metalised pattern on the substrate (1) is provided through gold wire bonded to the chip (2> and to the connection points to the substrate the integrated circuit chip is a flip chip (7 > with gold stud bumps C8) for bonding to the metalised pattern on the substrate ( 1 ). The flip chip and the substrate C1) is filled with epoxy to provide better adherence of the flip chip ) to the substrate CI). The integrated circuit package according to the invention is shown in fig,3. An integrated circuit flip chip (7) is provided with gold stud bumps is fixed to the integrated circuit flip chip . The » interconnections from the top chip on the substrate (1) The method steps tor manufacturing the high density hybrid integrated circuit package is illustrated in figure 4. A high density interconnect substrate is prepared on an insulator substrate (1> preferably on a ceramic substrate, by metalising the desired pattern The stud bumps are formed on the flip chip 7) for bonding with the substrate is bonded with the metalised pattern on the substrate and tested. Then an epoxy (3) is dispensed from the side to fill the space between the flip chip > and substrate (1) followed by curing. The top chip (9) is attached to the flip chip by an epoxy adhesive (8 ) . The connections from the top chip to the metalised pattern on the substrate is made through gold wires by wire bonding. The high density integrated circuit package is tested for interconnection integrity. In order to protect the wire bonds from mechanical stress the hybrid integrated circuit package may preferably be encapsulated using a suitable encapsulant, This will also help heat descipation characteristics of the device. The hybrid integrated circuit package according to the invention can be used with advantage in portable electronic gadgets, personal computers, disc drives, high density memories and various other commercial applications. The invention provides hybrid integrated circuit package with higher packaging density with reduced effective weight. The tests conducted on the hybrid integrated circuit package according to the invention provided excellent results and the structure is found rugged and reliable We Claim : 1 & high density hybrid integrated circuit package comprising an insulator substrate CI) with a metalised pattern for interconnecting the integrated circuit configuration > an integrated circuit flip chip consisting of plurality of semiconductor devices and provided with gold stud bumps for providing inter-connections by thermal compression bonding, the said gold stud bumps on the flip clip being bonded to the metalised portions on the ceramic substrate (1), an integrated circuit top chip {9) consisting of plurality of semiconductor devices being fixed with an epoxy (8) to the top portion of the flip chip (?) and the electrical connections from the top chip (7) to the metalised pattern C5> on the substrate (1) being taken through goldwires (4) bonded to the top chip (?) and the metalised pattern on the substrate CI). 2 h high density hybrid integrated circuit package, as claimed in claim 1, wherein the space between the said flip chip . 3. A high density hybrid integrated circuit package, as claimed in claims 1 or 2, wherein the said insulator substrate (1) is a ceramic substrate, 4 a method of manufacturing a high density hybrid integrated circuit package as claimed in claim 1, comprising the steps of preparing an insulator substrate tl> with a metaiised pattern to form the desired integrated circuit configuration, preparing an inlegrated circuit flip chip (7> and an integrated circuit top chip making gold stud bumps <.> on the flip chip attaching the flip chip (7 ) by thermal compression bonding between the gold stud bumps (6 > on i- he flip chip and the corresponding connection points on the top chip on top of the flip chip (7) by means of an epoxy adhesive » bonding gold wire to the connection points on the top chip i9> to the respective connection points in the metaiised pattern on the substrate (1> to obtain the hybrid integrated circuit package. 5, The method as claimed in claim 4, wherein the space between the substrate (1) and the flip chip (7) is filled by dispensing a two part epoxy from the side and cured before fixing the top chip . 8, The method as claimed in claims 4 or 5, wherein the insulator substrate is a ceramic substrate. 7 ft high density hybrid integrated circuit package, substantially as hereinabove described and illustrated with reference to figure 3 of the accompanying drawings. 8. A method of manufacturing a high density hybrid integrated circuit package, substantially as hereinabove described and illustrated with reference to figure 4 of the accompanying drawings,

Full Text

The invention relates to a high density hybrid integrated circuit package having a flip con structure and a method of uanufaoturing the same
If'lip fton est rue tare is a novel chip integration technique which provides about 90% increase in packaging densities in a hybrid integrated circuit.
With small satellite missions becoming a reality and preliminary studies undergoing, it was felt that new packaging technologies which could provide higher functional integration in small volumes shall be pursued. So far users are provided with single layer and multilayer hybrid circuits using conventional chip and wire technology. Though some developmental work has been carried out in areas of multilayer structures and photo etchable high density interconnections for increasing interconnect densities» it did not provide major improvements. In a conventional hybrid integrated circuit, interconnections are carried out by wire bonding. In a flip chip assembly of hybrid integrated circuit, the chip is reversed and directly attached to a substrate in face down configuration. The interconnections between bond pads of chip and metalised conductor are provided through metallic bumps formed on the chip.
The high density hybrid integrated circuit package according to the invention provides a three dimensional packaging by mounting two chips on over the other on a substrate.

i
Accordingly the present invention provides a high density hybrid integrated circuit package comprising an insulator substrate with a metaiised pattern for interconnecting the integrated circuit configuration an integrated circuit flip chip consisting of plurality of semiconductor devices and provided with gold stud bumps for providing inter-connect ions by thermal compression bonding> the said gold stud bumps on the flip clip being bonded to the metaiised portions on the ceramic substrate, an integrated circuit top chip consisting of plurality of semiconductor devices being fixed with an epoxy to the top portion of the flip chip and the electrical connections from the top chip to the metaiised pattern on the substrate being taken through goidwires bonded to the top chip and the metaiised pattern on the substrate.
The invention also provides a method of manufacturing a high density hybrid integrated circuit package as described hereinabove, comprising the steps of preparing art insu later substrate with a metaiised pattern to form the desired integrated circuit configuration, preparing an integrated circuit flip chip and an integrated circuit top chip consisting of plurality of semiconductor devices, making gold stud bumps on the flip chip„

at \ aching, the V t ip ^bip by thermal compression bonding between the gold stud bumps on the flip chip and the corresponding connection points on the top chip to the respective connection points in the metalised pattern on the substrate, f ixing the top **-hip on top of the flip chip by means of an epoxy adhesive, bondiug go Id wire to the connect i on points on the top ohip to the respective connect ion points in the metalised pattern on the substrate to obtain the hybrid integrated circuit package
f'rfiter ably 1:he space between the f 1 ip chip and the insulater substrate is fi 1 led with an epoxy and cured for a stab1e attachment between the flip chip and the substrate. The insulator substrate is preferably a ceramic substrate, Thus in * be hybrid integrated circuit package according to the invention, the integrated circuit in the flip chip and the integrated n i rcu it in the top chip are mounted back to back. The connections from the integrated circuit in th flip chip is provided by chip bonding and the connections from the integrated circuit in the top chip is provided by wire bonding.
t n order to make the interconnection between the flip chip and the substrate the chip is tempererily glued to a substrate with an adhesive. Then using gold wire and thermosonic wire bonder, the gold stud bumps are formed on the chip at the point of connections. Typically, the gold wire used is of about 1.0 mil diameter, 1 to 3% elongation and tensil strength of about 12

gms The gold stud bumps are made preferably keeping the temperature of the substrate at 12b to 150°C, bonding force i«at.v?een 40 to 100 gms and the bonding time between 40 to 80 millisecond The chip is removed from the substrate after the £oid stud bumps are formed on the chip, The f 3 ip chip with gold stud bumps are aligned with the metalised pattern on the subsirate which is heated preferably at a temperature of 240 to i!60°*t mi*:\ bonded to the respective connection points in the metalised pattern on the substrate by thermal compression bonding. The bonded chip is tested for interconnection integrity
The method of chip bonding and wire bonding are well known in the art and the optimum parameters to obtain good result are well known tor person skilled in the art. Various thermal compression bonding machines and thermosonic wire bonders are used in the art.
After the flip chip is bonded to the substrate» an epoxy is dispensed from the side to fill the space between the flip chip and the substrate. It is preferable to use a two part epoxy with a viscosity typically in the range of 1800 to 2000 ops, so that, the space between the flip chip and substrate is filled by capillary action. It is then cured at a temperature preferably in the range of 80 to 150°C for a period of 30 to 120 minutes in an oven The top chip is attached with non-conductive epoxy adhesive to the flip chip and cured preferably at a temperature in i be range of 80 to 150°C for 30 to 120 minutes in an oven.

Interconnections from top chip to the metalised pattern on the substrate is done by thermogenic wire bonding using gold wire Typically 1.0 mil diameter gold wire having an elongation of i to 3%, tensile strength of 12 gms is used for wire bonding » Preferably substrate .temperature may be kept at 125 to 150°C, t»««n In order tn protect the wire bonding from mechanical stress the structure is preferably encapsulated using a known glob top enoapsulant. it provides additional heat desipation to the package
The invention will now be described with reference to the accompanying drawings :
}? ig 1 : shows the structure of a conventional wire bonded integrated circuit
V ig 'A shows the structure of a conventional chip bonded integrated circui t
Pig. 3 shows the structure of a high density hybrid integrated circuit package according to the invention.
I*v ig 4 shows the process f low chart illustrating the anufacturing steps.

The structure of integrated circuit package using wire bonding is shown in fig, J and that using chip bonding is shown in fig. 2 The connections from the integrated circuit chip (2 > to the metalised pattern on the substrate (1) is provided through gold wire bonded to the chip (2> and to the connection points to the substrate the integrated circuit chip is a flip chip (7 > with gold stud bumps C8) for bonding to the metalised pattern on the substrate ( 1 ). The flip chip and the substrate C1) is filled with epoxy to provide better adherence of the flip chip ) to the substrate CI). The integrated circuit package according to the invention is shown in fig,3. An integrated circuit flip chip (7) is provided with gold stud bumps is fixed to the integrated
circuit flip chip . The
»
interconnections from the top chip on the substrate (1)

The method steps tor manufacturing the high density hybrid integrated circuit package is illustrated in figure 4. A high density interconnect substrate is prepared on an insulator substrate (1> preferably on a ceramic substrate, by metalising the desired pattern The stud bumps are formed on the flip chip 7) for bonding with the substrate is bonded with the metalised pattern on the substrate and tested. Then an epoxy (3) is dispensed from the side to fill the space between the flip chip > and substrate (1) followed by curing. The top chip (9) is attached to the flip chip by an epoxy adhesive (8 ) . The connections from the top chip to the metalised pattern on the substrate is made through gold wires by wire bonding. The high density integrated circuit package is tested for interconnection integrity. In order to protect the wire bonds from mechanical stress the hybrid integrated circuit package may preferably be encapsulated using a suitable encapsulant, This will also help heat descipation characteristics of the device.
The hybrid integrated circuit package according to the invention can be used with advantage in portable electronic gadgets, personal computers, disc drives, high density memories and various other commercial applications. The invention provides hybrid integrated circuit package with higher packaging density with reduced effective weight.
The tests conducted on the hybrid integrated circuit package according to the invention provided excellent results and the structure is found rugged and reliable

We Claim :
1 & high density hybrid integrated circuit package comprising an insulator substrate CI) with a metalised pattern for interconnecting the integrated circuit configuration > an integrated circuit flip chip consisting of plurality of semiconductor devices and provided with gold stud bumps for providing inter-connections by thermal compression bonding, the said gold stud bumps on the flip clip being bonded to the metalised portions on the ceramic substrate (1), an integrated circuit top chip {9) consisting of plurality of semiconductor devices being fixed with an epoxy (8) to the top portion of the flip chip (?) and the electrical connections from the top chip (7) to the metalised pattern C5> on the substrate (1) being taken through goldwires (4) bonded to the top chip (?) and the metalised pattern on the substrate CI).
2 h high density hybrid integrated circuit package, as claimed in claim 1, wherein the space between the said flip chip .
3. A high density hybrid integrated circuit package, as claimed in claims 1 or 2, wherein the said insulator substrate (1) is a ceramic substrate,

4 a method of manufacturing a high density hybrid integrated circuit package as claimed in claim 1, comprising the steps of preparing an insulator substrate tl> with a metaiised pattern to form the desired integrated circuit configuration, preparing an inlegrated circuit flip chip (7> and an integrated circuit top chip making gold stud bumps <.> on the flip chip attaching the flip chip (7 ) by thermal compression bonding between the gold stud bumps (6 > on i- he flip chip and the corresponding connection points on the top chip on top of the flip chip (7) by means of an epoxy adhesive » bonding gold wire to the connection points on the top chip i9> to the respective connection points in the metaiised pattern on the substrate (1> to obtain the hybrid integrated circuit package.
5, The method as claimed in claim 4, wherein the space between the substrate (1) and the flip chip (7) is filled by dispensing a two part epoxy from the side and cured before fixing the top chip .
8, The method as claimed in claims 4 or 5, wherein the insulator substrate is a ceramic substrate.

7 ft high density hybrid integrated circuit package, substantially as hereinabove described and illustrated with reference to figure 3 of the accompanying drawings.
8. A method of manufacturing a high density hybrid integrated circuit package, substantially as hereinabove described and illustrated with reference to figure 4 of the accompanying drawings,

Documents:

1120-mas-1999- abstract.pdf

1120-mas-1999- claims duplicate.pdf

1120-mas-1999- claims original.pdf

1120-mas-1999- correspondence others.pdf

1120-mas-1999- correspondence po.pdf

1120-mas-1999- description complete duplicate.pdf

1120-mas-1999- description complete original.pdf

1120-mas-1999- drawings.pdf

1120-mas-1999- form 1.pdf

1120-mas-1999- form 19.pdf

1120-mas-1999- form 26.pdf

1120-mas-1999- form 3.pdf

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Patent Number

207442

Indian Patent Application Number

1120/MAS/1999

PG Journal Number

26/2007

Publication Date

29-Jun-2007

Grant Date

13-Jun-2007

Date of Filing

16-Nov-1999

Name of Patentee

INDIAN SPACE RESEARCH ORGANISATION

Applicant Address

ISRO HEADQUARTERS ,ANTHARIKSH BHAVAN, NEW BEL ROAD, BANGALORE-560 094.

Inventors:

#	Inventor's Name	Inventor's Address
1	PAPUU SATYANARAYANA	ISRO SATELLITE CENTRE, AIRPORT ROAD, BANGALORE- 560 017.

PCT International Classification Number

H05K1/00

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA