Indian Patents. 206959:A METHOD OF FABRICATING A GALLIUM NITRIDE SEMICONDUCTOR LAYER

Title of Invention	A METHOD OF FABRICATING A GALLIUM NITRIDE SEMICONDUCTOR LAYER
Abstract	A method of fabricating a gallium nitride semiconductor layer comprising the steps of: laterally growing at least one sidewall of an underlying gallium nitride layer into at least one trench in the underlying gallium nitride layer to thereby form a lateral gallium nitride semiconductor layer.

Full Text	FORM 2 THE PATENTS ACT 1970 [39 OF 1970] COMPLETE SPECIFICATION [See Section 10] "FABRICATION OF GALLIUM NITRJPE SEMICONDUCTOR LAYERS BY LATERAklaROWTH FROM TRENCH SIDEWALLS" NORTH CAROLINA STATE UNIVERSITY, of 1 Holladay Hall, Campus Box 7003, Raleigh, North Carolina 27695-7003, United States of America, The following specification particularly describes the nature of the invention and the manner in which it is to be performed:- Field of the Invention This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor. 5 Background of the Invention Gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium 10 nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride. A major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium 15 nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable. 20 It is also known to fabricate gallium nitride structures through openings in a mask. For example, in fabricating field emitter arrays, it is known to selectively grow gallium nitride on stripe or circular patterned substrates. See, for example, the publications by Nam et al. entitled "Selective Growth o/GaN and AIo.jGao.sN on GaN/AlN/6H-SiC(0001) Multilayer Substrates Via Organometallic Vapor Phase 25 Epitaxy", Proceedings of the Materials Research Society, December 1996, and "Growth of GaN and Alo.7Gao.3Non PatterenedSubstrates via Organometallic Vapor Phase Epitaxy", Japanese Journal of Applied Physics., Vol. 36, Part 2, No. 5A, May 1997, pp. L532-L535. As disclosed in these publications, undesired ridge growth or lateral overgrowth may occur under certain conditions. Summary of the Invention 5 It is therefore an object of the present invention to provide improved methods of fabricating gallium nitride semiconductor layers, and improved gallium nitride layers so fabricated. It is another object of the invention to provide methods of fabricating gallium nitride semiconductor layers that can have low defect densities, and gallium nitride 10 semiconductor layers so fabricated. These and other objects are provided, according to the present invention by laterally growing a sidewall of an underlying gallium nitride layer into a trench in the underlying gallium nitride layer, to thereby form a lateral gallium nitride layer. Microelectronic devices may then be formed in the lateral gallium nitride layer. 15 It has been found, according to the present invention, that dislocation defects do not significantly propagate laterally from the sidewall into the trench in the underlying gallium nitride layer, so that the lateral gallium nitride semiconductor layer is relatively defect free. The sidewall growth may be accomplished without the need to mask portions of the underlying gallium nitride layer during growth of the 20 lateral gallium nitride layer. According to another aspect of the present invention, a pair of sidewalls of the underlying gallium nitride layer are laterally grown into a trench in the underlying gallium nitride layer between the pair of sidewalls until the grown sidewalls coalesce in the trench. The lateral gallium nitride semiconductor layer may be laterally grown 25 using metalorganic vapor phase epitaxy (MOVPE). For example, the lateral gallium nitride layer may be laterally grown using triethylgallium (TEG) and ammonia (NH3) precursors at 1000-1100°C and 45 Torr. Preferably, TEG at 13-39umol/min and NH3 at 1500 seem are used in combination with 3000 seem H2 diluent. Most preferably, TEG at 26umol/min, NH3 at 1500 seem and H2 at 3000 seem at a temperature of 30 1100°C and 45 Torr are used. The underlying gallium nitride layer preferably is formed on a substrate such as 6H-SiC(0001), which itself includes a buffer layer such as aluminum nitride thereon. Other substrates such as sapphire, and other buffer . layers such as low temperature gallium nitride, may be used. Multiple substrate layers and buffer layers also may be used. The underlying gallium nitride layer including the sidewall may be formed by forming the trench in the underlying gallium nitride layer, such that the trench 5 includes the sidewall. Alternatively, the sidewall may be formed by forming a post on the underlying gallium nitride layer, the post including the sidewall and defining the trench. A series of alternating trenches and posts is preferably formed to form a plurality of sidewalls. Trenches and/or posts may be formed by selective etching, selective epitaxial growth, combinations of etching and growth, or other techniques. 10 The trenches may extend into the buffer layer and into the substrate. The sidewall of the underlying gallium nitride layer is laterally grown into the trench, to thereby form the lateral gallium nitride layer of lower defect density than the defect density of the underlying gallium nitride layer. Some vertical growth may also occur. The laterally grown gallium nitride layer is vertically grown while 15 propagating the lower defect density. Vertical growth may also take place simultaneous with the lateral growth. The defect density of the overgrown gallium nitride semiconductor layer may be further decreased by growing a second gallium nitride semiconductor layer from the lateral gallium nitride layer. In one embodiment, the lateral gallium nitride layer 20 is masked with a mask that includes an array of openings therein. The lateral gallium nitride layer is grown through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. In another embodiment, the lateral gallium nitride layer is grown vertically. A plurality of second sidewalls are formed in the vertically grown lateral gallium nitride layer to define a plurality of 25 second trenches. The plurality of second sidewalls of the vertically grown lateral gallium nitride layer are then laterally grown into the plurality of second trenches, to thereby form a second lateral gallium nitride layer. Microelectronic devices are then formed in the gallium nitride semiconductor layer. The plurality of sidewalls of the underlying gallium nitride layer may be grown using metalorganic vapor phase 30 epitaxy as was described above. The second sidewalls may be grown by etching and/or selective epitaxial growth of trenches and/or posts, as was described above. Gallium nitride semiconductor structures according to the invention comprise an underlying gallium nitride layer including a trench having a sidewall. and a lateral gallium nitride layer that extends from the sidewall of the underlying gallium nitride layer into the trench. A vertical gallium nitride layer extends from the lateral gallium nitride layer. A plurality of microelectronic devices are included in the vertical gallium nitride layer. A series of alternating trenches and posts may be provided to 5 define a plurality of sidewalls. The underlying gallium nitride layer includes a predetermined defect density, and the lateral gallium nitride, layer is of lower defect density than the predetermined defect density. Other embodiments of gaih'um nitride semiconductor structures according to the invention comprise a mask including an array of openings therein on the lateral 10 gallium nitride layer and a vertical gallium nitride layer that extends from the lateral gallium nitride layer through the openings and onto the mask. Alternatively, a vertical gallium nitride layer extends from the lateral gallium nitride layer and includes a plurality of second sidewalls therein. A second lateral gallium nitride layer extends from the plurality of second sidewalls. Microelectronic devices are included 15 in the second lateral gallium nitride layer. Accordingly, low defect density gallium nitride semiconductor layers may be produced, to thereby allow the production of high performance microelectronic devices. Brief Description of the Drawings 20 Figures 1-5 are cross-sectional views of first embodiments of gallium nitride semiconductor structures during intermediate fabrication steps according to the present invention. Figures 6-10 are cross-sectional views of second embodiments of gallium nitride semiconductor structures during intermediate fabrication steps according to the 25 present. invention. Figures 11-15 are cross-sectional views of third embodiments of gallium nitride semiconductor structures during intermediate fabrication steps according to the present invention. 30 Detailed Description of Preferred Embodiments The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the . invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like 5 numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "onto" another element, it can be directly on the other element or intervening elements may also be present. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well. 10 Referring now to Figures 1-5, methods of fabricating gallium nitride semiconductor structures according to a first embodiment of the present invention will now be described. As shown in Figure 1, an underlying gallium nitride layer 104 is grown on a substrate 102. The substrate 102 may include a 6H-SiC(0001) substrate 102a and an aluminum nitride buffer layer 102b. The crystallographic designation 15 conventions used herein are well known to those having skill in the art, and need not be described further. The gallium nitride layer 104 may be between 1.0 and 2.0um thick, and may be grown at 1000°C on a high temperature (1100°C) aluminum nitride buffer layer 102b that was deposited on the 6H-SiC substrate 102a in a cold wall vertical and inductively heated metalorganic vapor phase epitaxy system using 20- triethylgallium at 26umol/min, ammonia at 1500 seem and 3000 seem hydrogen diluent. Additional details of this growth technique may be found in a publication by T.W. Weeks et al. entitled "GaN Thin Films Deposited Via Organometallic Vapor Phase Epitaxy on a(6H)-SiC(0001) Using High-Temperature Monocrystalline AIN Buffer Layers", Applied Physics Letters, Vol. 67, No. 3, July 17, 1995, pp. 401-403, 25 the disclosure of which is hereby incorporated herein by reference. Other substrates, with or without buffer layers, may be used. Still referring to Figure 1, the underlying gallium nitride layer 104 includes a plurality of sidewalls 105 therein. It will be understood by those having skill in the art that the sidewalls 105 may be thought of as being defined by a plurality of spaced 30 apart posts 106, that also may be referred to as "mesas", "pedestals" or "columns". The sidewalls 105 may also be thought of as being defined by a plurality of trenches 107, also referred to as "wells" in the underlying gallium nitride layer 104. The sidewalls 105 may also be thought of as being defined by a series of alternating trenches 107 and posts 106. It will be understood that the posts 106 and the trenches 107 that define the sidewalls 105 may be fabricated by selective etching and/or selective epitaxial growth and/or other conventional techniques. Moreover, it will also be understood that the sidewalls need not be orthogonal to the substrate 102, but 5 rather may be oblique thereto. Finally, it will also be understood that although the sidewalls 105 are shown in cross-section in Figure 1, the posts 106 and trenches 107 may define elongated regions that are straight, V-shaped or have other shapes. As shown in Figure 1, the trenches 107 may extend into the buffer layer 102b and into the substrate 102a, so that subsequent gallium nitride growth occurs preferentially on 10 the sidewalls 105 rather than on the trench floors. In other embodiments, the trenches may not extend into the substrate 102a, and also may not extend into buffer layer 102b. depending, for example, on the trench geometry and the lateral versus vertical growth rates of the gallium nitride. Referring now to Figure 2, the sidewalls 105 of the underlying gallium nitride 15 layer 104 are laterally grown to form a lateral gallium nitride layer 108a in the trenches 107. Lateral growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr. The precursors TEG at 13-39umol/min and NH3 at 1500 seem may be used in combination with a 3000 seem H2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be 20 used. As used herein, the term "lateral" means a direction that is orthogonal to the sidewalls 105. It will also be understood that some vertical growth on the posts 106 may also take place during the lateral growth from sidewalls 105. As used herein, the term "vertical" denotes a directional parallel to the sidewalls 105. Referring now to Figure 3, continued growth of the lateral gallium nitride 25 layer 108a causes vertical growth onto the underlying gallium nitride layer 104, specifically onto the posts 106, to form a vertical gallium nitride layer 108b. Growth conditions for vertical growth may be maintained as was described in connection with Figure 2. As also shown in Figure 3, continued vertical growth into trenches 107 may take place at the bottom of the trenches. 30 Referring now to Figure 4, growth is allowed to continue until the lateral growth fronts coalesce in the trenches 107 at the interfaces 108c, to form a continuous gallium nitride semiconductor layer in the trenches. The total growth time may be. approximately 60 minutes. As shown in Figure 5, microelectronic devices 110 may then be formed in the lateral gallium nitride semiconductor layer 108a. Devices may aiso be formed in vertical gallium nitride layer 108b. Accordingly, in Figure 5, gallium nitride semiconductor structures 100 according to a first embodiment of the present invention are illustrated. The gallium 5 nitride structures 100 include the substrate 102. The substrate may be sapphire or gallium nitride or other conventional substrates. However, preferably, the substrate includes the 6H-SiC(0001) substrate 102a and the aluminum nitride buffer layer 102b on the silicon carbide substrate 102a. The aluminum nitride buffer layer 102b may be 0.1 um thick. 10 The fabrication of the substrate 102 is well known to those having skill in the art and need not be described further. Fabrication of silicon carbide substrates are described, for example, in U.S. Patents 4,865,685 to Palmour; Re 34,861 to Davis et al.; 4,912,064 to Kong et al. and 4,946,547 to Palmour et al., the disclosures of which are hereby incorporated herein by reference. 15 The underlying gallium nitride layer 104 is also included on the buffer layer 102b opposite the substrate 102a. The underlying gallium nitride layer 104 may be between about 1.0 and 2.0um thick, and may be formed using metalorganic vapor phase epitaxy (MOVPE). The underlying gallium nitride layer generally has an undesired relatively high defect density. For example, dislocation densities of 20 between about 108 and 1010cm"2 may be present jn the underlying gallium nitride layer. These high defect densities may result from mismatches in lattice parameters between the buffer layer 102b and the underlying gallium nitride layer 104, and/or other causes. These high defect densities may impact the performance of microelectronic devices formed in the underlying gallium nitride layer 104. 25 Stih continuing with the description of Figure 5, the underlying gallium, nitride layer 104 includes the plurality of sidewails 105 that may be defined by the plurality of pedestals 106 and/or the plurality of trenches 107. As was described above, the sidewails may be oblique and of various elongated shapes. Continuing with the description of Figure 5, the lateral gallium nitride layer 30 108a extends from the plurality of sidewails 105 of the underlying gallium nitride layer 104. The lateral gallium nitride layer 108a may be formed using metalorganic vapor phase epitaxy at about 1000-1100°C and 45 Torr. Precursors of triethygallium (TEG) at 13-39umol/min and ammonia (NH3) at 1500 seem may be used in combination with a 3000 seem H2 diluent, to form the lateral gallium nitride layer 108a. Still continuing with the description of Figure 5, the gallium nitride semiconductor structure 100 also includes the vertical gallium nitride layer 108b that 5 extends vertically from the posts 106. As shown in Figure 5, the lateral gallium nitride layer 108a coalesces at the interfaces 108c to form a continuous lateral gallium nitride semiconductor layer 108a in the trenches. It has been found that the dislocation densities in the underlying gallium nitride layer 104 generally do not propagate laterally from the sidewalls 105 10 with the same density as vertically from the underlying gallium nitride layer 104. Thus, the lateral gallium nitride layer 108a can have a relatively low defect density, for example less that 104 cm"2. Accordingly, the lateral gallium nitride layer 108b may form device quality gallium nitride semiconductor material. Thus, as shown in Figure 5, microelectronic devices 110 may be formed in the lateral gallium nitride 15 semiconductor layer 108a. It will also be understood that a mask need not be used to fabricate the gallium nitride semiconductor structures 100 of Figure 5, because lateral growth is directed from the sidewalls 105. Referring now to Figures 6-10, second embodiments of gallium nitride semiconductor structures and fabrication methods according to the present invention 20 will now be described. First, gallium nitride semiconductor structures of Figure 4 are fabricated as was already described with regard to Figures 1-4. Then, referring to Figure 6, the posts 106 are masked with a mask 206 that includes an array of openings therein. The mask may comprise silicon dioxide at thickness of 1000 A and may be deposited using low pressure chemical vapor deposition at 410°C. Other masking 25 materials may be used. The mask may be patterned using standard photolithography techniques and etched in a buffered HF solution. In one embodiment, the openings are 3um-wide openings that extend in parallel at distances of between 3 and 40pm and that are oriented along the direction on the lateral gallium nitride layer 108a. Prior to further processing, the structure may be dipped in a 50% hydrochloric 30 acid (HCl) solution to remove surface oxides. It will be understood that although the mask 206 is preferably located above the posts 106, it can also be offset therefrom. Referring now to Figure 7, the lateral gallium nitride semiconductor layer -108a is grown through the array of openings to form a vertical gallium nitride layer 208a in the openings. Growth of gallium nitride may be obtained, as was described in connection with Figure 2. It will be understood that growth in two dimensions may be used to form an overgrown gallium nitride semiconductor layer. Specifically, the mask 206 may be 5 patterned to include an array of openings that extend along two orthogonal directions such as and . Thus, the openings can form a rectangle of orthogonal striped patterns. In this case, the ratio of the edges of the rectangle is preferably proportional to the ratio of the growth rates of the {1120} and {1101} facets, for example, in a ratio of 1.4:1. The openings can be equitriangular with 10 respect to directions such as and . Referring now to Figure 8, continued growth of the vertical gallium nitride layer 208a causes lateral growth onto the mask 206. to form a second lateral gallium nitride layer 208b. Conditions for overgrowth may be maintained as was described in connection with Figure 7. 15 Referring now to Figure 9, lateral overgrowth is allowed to continue until the lateral growth fronts coalesce at the second interfaces 208c on the mask 206 to form a continuous overgrown gallium nitride semiconductor layer 208. The total growth time may be approximately sixty minutes. As shown in Figure 10, microelectronic devices 210 may then be formed in the second lateral gallium nitride layer 208b. The 20 microelectronic devices may also be formed in the vertical gallium nitride layer 208a. Accordingly, by providing the second lateral growth layer 208b', defects that were present in continuous gallium nitride semiconductor layer 108 may be reduced even further, to obtain device quality gallium nitride in the gallium nitride semiconductor structure 200. 25 Referring now to Figures 11-15, third embodiments of gallium nitride semiconductor structures and fabrication methods according to the present invention will now be described. First, gallium nitride semiconductor structures of Figure 4 are fabricated as was already described in connection with Figures 1-4. Then, a plurality of second sidewalls 305 are formed. The second sidewalls 305 may be formed by 30 selective epitaxial growth of second posts 306 by etching second trenches 307 in the first posts 106 and/or combinations thereof. As was already described, the second sidewalls 305 need not be orthogonal to substrate 102, but rather may be oblique. The second trenches 307 need not be directly over the first posts 106, but may be laterally offset therefrom. The second trenches are preferably deep so that lateral growth preferentially occurs on the sidewalis 305 rather than on the bottom of second trenches 306. 5 Referring now to Figure 12, the second sidewalis 305 of the second posts 306 and/or the second trenches 307 are laterally grown to form a second lateral gallium nitride layer 308a in the second trenches 307. As was already described, lateral growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr. The precursors TEG at 13-39umol/min and NH3 at 1500 seem may be used in 10 combination with a 3000 seem Hb diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used. It will also be understood that some vertical growth may take place on the second posts 306 during the lateral growth from the second sidewalis 305. Referring now to Figure 13, continued growth of the second lateral gallium 15 nitride layer 308a causes vertical growth onto the second posts 306, to form a second vertical gallium nitride layer 308b. As also shown, vertical growth from the floors of the second trenches and from the tops of the second posts may also take place. Growth conditions for vertical growth may be maintained as was described in connection with Figure 12. 20 Referring now to Figure 14, growth is allowed to continue until the lateral growth fronts coalesce in the second trenches 307 at the second interfaces 308c to form a second continuous gallium nitride semiconductor layer 308. The total growth time may be approximately sixty minutes. As shown in Figure 15, microelectronic devices 310 may then be formed in the second continuous gallium nitride 25 semiconductor layer 308. Accordingly, third embodiments of gallium nitride semiconductor structures 300 according to the present invention may be formed without the need to mask gallium nitride for purposes of defining lateral growth. Rather, lateral growth from first and second sidewalis may be used. By performing two separate lateral growths, 30 the defect density may be reduced considerably. Additional discussion of mefhods and structures of the present invention will now be provided. The first and second trenches 107 and 307 and the openings in the mask 206 are preferably rectangular trenches and openings that preferably extend along the and/or directions on the underlying gallium nitride layer 104 or the first lateral gallium nitride layer 108a. Truncated triangular stripes having (1101) slant facets and a narrow (0001) top facet may be obtained for trenches and/or mask openings along the direction. Rectangular stripes 5 having a (0001) top facet, (1120) vertical side faces and (1 1 01) slant facets may be grown along the direction. For growth times up to 3 minutes, similar morphologies may be obtained regardless of orientation. The stripes develop into different shapes if the growth is continued. The amount of lateral growth generally exhibits a strong dependence on trench 10 and/or mask opening orientation. The lateral growth rate of the oriented trenches and/or mask openings is generally much faster than those along . Accordingly, it is most preferred to orient the trenches and/or mask openings, so that they extend along the direction of the underlying gallium nitride layer 104 or the first lateral gallium nitride layer 108a. 15 The different morphological development as a function of trench and/or mask opening orientation appears to be related to the stability of the crystallographic planes in the gallium nitride structure. Trenches and/or mask openings oriented along may have wide (1 1 00) slant facets and either a very narrow or no (0001) top facet depending on the growth conditions. This may be because (1 101) is the 20 most stable plane in the gallium nitride wurtzite crystal structure, and the growth rate of this plane is lower than that of others. The {llOl} planes of the oriented trenches and/or mask openings may be wavy, which implies the existence of more than one Miller index. It appears that competitive growth of selected {1 101} planes occurs during the deposition which causes these planes to become unstable and 25 which causes their growth rate to increase relative to that of the (1 101) of trenches and/or mask openings oriented along . The morphologies of the gallium nitride layers selectively grown from trenches and/or mask openings oriented along are also generally a strong function of the growth temperatures. Layers grown at 1000°C may possess a truncated 30 triangular shape. This morphology may gradually change to a rectangular cross- " section as the growth temperature is increased. This shape change may occur as a result of the increase in the diffusion coefficient and therefore the flux of the gallium species along the (0001) top plane onto the {1 T01} planes with an increase in growth temperature. This may result in a decrease in the growth rate of the (0001) plane and an increase in that of the (1 101}. This phenomenon has also been observed in the 5 selective growth of gallium arsenide on silicon dioxide. Accordingly, temperatures of 1100°C appear to be most preferred. The morphological development of the gallium nitride regions also appears to depend on the flow rate of the TEG. An increase in the supply of TEG generally increases the growth rate in both the lateral and the vertical directions. However, the 10 lateral/vertical growth rate ratio decrease from 1.7 at the TEG flow rate of 13umol/min to 0.86 at 39umol.min. This increased influence on growth rate along relative to that of with TEG flow rate may be related to the type of reactor employed, wherein the reactant gases flow vertically and perpendicular to the substrate. The considerable increase in the concentration of the gallium species on the 15 surface may sufficiently impede their diffusion to the (1 1 01} planes such that chemisorption and gallium nitride growth occur more readily on the (0001) plane. Continuous 2um thick gallium nitride semiconductor layers may be obtained using 3um wide trenches and/or mask openings spaced 7um apart and oriented along , at 1100°C and a TEG flow rate of 26umol/min. The continuous gallium 20 nitride semiconductor layers may include subsurface voids that form when two growth fronts coalesce. These voids may occur most often using lateral growth conditions wherein rectangular trenches and/or mask openings having vertical (1120} side facets developed. The continuous gallium nitride semiconductor layers may have a 25 microscopically flat and pit-free surface. The surfaces of the laterally grown gallium nitride layers may include a terrace structure having an average step height of 0.32nm. This terrace structure may be related to the laterally grown gallium nitride, because it is generally not included in much larger area films grown only on aluminum nitride buffer layers. The average RMS roughness values may be similar to the values 30 obtained for the underlying gallium nitride layer 104. Threading dislocations, originating from the interface between the underlying gallium nitride layer 104 and the buffer layer 102b, appear to propagate to the top surface of the underlying gallium nitride layer 104. The dislocation density within these regions is approximately 10 cm" . By contrast, threading dislocations do not appear to readily propagate laterally. Rather, the lateral gallium nitride regions 108a and 308a contain only a few dislocations. These few dislocations may be formed 5 parallel to the (0001) plane via the extension of the vertical threading dislocations after a 90° bend in the regrown region. These dislocations do not appear to propagate to the top surface of the overgrown gallium nitride layer. As described, the formation mechanism of the selectively grown gallium nitride layers is lateral epitaxy. The two main stages of this mechanism are vertical 10 growth and lateral growth. During vertical growth through a mask, the deposited gallium nitride grows selectively within the mask openings more rapidly than it grows on the mask, apparently due to the much higher sticking coefficient, s, of the gallium atoms on the gallium nitride surface (s=l) compared to on the mask (s«l). Since the SiC>2 bond strength is 799.6 kJ/mole and much higher than that of Si-N (439 kJ/mole), 15 Ga-N (103 kJ/mole), and Ga-0 (353.6 kJ/mole), Ga or N atoms should not readily bond to the mask surface in numbers and for a time sufficient to cause gallium nitride nuclei to form. They would either evaporate or diffuse along the mask surface to the opening in the mask or to the vertical gallium nitride surfaces which have emerged. During lateral growth, the gallium nitride grows simultaneously both vertically and 20 laterally. Surface diffusion of gallium and nitrogen on the gallium nitride may play a role in gallium nitride selective growth. The major source of material appears to be derived from the gas phase. This may be demonstrated by the fact that an increase in the TEG flow rate causes the growth rate of the (0001) top facets to develop faster 25 than the (1 101) side facets and thus controls the lateral growth. The laterally grown gallium nitride bonds to the underlying mask sufficiently strongly so that it generally does not break away on cooling. However, lateral cracking within the SiO? mask may take place due to thermal stresses generated on cooling. The viscosity (p) of the SiCh at 1050°C is about lO13""1 poise which is one 30 order of magnitude greater than the strain point (about 101 " poise) where stress relief in a bulk amorphous material occurs within approximately six hours. Thus, the SiCb mask may provide limited compliance on cooling. As the atomic arrangement on the amorphous SiO2 surface is quite different from that on the GaN surface, chemical bonding may occur only when appropriate pairs of atoms are in close proximity. Extremely small relaxations of the silicon and oxygen and gallium and nitrogen atoms on the respective surfaces and/or within the bulk of the SiC2 may accommodate the gallium nitride and cause it to bond to the oxide. Accordingly, the embodiments of 5 Figures 1-5 and 11-15, which need not employ a mask, may be particularly advantageous. In conclusion, lateral epitaxial overgrowth may be obtained from sidewalls of an underlying gallium nitride layer via MOVPE. The growth may depend strongly on the sidewall orientation, growth temperature and TEG flow rate. Coalescence of 10 overgrown gallium nitride regions to form regions with both extremely low densities of dislocations and smooth and pit-free surfaces may be achieved through 3 urn wide trenches between 7 urn wide posts and extending along the direction, at 1100°C and a TEG flow rate of 26umol/min. The lateral overgrowth of gallium nitride from sidewalls via MOVPE may be used to obtain low defect density regions 15 for microelectronic devices, without the need to use masks. In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims. WE CLAIM: 1. A method of fabricating a gallium nitride semiconductor layer comprising the steps of: laterally growing at least one sidewall of an underlying gallium nitride layer into at least one trench in the underlying gallium nitride layer to thereby form a lateral gallium nitride semiconductor layer. 2. A method as claimed in claim 1, wherein the laterally growing step is followed by the step of forming microelectronic devices in the lateral gallium nitride semiconductor layer. 3. A method as claimed in claim 1, wherein the laterally growing step comprises the step of growing a pair of sidewalls of the underlying gallium nitride layer into a trench in the underlying gallium nitride layer between the pair of sidewalls until the grown pair of sidewalls coalesce in the trench. 4. A method as claimed in claim 1, wherein the laterally growing step comprises the step of laterally growing the sidewall of the underlying gallium nitride layer using metalorganic vapor phase epitaxy. 5. A method as claimed in claim 1, wherein the laterally growing step is preceded by the step of forming the underlying gallium nitride layer including the sidewall on a substrate. 6. A method as claimed in claim 5, wherein the forming step comprises the steps of: forming a buffer layer on a substrate; and forming the underlying gallium nitride layer on the buffer layer opposite the substrate. 7. A method as claimed in claim 5, wherein the forming step comprises the step of forming the trench in the underlying gallium nitride layer, the trench including the sidewall. 8. A method as claimed in claim 5, wherein the forming step comprises the step of forming a post on the underlying gallium nitride layer, the post including the sidewall and defining the trench. 9. A method as claimed in claim 1, wherein the underlying gallium nitride layer includes a predetermined defect density and wherein the step of laterally growing a sidewall of an underlying gallium nitride layer into a trench in the underlying gallium nitride layer to thereby form a lateral gallium nitride layer comprises the steps of: laterally growing the sidewall of the underlying gallium nitride layer to thereby form the lateral gallium nitride layer of lower defect density than the predetermined defect density; and vertically growing the lateral gallium nitride layer while propagating the lower defect density. 10. A method as claimed in claim 1, wherein the growing step comprises the step of growing the sidewall of the underlying gallium nitride layer using metalorganic vapor phase epitaxy of triethylgallium at 13-39\|umol/min and ammonia at 1500 seem at a temperature of 1000°C-1100°C. 11. A method as claimed in claim 7, wherein the trench forming step comprises the step of selectively etching the underlying gallium nitride layer to form the trench that includes the sidewall. 12. A method as claimed in claim 8, wherein the post forming step comprises the step of selectively growing the underlying gallium nitride layer to form the post including the sidewall. 13. A method as claimed in claim 1, wherein the step of laterally growing comprises: laterally growing a plurality of sidewalls of an underlying gallium nitride layer into a plurality of trenches in the underlying gallium nitride layer to thereby form a lateral gallium nitride layer. 14. A method as claimed in claim 13, wherein the laterally growing step is followed by the steps of: making the lateral gallium nitride layer with a mask that includes an array of openings therein; and growing the lateral gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. 15. A method as claimed in claim 13, wherein the growing step is followed by the steps of: vertically growing the lateral gallium nitride layer, forming a plurality of second sidewalls in the vertically grown lateral gallium nitride layer to define a plurality of second trenches; and laterally growing the plurality of second sidewalls of the vertically grown lateral gallium nitride layer into the plurality of second trenches, to thereby form a second lateral gallium nitride semiconductor layer. 16. A method as claimed in claim 14 , wherein the laterally growing step is followed by the step of forming microelectronic devices in the overgrown gallium nitride semiconductor layer. 17. A method as claimed in claim 15, wherein the step of laterally growing the plurality of second sidewalls is followed by the step of forming microelectronic devices in the second lateral gallium nitride semiconductor layer. 18. A method as claimed in claim 13, wherein the laterally growing step comprises the step of growing the plurality of .sidewalls of the underlying gallium nitride layer into the plurality of trenches in the underlying gallium nitride layer until the plurality of grown sidewalls coalesce in the trenches. 19. A method as claimed in claim 14, wherein the growing step comprises the step of growing the lateral gallium nitride layer through the array of openings and onto the mask until the grown lateral gallium nitride layer coalesces on the mask to form a continuous overgrown gallium nitride semiconductor layer. 20. A method as claimed in claim 15, wherein the step of laterally growing the plurality of second sidewalls comprises the step of laterally growing the plurality of second sidewalls of the vertically grown lateral gallium nitride layer into the plurality of second trenches until the plurality of laterally grown second sidewalls coalesce in the plurality of second trenches. 21. A method as claimed in claim 13, wherein the laterally growing step comprises the step of laterally growing the plurality of sidewalls of the underlying gallium nitride layer using metalorganic vapour phase epitaxy. 22. A method as claimed in claim 13, wherein the laterally growing step is preceded by the step of forming the underlying gallium nitride layer including the plurality of sidewalls on a substrate. 23. A method as claimed in claim 22, wherein the forming step comprises the steps of: forming a buffer layer on a substrate; and forming the underlying gallium nitride layer on the buffer layer opposite the substrate. 24. A method as claimed in claim 22, wherein the forming step comprises the step of forming the plurality of trenches in the underlying gallium nitride layer, the plurality of trenches including the plurality of sidewalls. 25. A method as claimed in claim 22, wherein the forming step comprises the step of forming a plurality of posts in the underlying gallium nitride layer, the plurality of posts including the plurality of sidewalls and defining the plurality of trenches. 26. A method as claimed in claim 13, wherein the underlying gallium nitride layer includes a predetermined defect density, and wherein the step of laterally growing a plurality of sidewalls of the underlying gallium nitride layer into the plurality of trenches in the underlying gallium nitride layer to thereby form a lateral gallium nitride layer comprises the steps of: laterally growing the plurality of sidewalls of the underlying gallium nitride layer into the plurality of trenches to thereby form a lateral gallium nitride semiconductor layer of lower defect density than the predetermined defect density; and vertically growing the laterally gallium nitride layer while propagating the lower defect density. A method as claimed in claim 13, wherein the laterally growing step comprises the step of laterally growing the plurality of sidewalls of the underlying gallium nitride layer using metalorganic vapor phase epitaxy of triethylgallium at 13-39umol/min and ammonia at 1500 seem at a temperature of 1000°C -1100°C. Dated this 31st day of October, 2000. (SANJAY KUMAR)-Of REMFRY & SAGAR ATTORNEY FOR THE APPLICANTS

Full Text

FORM 2
THE PATENTS ACT 1970 [39 OF 1970]
COMPLETE SPECIFICATION
[See Section 10]
"FABRICATION OF GALLIUM NITRJPE SEMICONDUCTOR LAYERS BY LATERAklaROWTH FROM TRENCH SIDEWALLS"

NORTH CAROLINA STATE UNIVERSITY, of 1 Holladay Hall, Campus Box 7003, Raleigh, North Carolina 27695-7003, United States of America,

The following specification particularly describes the nature of the invention and the manner in which it is to be performed:-

Field of the Invention
This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor. 5
Background of the Invention Gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium
10 nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
A major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium
15 nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable.
20 It is also known to fabricate gallium nitride structures through openings in a
mask. For example, in fabricating field emitter arrays, it is known to selectively grow gallium nitride on stripe or circular patterned substrates. See, for example, the publications by Nam et al. entitled "Selective Growth o/GaN and AIo.jGao.sN on GaN/AlN/6H-SiC(0001) Multilayer Substrates Via Organometallic Vapor Phase
25 Epitaxy", Proceedings of the Materials Research Society, December 1996, and
"Growth of GaN and Alo.7Gao.3Non PatterenedSubstrates via Organometallic Vapor Phase Epitaxy", Japanese Journal of Applied Physics., Vol. 36, Part 2, No. 5A, May

1997, pp. L532-L535. As disclosed in these publications, undesired ridge growth or lateral overgrowth may occur under certain conditions.
Summary of the Invention
5 It is therefore an object of the present invention to provide improved methods
of fabricating gallium nitride semiconductor layers, and improved gallium nitride layers so fabricated.
It is another object of the invention to provide methods of fabricating gallium nitride semiconductor layers that can have low defect densities, and gallium nitride
10 semiconductor layers so fabricated.
These and other objects are provided, according to the present invention by laterally growing a sidewall of an underlying gallium nitride layer into a trench in the underlying gallium nitride layer, to thereby form a lateral gallium nitride layer. Microelectronic devices may then be formed in the lateral gallium nitride layer.
15 It has been found, according to the present invention, that dislocation defects
do not significantly propagate laterally from the sidewall into the trench in the underlying gallium nitride layer, so that the lateral gallium nitride semiconductor layer is relatively defect free. The sidewall growth may be accomplished without the need to mask portions of the underlying gallium nitride layer during growth of the
20 lateral gallium nitride layer.
According to another aspect of the present invention, a pair of sidewalls of the underlying gallium nitride layer are laterally grown into a trench in the underlying gallium nitride layer between the pair of sidewalls until the grown sidewalls coalesce in the trench. The lateral gallium nitride semiconductor layer may be laterally grown
25 using metalorganic vapor phase epitaxy (MOVPE). For example, the lateral gallium nitride layer may be laterally grown using triethylgallium (TEG) and ammonia (NH3) precursors at 1000-1100°C and 45 Torr. Preferably, TEG at 13-39umol/min and NH3 at 1500 seem are used in combination with 3000 seem H2 diluent. Most preferably, TEG at 26umol/min, NH3 at 1500 seem and H2 at 3000 seem at a temperature of
30 1100°C and 45 Torr are used. The underlying gallium nitride layer preferably is
formed on a substrate such as 6H-SiC(0001), which itself includes a buffer layer such as aluminum nitride thereon. Other substrates such as sapphire, and other buffer .

layers such as low temperature gallium nitride, may be used. Multiple substrate layers and buffer layers also may be used.
The underlying gallium nitride layer including the sidewall may be formed by forming the trench in the underlying gallium nitride layer, such that the trench 5 includes the sidewall. Alternatively, the sidewall may be formed by forming a post on the underlying gallium nitride layer, the post including the sidewall and defining the trench. A series of alternating trenches and posts is preferably formed to form a plurality of sidewalls. Trenches and/or posts may be formed by selective etching, selective epitaxial growth, combinations of etching and growth, or other techniques.
10 The trenches may extend into the buffer layer and into the substrate.
The sidewall of the underlying gallium nitride layer is laterally grown into the trench, to thereby form the lateral gallium nitride layer of lower defect density than the defect density of the underlying gallium nitride layer. Some vertical growth may also occur. The laterally grown gallium nitride layer is vertically grown while
15 propagating the lower defect density. Vertical growth may also take place simultaneous with the lateral growth.
The defect density of the overgrown gallium nitride semiconductor layer may be further decreased by growing a second gallium nitride semiconductor layer from the lateral gallium nitride layer. In one embodiment, the lateral gallium nitride layer
20 is masked with a mask that includes an array of openings therein. The lateral gallium nitride layer is grown through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. In another embodiment, the lateral gallium nitride layer is grown vertically. A plurality of second sidewalls are formed in the vertically grown lateral gallium nitride layer to define a plurality of
25 second trenches. The plurality of second sidewalls of the vertically grown lateral
gallium nitride layer are then laterally grown into the plurality of second trenches, to thereby form a second lateral gallium nitride layer. Microelectronic devices are then formed in the gallium nitride semiconductor layer. The plurality of sidewalls of the underlying gallium nitride layer may be grown using metalorganic vapor phase
30 epitaxy as was described above. The second sidewalls may be grown by etching and/or selective epitaxial growth of trenches and/or posts, as was described above.
Gallium nitride semiconductor structures according to the invention comprise an underlying gallium nitride layer including a trench having a sidewall. and a lateral

gallium nitride layer that extends from the sidewall of the underlying gallium nitride layer into the trench. A vertical gallium nitride layer extends from the lateral gallium nitride layer. A plurality of microelectronic devices are included in the vertical gallium nitride layer. A series of alternating trenches and posts may be provided to 5 define a plurality of sidewalls. The underlying gallium nitride layer includes a
predetermined defect density, and the lateral gallium nitride, layer is of lower defect density than the predetermined defect density.
Other embodiments of gaih'um nitride semiconductor structures according to the invention comprise a mask including an array of openings therein on the lateral
10 gallium nitride layer and a vertical gallium nitride layer that extends from the lateral gallium nitride layer through the openings and onto the mask. Alternatively, a vertical gallium nitride layer extends from the lateral gallium nitride layer and includes a plurality of second sidewalls therein. A second lateral gallium nitride layer extends from the plurality of second sidewalls. Microelectronic devices are included
15 in the second lateral gallium nitride layer. Accordingly, low defect density gallium nitride semiconductor layers may be produced, to thereby allow the production of high performance microelectronic devices.
Brief Description of the Drawings
20 Figures 1-5 are cross-sectional views of first embodiments of gallium nitride
semiconductor structures during intermediate fabrication steps according to the present invention.
Figures 6-10 are cross-sectional views of second embodiments of gallium nitride semiconductor structures during intermediate fabrication steps according to the 25 present. invention.
Figures 11-15 are cross-sectional views of third embodiments of gallium nitride semiconductor structures during intermediate fabrication steps according to the present invention.
30 Detailed Description of Preferred Embodiments
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the . invention are shown. This invention may, however, be embodied in many different

forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like 5 numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "onto" another element, it can be directly on the other element or intervening elements may also be present. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well.
10 Referring now to Figures 1-5, methods of fabricating gallium nitride
semiconductor structures according to a first embodiment of the present invention will now be described. As shown in Figure 1, an underlying gallium nitride layer 104 is grown on a substrate 102. The substrate 102 may include a 6H-SiC(0001) substrate 102a and an aluminum nitride buffer layer 102b. The crystallographic designation
15 conventions used herein are well known to those having skill in the art, and need not be described further. The gallium nitride layer 104 may be between 1.0 and 2.0um thick, and may be grown at 1000°C on a high temperature (1100°C) aluminum nitride buffer layer 102b that was deposited on the 6H-SiC substrate 102a in a cold wall vertical and inductively heated metalorganic vapor phase epitaxy system using
20- triethylgallium at 26umol/min, ammonia at 1500 seem and 3000 seem hydrogen
diluent. Additional details of this growth technique may be found in a publication by T.W. Weeks et al. entitled "GaN Thin Films Deposited Via Organometallic Vapor Phase Epitaxy on a(6H)-SiC(0001) Using High-Temperature Monocrystalline AIN Buffer Layers", Applied Physics Letters, Vol. 67, No. 3, July 17, 1995, pp. 401-403,
25 the disclosure of which is hereby incorporated herein by reference. Other substrates, with or without buffer layers, may be used.
Still referring to Figure 1, the underlying gallium nitride layer 104 includes a plurality of sidewalls 105 therein. It will be understood by those having skill in the art that the sidewalls 105 may be thought of as being defined by a plurality of spaced
30 apart posts 106, that also may be referred to as "mesas", "pedestals" or "columns". The sidewalls 105 may also be thought of as being defined by a plurality of trenches 107, also referred to as "wells" in the underlying gallium nitride layer 104. The sidewalls 105 may also be thought of as being defined by a series of alternating

trenches 107 and posts 106. It will be understood that the posts 106 and the trenches 107 that define the sidewalls 105 may be fabricated by selective etching and/or selective epitaxial growth and/or other conventional techniques. Moreover, it will also be understood that the sidewalls need not be orthogonal to the substrate 102, but 5 rather may be oblique thereto. Finally, it will also be understood that although the sidewalls 105 are shown in cross-section in Figure 1, the posts 106 and trenches 107 may define elongated regions that are straight, V-shaped or have other shapes. As shown in Figure 1, the trenches 107 may extend into the buffer layer 102b and into the substrate 102a, so that subsequent gallium nitride growth occurs preferentially on
10 the sidewalls 105 rather than on the trench floors. In other embodiments, the trenches may not extend into the substrate 102a, and also may not extend into buffer layer 102b. depending, for example, on the trench geometry and the lateral versus vertical growth rates of the gallium nitride.
Referring now to Figure 2, the sidewalls 105 of the underlying gallium nitride
15 layer 104 are laterally grown to form a lateral gallium nitride layer 108a in the
trenches 107. Lateral growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr. The precursors TEG at 13-39umol/min and NH3 at 1500 seem may be used in combination with a 3000 seem H2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be
20 used. As used herein, the term "lateral" means a direction that is orthogonal to the sidewalls 105. It will also be understood that some vertical growth on the posts 106 may also take place during the lateral growth from sidewalls 105. As used herein, the term "vertical" denotes a directional parallel to the sidewalls 105.
Referring now to Figure 3, continued growth of the lateral gallium nitride
25 layer 108a causes vertical growth onto the underlying gallium nitride layer 104,
specifically onto the posts 106, to form a vertical gallium nitride layer 108b. Growth conditions for vertical growth may be maintained as was described in connection with Figure 2. As also shown in Figure 3, continued vertical growth into trenches 107 may take place at the bottom of the trenches.
30 Referring now to Figure 4, growth is allowed to continue until the lateral
growth fronts coalesce in the trenches 107 at the interfaces 108c, to form a continuous gallium nitride semiconductor layer in the trenches. The total growth time may be. approximately 60 minutes. As shown in Figure 5, microelectronic devices 110 may

then be formed in the lateral gallium nitride semiconductor layer 108a. Devices may aiso be formed in vertical gallium nitride layer 108b.
Accordingly, in Figure 5, gallium nitride semiconductor structures 100 according to a first embodiment of the present invention are illustrated. The gallium 5 nitride structures 100 include the substrate 102. The substrate may be sapphire or gallium nitride or other conventional substrates. However, preferably, the substrate includes the 6H-SiC(0001) substrate 102a and the aluminum nitride buffer layer 102b on the silicon carbide substrate 102a. The aluminum nitride buffer layer 102b may be 0.1 um thick.
10 The fabrication of the substrate 102 is well known to those having skill in the
art and need not be described further. Fabrication of silicon carbide substrates are described, for example, in U.S. Patents 4,865,685 to Palmour; Re 34,861 to Davis et al.; 4,912,064 to Kong et al. and 4,946,547 to Palmour et al., the disclosures of which are hereby incorporated herein by reference.
15 The underlying gallium nitride layer 104 is also included on the buffer layer
102b opposite the substrate 102a. The underlying gallium nitride layer 104 may be between about 1.0 and 2.0um thick, and may be formed using metalorganic vapor phase epitaxy (MOVPE). The underlying gallium nitride layer generally has an undesired relatively high defect density. For example, dislocation densities of
20 between about 108 and 1010cm"2 may be present jn the underlying gallium nitride
layer. These high defect densities may result from mismatches in lattice parameters between the buffer layer 102b and the underlying gallium nitride layer 104, and/or other causes. These high defect densities may impact the performance of microelectronic devices formed in the underlying gallium nitride layer 104.
25 Stih continuing with the description of Figure 5, the underlying gallium, nitride
layer 104 includes the plurality of sidewails 105 that may be defined by the plurality of pedestals 106 and/or the plurality of trenches 107. As was described above, the sidewails may be oblique and of various elongated shapes.
Continuing with the description of Figure 5, the lateral gallium nitride layer
30 108a extends from the plurality of sidewails 105 of the underlying gallium nitride layer 104. The lateral gallium nitride layer 108a may be formed using metalorganic vapor phase epitaxy at about 1000-1100°C and 45 Torr. Precursors of triethygallium (TEG) at 13-39umol/min and ammonia (NH3) at 1500 seem may be used in

combination with a 3000 seem H2 diluent, to form the lateral gallium nitride layer 108a.
Still continuing with the description of Figure 5, the gallium nitride semiconductor structure 100 also includes the vertical gallium nitride layer 108b that 5 extends vertically from the posts 106.
As shown in Figure 5, the lateral gallium nitride layer 108a coalesces at the interfaces 108c to form a continuous lateral gallium nitride semiconductor layer 108a in the trenches. It has been found that the dislocation densities in the underlying gallium nitride layer 104 generally do not propagate laterally from the sidewalls 105
10 with the same density as vertically from the underlying gallium nitride layer 104. Thus, the lateral gallium nitride layer 108a can have a relatively low defect density, for example less that 104 cm"2. Accordingly, the lateral gallium nitride layer 108b may form device quality gallium nitride semiconductor material. Thus, as shown in Figure 5, microelectronic devices 110 may be formed in the lateral gallium nitride
15 semiconductor layer 108a. It will also be understood that a mask need not be used to fabricate the gallium nitride semiconductor structures 100 of Figure 5, because lateral growth is directed from the sidewalls 105.
Referring now to Figures 6-10, second embodiments of gallium nitride semiconductor structures and fabrication methods according to the present invention
20 will now be described. First, gallium nitride semiconductor structures of Figure 4 are fabricated as was already described with regard to Figures 1-4. Then, referring to Figure 6, the posts 106 are masked with a mask 206 that includes an array of openings therein. The mask may comprise silicon dioxide at thickness of 1000 A and may be deposited using low pressure chemical vapor deposition at 410°C. Other masking
25 materials may be used. The mask may be patterned using standard photolithography techniques and etched in a buffered HF solution. In one embodiment, the openings are 3um-wide openings that extend in parallel at distances of between 3 and 40pm
and that are oriented along the direction on the lateral gallium nitride layer 108a. Prior to further processing, the structure may be dipped in a 50% hydrochloric 30 acid (HCl) solution to remove surface oxides. It will be understood that although the mask 206 is preferably located above the posts 106, it can also be offset therefrom. Referring now to Figure 7, the lateral gallium nitride semiconductor layer -108a is grown through the array of openings to form a vertical gallium nitride layer

208a in the openings. Growth of gallium nitride may be obtained, as was described in connection with Figure 2.
It will be understood that growth in two dimensions may be used to form an overgrown gallium nitride semiconductor layer. Specifically, the mask 206 may be 5 patterned to include an array of openings that extend along two orthogonal directions
such as and . Thus, the openings can form a rectangle of orthogonal striped patterns. In this case, the ratio of the edges of the rectangle is
preferably proportional to the ratio of the growth rates of the {1120} and {1101} facets, for example, in a ratio of 1.4:1. The openings can be equitriangular with
10 respect to directions such as and .
Referring now to Figure 8, continued growth of the vertical gallium nitride layer 208a causes lateral growth onto the mask 206. to form a second lateral gallium nitride layer 208b. Conditions for overgrowth may be maintained as was described in connection with Figure 7.
15 Referring now to Figure 9, lateral overgrowth is allowed to continue until the
lateral growth fronts coalesce at the second interfaces 208c on the mask 206 to form a continuous overgrown gallium nitride semiconductor layer 208. The total growth time may be approximately sixty minutes. As shown in Figure 10, microelectronic devices 210 may then be formed in the second lateral gallium nitride layer 208b. The
20 microelectronic devices may also be formed in the vertical gallium nitride layer 208a. Accordingly, by providing the second lateral growth layer 208b', defects that were present in continuous gallium nitride semiconductor layer 108 may be reduced even further, to obtain device quality gallium nitride in the gallium nitride semiconductor structure 200.
25 Referring now to Figures 11-15, third embodiments of gallium nitride
semiconductor structures and fabrication methods according to the present invention will now be described. First, gallium nitride semiconductor structures of Figure 4 are fabricated as was already described in connection with Figures 1-4. Then, a plurality of second sidewalls 305 are formed. The second sidewalls 305 may be formed by
30 selective epitaxial growth of second posts 306 by etching second trenches 307 in the first posts 106 and/or combinations thereof. As was already described, the second sidewalls 305 need not be orthogonal to substrate 102, but rather may be oblique. The

second trenches 307 need not be directly over the first posts 106, but may be laterally
offset therefrom. The second trenches are preferably deep so that lateral growth
preferentially occurs on the sidewalis 305 rather than on the bottom of second
trenches 306.
5 Referring now to Figure 12, the second sidewalis 305 of the second posts 306
and/or the second trenches 307 are laterally grown to form a second lateral gallium nitride layer 308a in the second trenches 307. As was already described, lateral growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr. The precursors TEG at 13-39umol/min and NH3 at 1500 seem may be used in
10 combination with a 3000 seem Hb diluent. If gallium nitride alloys are formed,
additional conventional precursors of aluminum or indium, for example, may also be used. It will also be understood that some vertical growth may take place on the second posts 306 during the lateral growth from the second sidewalis 305.
Referring now to Figure 13, continued growth of the second lateral gallium
15 nitride layer 308a causes vertical growth onto the second posts 306, to form a second vertical gallium nitride layer 308b. As also shown, vertical growth from the floors of the second trenches and from the tops of the second posts may also take place. Growth conditions for vertical growth may be maintained as was described in connection with Figure 12.
20 Referring now to Figure 14, growth is allowed to continue until the lateral
growth fronts coalesce in the second trenches 307 at the second interfaces 308c to form a second continuous gallium nitride semiconductor layer 308. The total growth time may be approximately sixty minutes. As shown in Figure 15, microelectronic devices 310 may then be formed in the second continuous gallium nitride
25 semiconductor layer 308.
Accordingly, third embodiments of gallium nitride semiconductor structures 300 according to the present invention may be formed without the need to mask gallium nitride for purposes of defining lateral growth. Rather, lateral growth from first and second sidewalis may be used. By performing two separate lateral growths,
30 the defect density may be reduced considerably.
Additional discussion of mefhods and structures of the present invention will now be provided. The first and second trenches 107 and 307 and the openings in the mask 206 are preferably rectangular trenches and openings that preferably extend

along the and/or directions on the underlying gallium nitride layer 104 or the first lateral gallium nitride layer 108a. Truncated triangular stripes
having (1101) slant facets and a narrow (0001) top facet may be obtained for
trenches and/or mask openings along the direction. Rectangular stripes
5 having a (0001) top facet, (1120) vertical side faces and (1 1 01) slant facets may be
grown along the direction. For growth times up to 3 minutes, similar morphologies may be obtained regardless of orientation. The stripes develop into different shapes if the growth is continued.
The amount of lateral growth generally exhibits a strong dependence on trench
10 and/or mask opening orientation. The lateral growth rate of the oriented trenches and/or mask openings is generally much faster than those along . Accordingly, it is most preferred to orient the trenches and/or mask openings, so that they extend along the direction of the underlying gallium nitride layer 104 or the first lateral gallium nitride layer 108a.
15 The different morphological development as a function of trench and/or mask
opening orientation appears to be related to the stability of the crystallographic planes in the gallium nitride structure. Trenches and/or mask openings oriented along
may have wide (1 1 00) slant facets and either a very narrow or no (0001)
top facet depending on the growth conditions. This may be because (1 101) is the 20 most stable plane in the gallium nitride wurtzite crystal structure, and the growth rate of this plane is lower than that of others. The {llOl} planes of the oriented trenches and/or mask openings may be wavy, which implies the existence of more than one Miller index. It appears that competitive growth of selected {1 101} planes occurs during the deposition which causes these planes to become unstable and 25 which causes their growth rate to increase relative to that of the (1 101) of trenches
and/or mask openings oriented along .
The morphologies of the gallium nitride layers selectively grown from trenches and/or mask openings oriented along are also generally a strong function of the growth temperatures. Layers grown at 1000°C may possess a truncated 30 triangular shape. This morphology may gradually change to a rectangular cross- " section as the growth temperature is increased. This shape change may occur as a

result of the increase in the diffusion coefficient and therefore the flux of the gallium species along the (0001) top plane onto the {1 T01} planes with an increase in growth temperature. This may result in a decrease in the growth rate of the (0001) plane and an increase in that of the (1 101}. This phenomenon has also been observed in the 5 selective growth of gallium arsenide on silicon dioxide. Accordingly, temperatures of 1100°C appear to be most preferred.
The morphological development of the gallium nitride regions also appears to depend on the flow rate of the TEG. An increase in the supply of TEG generally increases the growth rate in both the lateral and the vertical directions. However, the 10 lateral/vertical growth rate ratio decrease from 1.7 at the TEG flow rate of
13umol/min to 0.86 at 39umol.min. This increased influence on growth rate along relative to that of with TEG flow rate may be related to the type of reactor employed, wherein the reactant gases flow vertically and perpendicular to the substrate. The considerable increase in the concentration of the gallium species on the
15 surface may sufficiently impede their diffusion to the (1 1 01} planes such that
chemisorption and gallium nitride growth occur more readily on the (0001) plane.
Continuous 2um thick gallium nitride semiconductor layers may be obtained using 3um wide trenches and/or mask openings spaced 7um apart and oriented along , at 1100°C and a TEG flow rate of 26umol/min. The continuous gallium
20 nitride semiconductor layers may include subsurface voids that form when two growth fronts coalesce. These voids may occur most often using lateral growth
conditions wherein rectangular trenches and/or mask openings having vertical (1120} side facets developed.
The continuous gallium nitride semiconductor layers may have a 25 microscopically flat and pit-free surface. The surfaces of the laterally grown gallium nitride layers may include a terrace structure having an average step height of 0.32nm. This terrace structure may be related to the laterally grown gallium nitride, because it is generally not included in much larger area films grown only on aluminum nitride buffer layers. The average RMS roughness values may be similar to the values 30 obtained for the underlying gallium nitride layer 104.
Threading dislocations, originating from the interface between the underlying gallium nitride layer 104 and the buffer layer 102b, appear to propagate to the top

surface of the underlying gallium nitride layer 104. The dislocation density within these regions is approximately 10 cm" . By contrast, threading dislocations do not appear to readily propagate laterally. Rather, the lateral gallium nitride regions 108a and 308a contain only a few dislocations. These few dislocations may be formed 5 parallel to the (0001) plane via the extension of the vertical threading dislocations after a 90° bend in the regrown region. These dislocations do not appear to propagate to the top surface of the overgrown gallium nitride layer.
As described, the formation mechanism of the selectively grown gallium nitride layers is lateral epitaxy. The two main stages of this mechanism are vertical
10 growth and lateral growth. During vertical growth through a mask, the deposited
gallium nitride grows selectively within the mask openings more rapidly than it grows on the mask, apparently due to the much higher sticking coefficient, s, of the gallium atoms on the gallium nitride surface (s=l) compared to on the mask (s«l). Since the SiC>2 bond strength is 799.6 kJ/mole and much higher than that of Si-N (439 kJ/mole),
15 Ga-N (103 kJ/mole), and Ga-0 (353.6 kJ/mole), Ga or N atoms should not readily
bond to the mask surface in numbers and for a time sufficient to cause gallium nitride nuclei to form. They would either evaporate or diffuse along the mask surface to the opening in the mask or to the vertical gallium nitride surfaces which have emerged. During lateral growth, the gallium nitride grows simultaneously both vertically and
20 laterally.
Surface diffusion of gallium and nitrogen on the gallium nitride may play a role in gallium nitride selective growth. The major source of material appears to be derived from the gas phase. This may be demonstrated by the fact that an increase in the TEG flow rate causes the growth rate of the (0001) top facets to develop faster
25 than the (1 101) side facets and thus controls the lateral growth.
The laterally grown gallium nitride bonds to the underlying mask sufficiently strongly so that it generally does not break away on cooling. However, lateral cracking within the SiO? mask may take place due to thermal stresses generated on cooling. The viscosity (p) of the SiCh at 1050°C is about lO13""1 poise which is one
30 order of magnitude greater than the strain point (about 101 " poise) where stress relief in a bulk amorphous material occurs within approximately six hours. Thus, the SiCb mask may provide limited compliance on cooling. As the atomic arrangement on the amorphous SiO2 surface is quite different from that on the GaN surface, chemical

bonding may occur only when appropriate pairs of atoms are in close proximity. Extremely small relaxations of the silicon and oxygen and gallium and nitrogen atoms on the respective surfaces and/or within the bulk of the SiC2 may accommodate the gallium nitride and cause it to bond to the oxide. Accordingly, the embodiments of 5 Figures 1-5 and 11-15, which need not employ a mask, may be particularly advantageous.
In conclusion, lateral epitaxial overgrowth may be obtained from sidewalls of an underlying gallium nitride layer via MOVPE. The growth may depend strongly on the sidewall orientation, growth temperature and TEG flow rate. Coalescence of
10 overgrown gallium nitride regions to form regions with both extremely low densities of dislocations and smooth and pit-free surfaces may be achieved through 3 urn wide trenches between 7 urn wide posts and extending along the direction, at 1100°C and a TEG flow rate of 26umol/min. The lateral overgrowth of gallium nitride from sidewalls via MOVPE may be used to obtain low defect density regions
15 for microelectronic devices, without the need to use masks.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

WE CLAIM:
1. A method of fabricating a gallium nitride semiconductor layer
comprising the steps of:
laterally growing at least one sidewall of an underlying gallium nitride layer into at least one trench in the underlying gallium nitride layer to thereby form a lateral gallium nitride semiconductor layer.
2. A method as claimed in claim 1, wherein the laterally growing step is followed by the step of forming microelectronic devices in the lateral gallium nitride semiconductor layer.
3. A method as claimed in claim 1, wherein the laterally growing step comprises the step of growing a pair of sidewalls of the underlying gallium nitride layer into a trench in the underlying gallium nitride layer between the pair of sidewalls until the grown pair of sidewalls coalesce in the trench.
4. A method as claimed in claim 1, wherein the laterally growing step comprises the step of laterally growing the sidewall of the underlying gallium nitride layer using metalorganic vapor phase epitaxy.
5. A method as claimed in claim 1, wherein the laterally growing step is preceded by the step of forming the underlying gallium nitride layer including the sidewall on a substrate.
6. A method as claimed in claim 5, wherein the forming step comprises the steps of:
forming a buffer layer on a substrate; and

forming the underlying gallium nitride layer on the buffer layer opposite the substrate.
7. A method as claimed in claim 5, wherein the forming step comprises the step of forming the trench in the underlying gallium nitride layer, the trench including the sidewall.
8. A method as claimed in claim 5, wherein the forming step comprises the step of forming a post on the underlying gallium nitride layer, the post including the sidewall and defining the trench.
9. A method as claimed in claim 1, wherein the underlying gallium nitride layer includes a predetermined defect density and wherein the step of laterally growing a sidewall of an underlying gallium nitride layer into a trench in the underlying gallium nitride layer to thereby form a lateral gallium nitride layer comprises the steps of:
laterally growing the sidewall of the underlying gallium nitride layer to thereby form the lateral gallium nitride layer of lower defect density than the predetermined defect density; and
vertically growing the lateral gallium nitride layer while propagating the lower defect density.
10. A method as claimed in claim 1, wherein the growing step
comprises the step of growing the sidewall of the underlying
gallium nitride layer using metalorganic vapor phase epitaxy of
triethylgallium at 13-39|umol/min and ammonia at 1500 seem at a
temperature of 1000°C-1100°C.

11. A method as claimed in claim 7, wherein the trench forming step comprises the step of selectively etching the underlying gallium nitride layer to form the trench that includes the sidewall.
12. A method as claimed in claim 8, wherein the post forming step comprises the step of selectively growing the underlying gallium nitride layer to form the post including the sidewall.
13. A method as claimed in claim 1, wherein the step of laterally growing comprises:
laterally growing a plurality of sidewalls of an underlying gallium nitride layer into a plurality of trenches in the underlying gallium nitride layer to thereby form a lateral gallium nitride layer.
14. A method as claimed in claim 13, wherein the laterally growing
step is followed by the steps of:
making the lateral gallium nitride layer with a mask that includes an array of openings therein; and
growing the lateral gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer.
15. A method as claimed in claim 13, wherein the growing step is
followed by the steps of:
vertically growing the lateral gallium nitride layer,
forming a plurality of second sidewalls in the vertically grown
lateral gallium nitride layer to define a plurality of second trenches;
and

laterally growing the plurality of second sidewalls of the vertically grown lateral gallium nitride layer into the plurality of second trenches, to thereby form a second lateral gallium nitride semiconductor layer.
16. A method as claimed in claim 14 , wherein the laterally growing step is followed by the step of forming microelectronic devices in the overgrown gallium nitride semiconductor layer.
17. A method as claimed in claim 15, wherein the step of laterally growing the plurality of second sidewalls is followed by the step of forming microelectronic devices in the second lateral gallium nitride semiconductor layer.
18. A method as claimed in claim 13, wherein the laterally growing step comprises the step of growing the plurality of .sidewalls of the underlying gallium nitride layer into the plurality of trenches in the underlying gallium nitride layer until the plurality of grown sidewalls coalesce in the trenches.
19. A method as claimed in claim 14, wherein the growing step comprises the step of growing the lateral gallium nitride layer through the array of openings and onto the mask until the grown lateral gallium nitride layer coalesces on the mask to form a continuous overgrown gallium nitride semiconductor layer.
20. A method as claimed in claim 15, wherein the step of laterally growing the plurality of second sidewalls comprises the step of laterally growing the plurality of second sidewalls of the vertically grown lateral gallium nitride layer into the plurality of second trenches until the plurality of laterally grown second sidewalls coalesce in the plurality of second trenches.

21. A method as claimed in claim 13, wherein the laterally growing step comprises the step of laterally growing the plurality of sidewalls of the underlying gallium nitride layer using metalorganic vapour phase epitaxy.
22. A method as claimed in claim 13, wherein the laterally growing step is preceded by the step of forming the underlying gallium nitride layer including the plurality of sidewalls on a substrate.
23. A method as claimed in claim 22, wherein the forming step comprises the steps of:
forming a buffer layer on a substrate; and
forming the underlying gallium nitride layer on the buffer layer
opposite the substrate.
24. A method as claimed in claim 22, wherein the forming step comprises the step of forming the plurality of trenches in the underlying gallium nitride layer, the plurality of trenches including the plurality of sidewalls.
25. A method as claimed in claim 22, wherein the forming step comprises the step of forming a plurality of posts in the underlying gallium nitride layer, the plurality of posts including the plurality of sidewalls and defining the plurality of trenches.
26. A method as claimed in claim 13, wherein the underlying gallium nitride layer includes a predetermined defect density, and wherein the step of laterally growing a plurality of sidewalls of the underlying gallium nitride layer into the plurality of trenches in the underlying gallium nitride layer to thereby form a lateral gallium nitride layer comprises the steps of:

laterally growing the plurality of sidewalls of the underlying gallium nitride layer into the plurality of trenches to thereby form a lateral gallium nitride semiconductor layer of lower defect density than the predetermined defect density; and
vertically growing the laterally gallium nitride layer while propagating the lower defect density.
A method as claimed in claim 13, wherein the laterally growing step comprises the step of laterally growing the plurality of sidewalls of the underlying gallium nitride layer using metalorganic vapor phase epitaxy of triethylgallium at 13-39umol/min and ammonia at 1500 seem at a temperature of 1000°C -1100°C.
Dated this 31st day of October, 2000.
(SANJAY KUMAR)-Of REMFRY & SAGAR ATTORNEY FOR THE APPLICANTS

Documents:

abstract1.jpg

in-pct-2000-00564-mum-cancelled pages(23-06-2004).pdf

in-pct-2000-00564-mum-claims(granted)-(23-06-2004).doc

in-pct-2000-00564-mum-claims(granted)-(23-06-2004).pdf

in-pct-2000-00564-mum-correspondence(28-06-2004).pdf

in-pct-2000-00564-mum-correspondence(ipo)-(06-10-2004).pdf

in-pct-2000-00564-mum-drawing(23-06-2004).pdf

in-pct-2000-00564-mum-form 1(31-10-2000).pdf

in-pct-2000-00564-mum-form 1a(01-08-2007).pdf

in-pct-2000-00564-mum-form 1a(23-06-2004).pdf

in-pct-2000-00564-mum-form 2(granted)-(23-06-2004).doc

in-pct-2000-00564-mum-form 2(granted)-(23-06-2004).pdf

in-pct-2000-00564-mum-form 3(23-06-2004).pdf

in-pct-2000-00564-mum-form-pct-ipea-409(30-12-2003).pdf

in-pct-2000-00564-mum-form-pct-isa-210(30-12-2003).pdf

in-pct-2000-00564-mum-petition under rule 137(23-06-2004).pdf

in-pct-2000-00564-mum-petition under rule 138(23-06-2004).pdf

in-pct-2000-00564-mum-power of authority(21-11-2000).pdf

in-pct-2000-00564-mum-power of authority(23-01-2004).pdf

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Patent Number

206959

Indian Patent Application Number

IN/PCT/2000/00564/MUM

PG Journal Number

30/2007

Publication Date

27-Jul-2007

Grant Date

16-May-2007

Date of Filing

31-Oct-2000

Name of Patentee

NORTH CAROLINA STATE UNIVERSITY

Applicant Address

1 HOLLADAY HALL, CAMPUS BOX 7003, RALEIGH, NORTH CAROLINA, 27695-7003, UNITED STATE OF AMERICA

Inventors:

#	Inventor's Name	Inventor's Address
1	TSVETANKA ZHELEVA	2109 COPELAND WAY, CHAPEL HILL, NORTH CAROLINA 27514, USA
2	DARREN B. THOMSON	312-D BARGATE DRIVE, CARY, NORTH CAROLINA 27511, USA
3	KEVIN J. LINTHICUM	474 CROSSLINK DRIVE, ANGIER, NORTH CAROLIN 27501, USA
4	ROBERT F. DAVIS	5705 CALTON DRIVE, RALEIGH, NORTH CAROLINA 27612, USA
5	SCOTT A. SMITH	505 CRAWLEY RUN, # 101, CENTERVILLE, OHIO 45458, USA
6	THOMAS GEHRKE,	116B BIM STRET, CARRBORO, NORTH CAROLINA 27510, USA

PCT International Classification Number

C30B 25/04

PCT International Application Number

PCT/US99/12967

PCT International Filing date

1999-06-09

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	60/088/761	1998-06-10	U.S.A.