Title of Invention	A METHOD OF FABRICATING A GALLIUM NITRIDE SEMICONDUCTOR LAYER
Abstract	A method of fabricating a gallium nitride semiconductor layer comprising the steps of: providing a silicon carbide substrate (102), a gallium nitride layer (104) on the silicon carbide substrate and a capping layer (109) on the gallium nitride layer opposite the silicon carbide substrate, the gallium nitride layer comprising a plurality of posts (106) and a plurality of trenches (107) therebetween, the trenches defining a plurality of openings in the capping layer; and laterally growing the sidewalls (105) of the posts into the trenches to thereby form a gallium nitride semiconductor layer (108a); characterized by: the plurality of trenches comprising trench floors in the silicon carbide substrate.

Title of Invention

A METHOD OF FABRICATING A GALLIUM NITRIDE SEMICONDUCTOR LAYER

Abstract

A method of fabricating a gallium nitride semiconductor layer comprising the steps of: providing a silicon carbide substrate (102), a gallium nitride layer (104) on the silicon carbide substrate and a capping layer (109) on the gallium nitride layer opposite the silicon carbide substrate, the gallium nitride layer comprising a plurality of posts (106) and a plurality of trenches (107) therebetween, the trenches defining a plurality of openings in the capping layer; and laterally growing the sidewalls (105) of the posts into the trenches to thereby form a gallium nitride semiconductor layer (108a); characterized by: the plurality of trenches comprising trench floors in the silicon carbide substrate.

Full Text	FORM 2 THE PATENTS ACT 1970 [39 OF 1970] .— COMPLETE SPECIFICATION [See Section 10] "FABRICATION OF GALLIUM NITRIDE LAYERS BY LATERAL GROWTH" NORTH CAROLINA STATE UNIVERSITY, of 1 Holladay Hall, Campus Box 7003, Raleigh, North Carolina-27695-7003, United States of America, The following specification particularly describes the nature of the invention and the manner in which it is to be performed:- FABRICATION OF GALLIUM NITRIDE LAYERS BY LATERAL GROWTH Federally Sponsored Research This invention was made with Government support under Office of Naval Research Contract Nos. N00014-96-1 -0765, N00014-98-1-0384, and N00014-98-1-0654. The Government may have certain rights to this invention. Field of the Invention This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor. 0 Background of the Invention Gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride. A major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium 7 0 nitride layer is grovm. Accordingly, although gallium nitride layers have been grown on sapphjre substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable. It is also known to fabricate gallium nitride structures through openings in a mask. For example, in fabricating field emitter arrays, it is known to selectively grow gallium nitride on stripe or circular patterned substrates. See, for example, the publications by Nam et al. entitled "Selective Growth of GaN andAlo.?GansN on GaN/AlN/6H-SiC(0001) Multilayer Substrates Via Organometallic Vapor Phase Epitaxy", Proceedings of the Materials Research Society, December 1996. and "Growth of GaNandAloiGao8Non Patterened Substrates via Organometallic Vapor lb Phase Epitaxy", Japanese Journal of Applied Physics., Vol. 36, Part 2, No. 5A, May 1997, pp. L532-L535. As disclosed in these publications, undesired ridge growth or lateral overgrowth may occur under certain conditions. Summary of the Invention 1\|5 It is therefore an object of the present invention to provide improved methods of fabricating gallium nitride semiconductor layers, and improved gallium nitride layers so fabricated. It is another object of the invention to provide methods of fabricating gallium nitride semiconductor layers that can have low defect densities, and gallium nitride 2y semiconductor layers so fabricated. These and other objects are provided, according to the present invention, by masking an underlying gallium nitride layer on a silicon carbide substrate with a mask that includes an array of openings therein and etching the underlying gallium nitride layer through the array of openings to define a plurality of posts in the underlying 2$ gallium nitride layer and a plurality of trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended 3d> from the sidewalls of the posts. This form of growth is referred to herein as pendeoepitaxy from the Latin "to hang" or "to be suspended". Microelectronic devices may be formed in the gallium nitride semiconductor layer. ' According to another aspect of the invention, the sidewalls of the posts are laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer. The lateral growth r from the sidewalls of the posts may be continued so that the gallium nitride layer 5 grows vertically through the openings in the mask and laterally overgrows onto the mask on the tops of the posts, to thereby form a gallium nitride semiconductor layer. The lateral overgrowth can be continued until the grown sidewalls coalesce on the mask to thereby form a continuous gallium nitride semiconductor layer. Microelectronic devices may be formed in the continuous gallium nitride 0 semiconductor layer. It has been found, according to the present invention, that dislocation defects do not significantly propagate laterally from the sidewalls of the posts, so that the laterally grown sidewalls of the posts are relatively defect-free. Moreover, during growth, it has been found mat significant vertical growth on the top of the posts is 5 prevented by the mask so that relatively defect-free lateral growth occurs from the sidewalls onto the mask. Significant nucleation on the top of the posts also preferably is prevented. The overgrown gallium nitride semiconductor layer is therefore relatively defect-free. Accordingly, the mask functions as a capping layer on the posts that forces the 10 selective homoepitaxial growth of gallium nitride to occur only on the sidewalls. Defects associated with heteroepitaxial growth of the gallium nitride seed layer are pinned under the mask. By using a combination of growth from sidewalls and lateral overgrowth, a complete coalesced layer of relatively defect-free gallium nitride may be fabricated over the entire surface of a wafer in one regrowth step. grown using metalorganic vapor phase epitaxy (MOVPE). For example, the lateral gallium nitride layer may be laterally grown using tricihylgallium (TEG) and ammonia (NH3) precursors at about 1000-1100°C and about 45 Torr. Preferably, TEG at about 13-39umol/min and NH3 at about 1500 seem are used in combination .0 with about 3000 seem H2 diluent. Most preferably, TEG at about 26μmol/min, NH3 at about 1500 seem and H2 at about 3000 seem at a temperature of about 1100°C and about 45 Torr are used. The underlying gallium nitride layer preferably is formed on a substraie such as 6H-SiC(0001). which itself includes a buffer layer such as aluminum nitride thereon. Other buffer layers such as gallium nitride may be used. Multiple substrate layers and buffer layers also may be used. The underlying gallium nitride layer including the sidewall may be formed by forming trenches in the underlying gallium nitride layer, such that the trenches define the sidewalls. Alternatively, the sidewalls may be formed by forming masked posts on the underlying gallium nitride layer, the masked posts including the sidewalls and defining the trenches. A series of alternating trenches and masked posts is preferably formed to form a plurality of sidewalls. The posts are formed such that the top surface and not the sidewalls are masked. As described above, trenches and/or posts may be formed by masking and selective etching. Alternatively, selective epitaxial growth, combinations of etching and growth, or other techniques may be used. The mask may be formed on the post tops after formation of the posts. The trenches may extend into the buffer layer and/or into the substrate so that the trench floors are in the buffer layer and preferably are in the silicon carbide substrate. The sidewalls of the posts in the underlying gallium nitride layer are laterally grown into the trenches, to thereby form a lateral gallium nitride layer of lower defect density than that of the underlying gallium nitride layer. Some vertical growth may also occur in the trenches, although vertical growth from the post tops is reduced and preferably suppressed by the mask thereon. The laterally grown gallium nitride layer is vertically grown through the openings in the mask while propagating the lower defect density. As the height of the vertical growth extends through the openings in the mask, lateral growth over the mask occurs while propagating the lower defect density to thereby form an overgrown lateral gallium nitride layer on the mask. Gallium nitride semiconductor structures according to the invention comprise a silicon carbide substrate and a plurality of gallium nitride posts on the silicon carbide substrate. The posts each include a sidewall and a top and define a plurality of trenches therebetween. A capping layer is provided on the tops of the posts. A lateral gallium nitride layer extends laterally from the sidewalls of the posts into the trenches. The lateral gallium nitride layer may also be referred to as a pendeoepitaxial gallium nitride layer. The lateral gallium nitride layer may be a continuous lateral gallium nitride layer that extends between adjacent sidewalls across the trenches therebetween. The lateral gallium nitride layer may also extend vertically through the array of openings. An overgrown lateral gallium nitride layer may also be provided that extends laterally onto the capping layer. The overgrown lateral gallium nitride layer may be a continuous overgrown lateral gallium nitride layer that extends between the 5 adjacent sidewalls across the capping layer therebetween. A plurality of microelectronic devices may be provided in the lateral gallium nitride layer and/or in the overgrown lateral gallium nitride layer. A buffer layer may be included between the silicon carbide substrate and the plurality of posts. The trenches may extend into the silicon carbide substrate, into the buffer layer or through '. 0 the buffer layer and into the silicon carbide substrate. The gallium nitride posts may be of a defect density, and the lateral gallium nitride layer and the overgrown lateral gallium nitride layer are of lower defect density than the defect density. Accordingly, low defect density gallium nitride semiconductor layers may be produced, to thereby allow the production of high performance microelectronic devices. 5 Brief Description of the Drawings Figures 1-6 are cross-sectional views of gallium nitride semiconductor structures during intermediate fabrication steps according to the present invention. Figures 7 and 8 are cross-sectional views of other embodiments of gallium Detailed Description of Preferred Embodiments The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the ] 5 invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like .0 numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "onto" another element, it can be directly on the other element or intervening elements may also be present. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well. Referring now to Figures 1-6, methods of fabricating gallium nitride semiconductor structures according to the present invention will now be described, As shown in Figure 1, an underlying gallium nitride layer 104 is grown on a substrate 102. The substrate 102 may include a 6H-SiC(0001) substrate 102a and an aluminum nitride or other buffer layer 102b. The crystallographic designation conventions used herein are well known to those having skill in the art. and need not be described further. The underlying gallium nitride layer 104 may be between 0.5 and 2.0um thick, and may be grown at 1000°C on a high temperature (1100°C) aluminum nitride buffer layer 102b that was deposited on the 6H-SiC substrate 102a in a cold wall vertical and inductively heated metalorganic vapor phase epitaxy system using triethylgallium at 26μmol/min, ammonia at 1500 seem and 3000 seem hydrogen diluent. Additional details of this growth technique may be found in a publication by T.W. Weeks et al. entitled "GaN Thin Films Deposited Via Organometallic Vapor Phase Epitaxy on (6H)-SiC(0001) Using High+Temperature Monocrystalline AIN Buffer Layers", Applied Physics Letters, Vol. 67, No. 3, July 17, 1995, pp. 401-403, the disclosure of which is hereby incorporated herein by reference. Other silicon carbide substrates, with or without buffer layers, may be used. 2b Continuing with the description of Figure 1, a mask such as a silicon nitride (SiN) mask 109 is included on the underlying gallium nitride layer 104. The mask 109 may have a thickness of about 1000A and may be formed on the underlying gallium nitride layer 104 using low pressure chemical vapor deposition (CVD) at 410°C. The mask 109 is patterned to provide an array of openings therein, using 2)5 conventional photolithography techniques. As shown in Figure 1. the underlying gallium nitride layer is etched through the array of openings 10 define a plurality of posts 106 in the underlying gallium nitride layer 104 and a plurality of trenches 107 therebetween. The posts each include a sidewall 105 and a top having the mask 109 thereon. It will also be understood that 3\|0 although the posts 106 and trenches 107 are preferably formed by masking and etching as described above, the posts may also be formed by selectively growing the posts from an underlying gallium nitride layer and then forming a capping layer on -7- ) WO 00/3336: ■PCT/US the tops of the posts. Combinations of selective growth and selective etching mav also be used. Still referring to Figure J, the underlying gallium nitride layer 104 includes a plurality of sidewalls 105 therein. It will be understood by those having skill in the 5 art that the sidewalls 105 may be thought of as being defined by the plurality of spaced apart posts 106, that also may be referred to as "mesas", "pedestals" or "columns". The sidewalls 105 may also be thought of as being defined by the plurality of trenches 107, also referred to as "wells", in the underlying gallium nitride layer 104. The sidewalls 105 may also be thought of as being defined by a series of 10 alternating trenches 107 and posts 106. As described above, the posts 106 and the trenches 107 that define the sidewalls 105 may be fabricated by selective etching and/or selective epitaxial growth and/or other conventional techniques. Moreover, it will also be understood that the sidewalls need not be orthogonal to the substrate 102, but rather may be oblique thereto. ; 5 It will also be understood that although the sidewalls 105 are shown in cross- section in Figure 1. the posts 106 and trenches 107 may define elongated regions that are straight, V-shaped or have other shapes. As shown in Figure 1, the trenches 107 may extend into the buffer layer 102b and into the substrate 102a, so that subsequent gallium nitride growth occurs preferentially on the sidewalls 105 rather than on the 2 0 trench floors. In other embodiments, the trenches may not extend into the substrate 102a, and also may not extend into the buffer layer 102b. depending, for example, on the trench geometry and the lateral versus vertical grouih rates of the gallium nitride. Referring now to Figure 2, the sidewalls 105 of the underlying gallium nitride layer 104 are laterally grown to form a lateral gallium nitride layer 108a in the 25 trenches 107. Laieral growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr. The precursors TEG at 13-39μmo!/min and NH3 at 1500 seem may be used in combination with a 3000 seem H2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used. As used herein, the term "lateral" means a direction that is parallel to the faces 30 of the substrate 102. It will also be understood that some venical growth of the lateral gallium nitride 108a may also take place during the lateral growth from the sidewalls 105. As used herein, the term "venical" denotes a direciional parallel to the sidewalls -8 105. However, it will be understood that growth and/or nucleation on the top of the posts 106 is reduced and is preferably eliminated by the mask 109 Referring now to Figure 3, continued growth of the lateral gallium nitride layer 108a causes vertical growth of the lateral gallium nitride layer 108a through the array of openings. Conditions for vertical growth may be maintained as was described in connection with Figure 2. As also shown in Figure 3, continued vertical growth into trenches 107 may take place at the bottom of the trenches. Referring now to Figure 4, continued growth of the lateral gallium nitride layer 108a causes lateral overgrowth onto the mask 109. to form an overgrown lateral gallium nitride layer 108b. Growth conditions for overgrowth may be maintained as was described in connection with Figure 2. Referring now to Figure 5, growth is allowed to continue until the lateral growth fronts coalesce in the trenches 107 at the interfaces 108c, to form a continuous lateral gallium nitride semiconductor layer 108a in the trenches. Still referring to Figure 5, growth is also allowed to continue until the lateral overgrowih fronts coalesce over the mask 109 at the interfaces 108d, to form a continuous overgrown lateral gallium nitride semiconductor layer 108b. The total growth time may be approximately 60 minutes. A single continuous growth step may be used. As shown in Figure 6, microelectronic devices 110 may then be formed in the lateral gallium nitride semiconductor layer 108a. Microelectronic devices also may be formed in the overgrown lateral gallium nitride layer 108b. Accordingly, in Figure 6, gallium nitride semiconductor structures 100 according to the present invention are illustrated. The gallium nitride structures 100 include the substrate 102. The substrate preferably includes the 6H-SiC(0001) substrate I02a and the aluminum nitride buffer layer 102b on the silicon carbide substrate 102a. The aluminum nitride buffer layer 102b may be 0.1 μrn thick. The fabrication of the substrate 102 is well known to those having skill in the art and need not be described further. Fabrication of silicon carbide substrates are described, for example, in U.S. Patents 4,865,685 to Palmour; Re 34,861 to Davis et al.; 4,912.064 to Kong et al. and 4,946,547 to Palmour et al., the disclosures of which are hereby incorporated herein by reference. The underlying gallium nitride layer 104 is also included on the buffer layer 102b opposite the substrate 102a. The underlying gallium nitride layer 104 may be VVQ-G0713365 PeT/ttS99/2805ti between about 0.5 and 2.0um thick, and may be formed using metalorganic vapor phase epitaxy (MOVPE). The underlying gallium nitride layer generally has an undesired relatively high defect density. For example, dislocation densities of between about 108and 101 cm" may be present in the underlying gallium nitride > layer. These high defect densities may result from mismatches in lattice parameters between the buffer layer 102b and the underlying gallium nitride layer 104, and/or other causes. These high defect densities may impact the performance of microelectronic devices formed in the underlying gallium nitride layer 104. Still continuing with the description of Figure 6. the underlying gallium nitride 1 ) layer 104 includes the plurality of sidewails 105 that may be defined by the plurality of posts 106 and/or the plurality of trenches 107. As was described above, the sidewails may be oblique and of various elongated shapes. Also as was described above, the gallium nitride posts 106 are capped with a capping layer such as a mask 109, preferably comprising silicon nitride. 15 Continuing with the description of Figure 6. the lateral gallium nitride layer 108a extends laterally and vertically from the plurality of sidewails 105 of the underlying gallium nitride layer 104. The overgrown lateral gallium nitride 108b extends from the lateral gallium nitride layer 108a. The lateral gallium nitride layer 108a and the overgrown lateral gallium nitride layer 108b may be formed using 20 metalorganic vapor phase epitaxy at about 1000-1100°C and about 45 Torr. Precursors of triethygallium (TEG) at about 13-39umoI/min and ammonia (NH3) at about 1500 seem may be used in combination with an about 3000 seem H2 diluent, to form the lateral gallium nitride layer 108a and the overgrown lateral gallium nitride layer 108b. \ 5 As shown in Figure 6. the lateral gallium nitride layer 108a coalesces at the interfaces 108c to form a continuous lateral gallium nitride semiconductor layer 108a in the trenches. It has been found that the dislocation densities in the underlying gallium nitride layer 104 generally do not propagate laterally from the sidewails 105 with the same density as vertically from the underlying gallium nitride layer 104. !10 Thus, the lateral gallium nitride layer 108a can have a relatively low dislocation defect density, for example less than about 104 cm-2 . From a practical standpoint, this may be regarded as defect-free. Accordingly, the lateral gallium nitride layer 108a may form device quality gallium nitride semiconductor material. Thus, as shown in - 10' \ Figure 6, microelectronic devices 110 may be formed in ihe lateral gallium nitride semiconductor layer 108a. Still referring to Figure 6, the overgrown lateral gallium nitride layer 108b K coalesces at the interfaces I08d to form a continuous overgrown lateral gallium nitride semiconductor layer 108b over the masks. It has been found that the dislocation densities ;n the underlying gallium nitride layer 104 and of the lateral gallium nitride layer 108a generally do not propagate laterally with the same density as vertically from the underlying gallium nitride layer 104 and the lateral gallium nitride layer 108a. Thus, the overgrown lateral gallium nitride layer 108b also can 0 have a relatively low defect density, for example less than about 10 cm"". Accordingly, the overgrown lateral gallium nitride layer 108b may also form device quality gallium nitride semiconductor material. Thus, as shown in Figure 6, microelectronic devices 110 may also be formed in the overgrown lateral gallium nitride semiconductor layer 108b. Referring now to Figures 7 and 8, other embodiments of gallium nitride semiconductor structures and fabrication methods according to the present invention will now be described. Gallium nitride structures are fabricated as was already described in connection with Figures 1 -6 using different spacings or dimensions for the posts and trenches. In Figure 7, a small post-width / trench-width ratio is used to produce discrete gallium nitride structures. In Figure 8. a large post-width / trench-width ratio is used, to produce other discrete gallium nitride structures. Referring now to Figure 7, using a small post-width / trench-width ratio, gallium nitride semiconductor structures of Figure 7 are fabricated as was already described in connection with Figures 1 -4. Still referring to Figure 7, growth is allowed to continue until the overgrown lateral fronts coalesce over the mask 109 at the interfaces 108d, to form a continuous overgrown lateral gallium nitride semiconductor layer over the mask 109. The total growth time may be approximately 60 minutes. As shown in Figure 7, microelectronic devices 110 may be formed in the overgrown lateral gallium nitride layer 108b. Referring now to Figure 8, using a large post-width / trench-width ratio, gallium nitride semiconductor structures of Figure 8 are fabricated as was already described in connection with Figure 1-4. Still referring to Figure 8, growth is allowed to continue until the overgrown lateral fronts coalesce in the trenches 107 at the interfaces 108c. to form a continuous gallium nitride semiconductor layer 108a in the trenches 107. The total growth time may be approximately 60 minutes. As shown in Figure 8. microelectronic devices 110 may be formed in the pendeoepitaxial gallium nitride layer 108a. ! Additional discussion of methods and structures of the present invention will now be provided. The trenches 107 and are preferably rectangular trenches that preferably extend along the and/or directions on the underlying gallium nitride layer 104. Truncated triangular stripes having (1101) slant facets and a narrow (0001) top facet may be obtained for trenches along the direction. 1 ) Rectangular stripes having a (0001) top facet, (1120) vertical side faces and (1 101) slant facets may be grown along the direction. For growth times up to 3 minutes, similar morphologies may be obtained regardless of orientation. The stripes develop into different shapes if the growth is continued. The amount of lateral growth generally exhibits a strong dependence on trench 15 orientation. The lateral growth rate of the oriented is generally much faster than those along . Accordingly, it is most preferred to orient the trenches so that they extend along the direction of the underlying gallium nitride layer 104. The different morphological development as a function of orientation appears 20 to be related to the stability of the crystallographic planes in the gallium nitride structure. Trenches oriented along may have wide (1100) slant facets and either a very narrow or no (0001) top facet depending on the growth conditions. This may be because (1101) is the most stable plane in the gallium nitride wurtzite crystal structure, and the growth rate of this plane is lower than that of others. The {11 01} Z 5 planes of the oriented trenches may be wavy, which implies the existence of more than one Miller index. It appears that competitive growth of selected {1 101} planes occurs during the deposition which causes these planes to become unstable and which causes their growth rate to increase relative to that of the (1 101) of trenches oriented along . !'0 The morphologies of the gallium nitride layers selectively grown from trenches oriented along are also generally a strong function of the growth temperatures. Layers grown at 1000°C may possess a truncated triangular shape. This morphology may gradually change to a rectangular cross-section as the growth temperature is increased. This shape change may occur as a result of the increase in the diffusion coefficient and therefore the flux of the gallium species along the (0001) top plane onto the {1101} planes with an increase in growth temperature. This may result in a decrease in the growth rate of the (0001) plane and an increase in that of the {1 T01}. This phenomenon has also been observed in the selective growth of gallium arsenate on silicon dioxide. Accordingly, temperatures of 1100°C appear to be most preferred. The morphological development of the gallium nitride regions also appears to depend on the flow rate of the TEG. An increase in the supply of TEG generally increases the growth rate in both the lateral and the vertical directions. However, the lateral/vertical growth rate ratio decrease from about 1.7 at the TEG flow rate of about 13pmol/min to 0.86 at about 39p.mol/min. This increased influence on growth rate along relative to that of with TEG flow rate may be related to the type of reactor employed, wherein the reactant gases flow vertically and perpendicular to the substrate. The considerable increase in the concentration of the gallium species on the surface may sufficiently impede their diffusion to the {110I} planes such that chemisorption and gallium nitride growth occur more readily on the (0001) plane. Continuous 2um thick gallium nitride semiconductor layers may be obtained using 7μrn wide trenches spaced 3 μrn apart and oriented along , at about 1100°C and a TEG flow rate of about 26μmol/min. Continuous 2μm thick gallium nitride semiconductor layers may also be obtained using 3μm wide trenches spaced 2μm apart and oriented along , also at about 1100°C and a TEG flow rate of about 26μmol/min. The continuous gallium nitride semiconductor layers may include subsurface voids that form when two growth fronts coalesce. These voids may occur most often using lateral growth conditions wherein rectangular trenches and/or mask openings having vertical {1120} side facets developed. The continuous gallium nitride semiconductor layers may have a microscopically flat and pit-free surface. The surfaces of the laterally grown gallium nitride layers may include a terrace structure having an average step height of 0.32nm. This terrace structure may be related to the laterally grown gallium nitride, because it is generally not included in much larger area films grown only on aluminum nitride buffer layers. The average RMS roughness values may be similar to the values obtained for the underlying gallium nitride layer 104. Threading dislocations, originating from the interface between the underlying gallium nitride layer 104 and the buffer layer 102b, appear to propagate to the top surface of the underlying gallium nitride layer 104. The dislocation density within these regions is approximately 109 cm'2. By contrast, threading dislocations do not appear to readily propagate laterally. Rather, the lateral gallium nitride layer 108a and the overgrown lateral gallium nitride layer 108b contain only a few dislocations. In the lateral gallium nitride layer 108a, the few dislocations may be formed parallel to the (0001) plane via the extension of the vertical threading dislocations after a 90° bend in the regrown region. These dislocations do not appear to propagate to the top surface of the overgrown gallium nitride layer. As described, the formation mechanism of the selectively grown gallium nitride layers is lateral epitaxy. The two main stages of this mechanism are lateral (or pendeoepitaxial) growth and lateral overgrowth. During pendeoepitaxial growth, the gallium nitride grows simultaneously both vertically and laterally. The deposited gallium nitride grows selectively on the sidewalls more rapidly than it grows on the mask 109, apparently due to the much higher sticking coefficient, s, of the gallium atoms on the gallium nitride sidewall surface (s=l) compared to on the mask (s«l) and substrate (s the TEG flow rate causes the growth rate of the (0001U top facets to develop faster than the (110l) side facets and thus controls the lateral growth. In conclusion, pendeoepitaxial and lateral epitaxial overgrowth may be obtained from sidewalls of an underlying masked gallium nitride layer via MOVPE. The growth may depend strongly on the sidewall orientation, growth temperature and TEG flow rate. Coalescence of pendeoepitaxial grown and lateral overgrown gallium nitride regions to form regions with both extremely low densities of dislocations and smooth and pit-free surfaces may be achieved through 3pm wide trenches between 2μm wide posts and extending along the direction, at about 1100°C and a TEG flow rate of about 26μmol/min. The pendeoepitaxial and lateral overgrowth of gallium nitride from sidewalls via MOVPE may be used to obtain low defect density regions for microelectronic devices over the entire surface of the thin film. In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims. We Claim: 1. A method of fabricating a gallium nitride semiconductor layer comprising the steps of: providing a silicon carbide substrate (102), a gallium nitride layer (104) on the silicon carbide substrate and a capping layer (109) on the gallium nitride layer opposite the silicon carbide substrate, the gallium nitride layer comprising a plurality of posts (106) and a plurality of trenches (107) therebetween, the trenches defining a plurality of openings in the capping layer; and laterally growing the sidewalls (105) of the posts into the trenches to thereby form a gallium nitride semiconductor layer (108a); characterized by: the plurality of trenches comprising trench floors in the silicon carbide substrate. 2. A method as claimed in Claim 1 wherein the step of laterally growing comprises the step of laterally growing the sidewalls of the posts into the trenches until the laterally grown sidewalls coalesce (108c) in the trenches to thereby form a gallium nitride semiconductor layer. -16- 3. A method as claimed in Claim 1 wherein the step of laterally growing comprises the step of laterally overgrowing the laterally grown sidewalls of the posts in the trenches onto the capping layer on the tops of the posts, to thereby form a gallium nitride semiconductor layer. 4. A method as claimed in Claim 3 wherein the step of laterally growing comprises the step of laterally overgrowing (108b) the laterally grown sidewalls of the posts in the trenches onto the capping layer on the tops of the posts until the laterally grown sidewalls coalesce on the capping layer, to thereby form a gallium nitride semiconductor layer. 5. A method as claimed in Claim 1 wherein the laterally growing step is followed by the step of forming microelectronic devices (110) in the gallium nitride semiconductor layer. 6. A method as claimed in Claim 1 wherein the laterally growing step comprises the step of laterally growing the sidewalls of the posts into the trenches using metalorganic vapor phase epitaxy. 7. A method as claimed in Claim 1 wherein the underlying gallium nitride layer includes a defect density, and wherein the laterally growing step comprises the step of laterally growing the sidewalls of the posts into the trenches to thereby form a gallium nitride semiconductor layer of lower defect density than the defect density. -17- 8. A method as claimed in Claim 1 wherein the laterally growing step comprises the steps of: laterally and vertically growing sidewalls of the posts into the trenches and through the openings in the capping layer to thereby form a lateral gallium nitride layer (108a) in the trenches that extends vertically through the openings in the capping layer; and laterally overgrowing the lateral gallium nitride layer that extends through the openings in the capping layer onto the capping layer to thereby form an overgrown lateral gallium nitride layer (108b). 9. A method as claimed in Claim 8 wherein the steps of laterally and vertically growing the sidewalls and laterally overgrowing the lateral gallium nitride layer are performed without vertically growing gallium nitride on the capping layer. 10. A method as claimed in Claim 8 wherein the step of laterally overgrowing the lateral gallium nitride layer comprises the step of laterally overgrowing the lateral gallium nitride layer that extends through the openings in the capping layer onto the capping layer until the overgrown lateral gallium nitride layer coalesces (108d) on the capping layer to thereby form a continuous overgrown lateral gallium nitride layer. -18- 11. A method as claimed in Claim 8 wherein the step of laterally overgrowing the lateral gallium nitride layer is followed by the step of forming microelectronic devices (110) in the overgrown lateral gallium nitride layer. 12. A method as claimed in claim 8 wherein the providing step comprises the steps of: masking an underlying gallium nitride layer on a silicon carbide substrate with a mask that includes an array of openings therein; and etching the underlying gallium nitride layer through the array of openings to define a plurality of posts in the gallium nitride layer and a plurality of trenches therebetween, the posts each comprising a sidewall and a top having the mask thereon to provide the capping layer. 13. A method as claimed in Claim 12 wherein the masking step comprises the step of masking an underlying gallium nitride layer on a buffer layer (102b) on a silicon carbide substrate with a mask that includes an array of openings therein. 14. A method as claimed in Claim 12 wherein the etching step comprises the step of etching the underlying gallium nitride layer and the silicon carbide substrate through the array of openings to define a plurality of posts in the underlying gallium nitride layer and a plurality of trenches therebetween, the posts each comprising a sidewall and a top having the mask thereon, the trenches comprising trench floors in the silicon carbide substrate. -19- 15. A method as claimed in Claim 13 wherein the etching step comprises the step of etching the underlying gallium nitride layer, the buffer layer and the silicon carbide substrate through the array of openings to define a plurality of posts in the underlying gallium nitride layer and a plurality of trenches therebetween, the posts each comprising a sidewall and a top having the mask thereon, the trenches comprising trench floors in the silicon carbide substrate. 16. A method as claimed in Claim 8 wherein the underlying gallium nitride layer includes a defect density, and wherein the laterally and vertically growing step comprises the step of laterally and vertically growing the sidewalls of the posts into the trenches and through the openings in the capping layer to thereby form a lateral gallium nitride semiconductor layer of lower defect density than the defect density. 17. A gallium nitride semiconductor structure (100), comprising: a silicon carbide substrate (102a); a plurality of gallium nitride posts (106) on the silicon carbide substrate, the posts each comprising a sidewall (105) and a top, and defining a plurality of trenches (107) therebetween; a capping layer (109) on the tops of the posts; and a lateral gallium nitride layer (108a) that extends laterally from the sidewalls of the posts into the trenches, characterized by: a plurality of trenches extend into the silicon carbide substrate. -20- 18. A structure as claimed in Claim 17 wherein the lateral gallium nitride layer is a continuous lateral gallium nitride layer (108c) that extends between adjacent sidewalls across the trenches therebetween. 19. A structure as claimed in Claim 17 wherein the lateral gallium nitride layer also extends vertically in the trenches, to beyond the capping layer. 20. A structure as claimed in Claim 19 further comprising: an overgrown lateral gallium nitride layer (108b) that extends laterally from the lateral gallium nitride layer onto the capping layer. 21. A structure as claimed in Claim 20 wherein the overgrown lateral gallium nitride layer is a continuous overgrown lateral gallium nitride layer (108c) that extends between adjacent sidewalls across the capping layer therebetween. 22. A structure as claimed in Claim 17 further comprising a plurality of microelectronic devices (110) in the lateral gallium nitride layer. 23. A structure as claimed in Claim 19 further comprising a plurality of microelectronic devices in the lateral gallium nitride layer that extends vertically in the trenches, beyond the capping layer. -21- 24. A structure as claimed in Claim 20 further comprising a plurality of microelectronic devices in the overgrown lateral gallium nitride layer. 25. A structure as claimed in Claim 17 further comprising a buffer layer (102b) between the silicon carbide substrate and the plurality of posts. 26. A structure as claimed in Claim 25 wherein the trenches extend through the buffer layer and into the silicon carbide substrate. 27. A structure as claimed in Claim 17 wherein the posts are of a defect density and wherein the lateral gallium nitride layer is of lower defect density than the defect density. 28. A structure as claimed in Claim 20 wherein the posts are of a defect density and wherein the overgrown lateral gallium nitride layer is of lower defect density than the defect density. Dated this the 5th day of March, 2001 [JAYANTA PAL] Of Remfry &Sagar ATTORNEY FOR THE APPLICANTfS]

Full Text

FORM 2
THE PATENTS ACT 1970
[39 OF 1970] .—
COMPLETE SPECIFICATION
[See Section 10]

"FABRICATION OF GALLIUM NITRIDE LAYERS BY LATERAL GROWTH"
NORTH CAROLINA STATE UNIVERSITY, of 1 Holladay Hall, Campus Box 7003, Raleigh, North Carolina-27695-7003, United States of America,

The following specification particularly describes the nature of the invention and the manner in which it is to be performed:-

FABRICATION OF GALLIUM NITRIDE LAYERS BY LATERAL GROWTH
Federally Sponsored Research
This invention was made with Government support under Office of Naval Research Contract Nos. N00014-96-1 -0765, N00014-98-1-0384, and N00014-98-1-0654. The Government may have certain rights to this invention.
Field of the Invention
This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor.
0
Background of the Invention
Gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
A major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium 7 0 nitride layer is grovm. Accordingly, although gallium nitride layers have been grown on sapphjre substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon

carbide substrates. Notwithstanding these advances, continued reduction in defect
density is desirable.
It is also known to fabricate gallium nitride structures through openings in a mask. For example, in fabricating field emitter arrays, it is known to selectively grow gallium nitride on stripe or circular patterned substrates. See, for example, the publications by Nam et al. entitled "Selective Growth of GaN andAlo.?GansN on GaN/AlN/6H-SiC(0001) Multilayer Substrates Via Organometallic Vapor Phase Epitaxy", Proceedings of the Materials Research Society, December 1996. and "Growth of GaNandAloiGao8Non Patterened Substrates via Organometallic Vapor lb Phase Epitaxy", Japanese Journal of Applied Physics., Vol. 36, Part 2, No. 5A, May 1997, pp. L532-L535. As disclosed in these publications, undesired ridge growth or lateral overgrowth may occur under certain conditions.
Summary of the Invention
1|5 It is therefore an object of the present invention to provide improved methods
of fabricating gallium nitride semiconductor layers, and improved gallium nitride
layers so fabricated.
It is another object of the invention to provide methods of fabricating gallium nitride semiconductor layers that can have low defect densities, and gallium nitride
2y semiconductor layers so fabricated.
These and other objects are provided, according to the present invention, by masking an underlying gallium nitride layer on a silicon carbide substrate with a mask that includes an array of openings therein and etching the underlying gallium nitride layer through the array of openings to define a plurality of posts in the underlying
2$ gallium nitride layer and a plurality of trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended
3d> from the sidewalls of the posts. This form of growth is referred to herein as
pendeoepitaxy from the Latin "to hang" or "to be suspended". Microelectronic devices may be formed in the gallium nitride semiconductor layer.

'
According to another aspect of the invention, the sidewalls of the posts are laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer. The lateral growth r from the sidewalls of the posts may be continued so that the gallium nitride layer 5 grows vertically through the openings in the mask and laterally overgrows onto the mask on the tops of the posts, to thereby form a gallium nitride semiconductor layer. The lateral overgrowth can be continued until the grown sidewalls coalesce on the mask to thereby form a continuous gallium nitride semiconductor layer. Microelectronic devices may be formed in the continuous gallium nitride 0 semiconductor layer.
It has been found, according to the present invention, that dislocation defects do not significantly propagate laterally from the sidewalls of the posts, so that the laterally grown sidewalls of the posts are relatively defect-free. Moreover, during growth, it has been found mat significant vertical growth on the top of the posts is 5 prevented by the mask so that relatively defect-free lateral growth occurs from the sidewalls onto the mask. Significant nucleation on the top of the posts also preferably is prevented. The overgrown gallium nitride semiconductor layer is therefore relatively defect-free.
Accordingly, the mask functions as a capping layer on the posts that forces the
10 selective homoepitaxial growth of gallium nitride to occur only on the sidewalls.
Defects associated with heteroepitaxial growth of the gallium nitride seed layer are
pinned under the mask. By using a combination of growth from sidewalls and lateral
overgrowth, a complete coalesced layer of relatively defect-free gallium nitride may
be fabricated over the entire surface of a wafer in one regrowth step.
grown using metalorganic vapor phase epitaxy (MOVPE). For example, the lateral gallium nitride layer may be laterally grown using tricihylgallium (TEG) and ammonia (NH3) precursors at about 1000-1100°C and about 45 Torr. Preferably, TEG at about 13-39umol/min and NH3 at about 1500 seem are used in combination .0 with about 3000 seem H2 diluent. Most preferably, TEG at about 26μmol/min, NH3 at about 1500 seem and H2 at about 3000 seem at a temperature of about 1100°C and about 45 Torr are used. The underlying gallium nitride layer preferably is formed on a substraie such as 6H-SiC(0001). which itself includes a buffer layer such as

aluminum nitride thereon. Other buffer layers such as gallium nitride may be used. Multiple substrate layers and buffer layers also may be used.
The underlying gallium nitride layer including the sidewall may be formed by forming trenches in the underlying gallium nitride layer, such that the trenches define the sidewalls. Alternatively, the sidewalls may be formed by forming masked posts on the underlying gallium nitride layer, the masked posts including the sidewalls and defining the trenches. A series of alternating trenches and masked posts is preferably formed to form a plurality of sidewalls. The posts are formed such that the top surface and not the sidewalls are masked. As described above, trenches and/or posts may be formed by masking and selective etching. Alternatively, selective epitaxial growth, combinations of etching and growth, or other techniques may be used. The mask may be formed on the post tops after formation of the posts. The trenches may extend into the buffer layer and/or into the substrate so that the trench floors are in the buffer layer and preferably are in the silicon carbide substrate.
The sidewalls of the posts in the underlying gallium nitride layer are laterally grown into the trenches, to thereby form a lateral gallium nitride layer of lower defect density than that of the underlying gallium nitride layer. Some vertical growth may also occur in the trenches, although vertical growth from the post tops is reduced and preferably suppressed by the mask thereon. The laterally grown gallium nitride layer
is vertically grown through the openings in the mask while propagating the lower defect density. As the height of the vertical growth extends through the openings in the mask, lateral growth over the mask occurs while propagating the lower defect density to thereby form an overgrown lateral gallium nitride layer on the mask.
Gallium nitride semiconductor structures according to the invention comprise
a silicon carbide substrate and a plurality of gallium nitride posts on the silicon

carbide substrate. The posts each include a sidewall and a top and define a plurality of trenches therebetween. A capping layer is provided on the tops of the posts. A lateral gallium nitride layer extends laterally from the sidewalls of the posts into the trenches. The lateral gallium nitride layer may also be referred to as a pendeoepitaxial gallium nitride layer. The lateral gallium nitride layer may be a continuous lateral gallium nitride layer that extends between adjacent sidewalls across the trenches therebetween.

The lateral gallium nitride layer may also extend vertically through the array of openings. An overgrown lateral gallium nitride layer may also be provided that extends laterally onto the capping layer. The overgrown lateral gallium nitride layer may be a continuous overgrown lateral gallium nitride layer that extends between the 5 adjacent sidewalls across the capping layer therebetween.
A plurality of microelectronic devices may be provided in the lateral gallium nitride layer and/or in the overgrown lateral gallium nitride layer. A buffer layer may be included between the silicon carbide substrate and the plurality of posts. The trenches may extend into the silicon carbide substrate, into the buffer layer or through '. 0 the buffer layer and into the silicon carbide substrate. The gallium nitride posts may be of a defect density, and the lateral gallium nitride layer and the overgrown lateral gallium nitride layer are of lower defect density than the defect density. Accordingly, low defect density gallium nitride semiconductor layers may be produced, to thereby allow the production of high performance microelectronic devices. 5
Brief Description of the Drawings Figures 1-6 are cross-sectional views of gallium nitride semiconductor structures during intermediate fabrication steps according to the present invention. Figures 7 and 8 are cross-sectional views of other embodiments of gallium Detailed Description of Preferred Embodiments
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the
] 5 invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like
.0 numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "onto" another element, it can be directly on the other element or intervening elements may

also be present. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well.
Referring now to Figures 1-6, methods of fabricating gallium nitride
semiconductor structures according to the present invention will now be described,
As shown in Figure 1, an underlying gallium nitride layer 104 is grown on a substrate
102. The substrate 102 may include a 6H-SiC(0001) substrate 102a and an aluminum
nitride or other buffer layer 102b. The crystallographic designation conventions used
herein are well known to those having skill in the art. and need not be described
further. The underlying gallium nitride layer 104 may be between 0.5 and 2.0um
thick, and may be grown at 1000°C on a high temperature (1100°C) aluminum nitride
buffer layer 102b that was deposited on the 6H-SiC substrate 102a in a cold wall
vertical and inductively heated metalorganic vapor phase epitaxy system using
triethylgallium at 26μmol/min, ammonia at 1500 seem and 3000 seem hydrogen
diluent. Additional details of this growth technique may be found in a publication by
T.W. Weeks et al. entitled "GaN Thin Films Deposited Via Organometallic Vapor
Phase Epitaxy on (6H)-SiC(0001) Using High+Temperature Monocrystalline AIN
Buffer Layers", Applied Physics Letters, Vol. 67, No. 3, July 17, 1995, pp. 401-403,
the disclosure of which is hereby incorporated herein by reference. Other silicon
carbide substrates, with or without buffer layers, may be used.
2b Continuing with the description of Figure 1, a mask such as a silicon nitride
(SiN) mask 109 is included on the underlying gallium nitride layer 104. The mask 109 may have a thickness of about 1000A and may be formed on the underlying gallium nitride layer 104 using low pressure chemical vapor deposition (CVD) at 410°C. The mask 109 is patterned to provide an array of openings therein, using
2)5 conventional photolithography techniques.
As shown in Figure 1. the underlying gallium nitride layer is etched through the array of openings 10 define a plurality of posts 106 in the underlying gallium nitride layer 104 and a plurality of trenches 107 therebetween. The posts each include a sidewall 105 and a top having the mask 109 thereon. It will also be understood that
3|0 although the posts 106 and trenches 107 are preferably formed by masking and
etching as described above, the posts may also be formed by selectively growing the posts from an underlying gallium nitride layer and then forming a capping layer on

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)

WO 00/3336:

■PCT/US

the tops of the posts. Combinations of selective growth and selective etching mav also be used.
Still referring to Figure J, the underlying gallium nitride layer 104 includes a plurality of sidewalls 105 therein. It will be understood by those having skill in the 5 art that the sidewalls 105 may be thought of as being defined by the plurality of spaced apart posts 106, that also may be referred to as "mesas", "pedestals" or "columns". The sidewalls 105 may also be thought of as being defined by the plurality of trenches 107, also referred to as "wells", in the underlying gallium nitride layer 104. The sidewalls 105 may also be thought of as being defined by a series of 10 alternating trenches 107 and posts 106. As described above, the posts 106 and the trenches 107 that define the sidewalls 105 may be fabricated by selective etching and/or selective epitaxial growth and/or other conventional techniques. Moreover, it will also be understood that the sidewalls need not be orthogonal to the substrate 102, but rather may be oblique thereto.
; 5 It will also be understood that although the sidewalls 105 are shown in cross-
section in Figure 1. the posts 106 and trenches 107 may define elongated regions that are straight, V-shaped or have other shapes. As shown in Figure 1, the trenches 107 may extend into the buffer layer 102b and into the substrate 102a, so that subsequent gallium nitride growth occurs preferentially on the sidewalls 105 rather than on the
2 0 trench floors. In other embodiments, the trenches may not extend into the substrate 102a, and also may not extend into the buffer layer 102b. depending, for example, on the trench geometry and the lateral versus vertical grouih rates of the gallium nitride. Referring now to Figure 2, the sidewalls 105 of the underlying gallium nitride layer 104 are laterally grown to form a lateral gallium nitride layer 108a in the
25 trenches 107. Laieral growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr. The precursors TEG at 13-39μmo!/min and NH3 at 1500 seem may be used in combination with a 3000 seem H2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used. As used herein, the term "lateral" means a direction that is parallel to the faces
30 of the substrate 102. It will also be understood that some venical growth of the lateral gallium nitride 108a may also take place during the lateral growth from the sidewalls 105. As used herein, the term "venical" denotes a direciional parallel to the sidewalls
-8

105. However, it will be understood that growth and/or nucleation on the top of the posts 106 is reduced and is preferably eliminated by the mask 109
Referring now to Figure 3, continued growth of the lateral gallium nitride layer 108a causes vertical growth of the lateral gallium nitride layer 108a through the array of openings. Conditions for vertical growth may be maintained as was described in connection with Figure 2. As also shown in Figure 3, continued vertical growth into trenches 107 may take place at the bottom of the trenches.
Referring now to Figure 4, continued growth of the lateral gallium nitride layer 108a causes lateral overgrowth onto the mask 109. to form an overgrown lateral gallium nitride layer 108b. Growth conditions for overgrowth may be maintained as was described in connection with Figure 2.
Referring now to Figure 5, growth is allowed to continue until the lateral growth fronts coalesce in the trenches 107 at the interfaces 108c, to form a continuous lateral gallium nitride semiconductor layer 108a in the trenches.
Still referring to Figure 5, growth is also allowed to continue until the lateral overgrowih fronts coalesce over the mask 109 at the interfaces 108d, to form a continuous overgrown lateral gallium nitride semiconductor layer 108b. The total growth time may be approximately 60 minutes. A single continuous growth step may be used. As shown in Figure 6, microelectronic devices 110 may then be formed in the lateral gallium nitride semiconductor layer 108a. Microelectronic devices also may be formed in the overgrown lateral gallium nitride layer 108b.
Accordingly, in Figure 6, gallium nitride semiconductor structures 100 according to the present invention are illustrated. The gallium nitride structures 100 include the substrate 102. The substrate preferably includes the 6H-SiC(0001) substrate I02a and the aluminum nitride buffer layer 102b on the silicon carbide substrate 102a. The aluminum nitride buffer layer 102b may be 0.1 μrn thick.
The fabrication of the substrate 102 is well known to those having skill in the art and need not be described further. Fabrication of silicon carbide substrates are described, for example, in U.S. Patents 4,865,685 to Palmour; Re 34,861 to Davis et al.; 4,912.064 to Kong et al. and 4,946,547 to Palmour et al., the disclosures of which are hereby incorporated herein by reference.
The underlying gallium nitride layer 104 is also included on the buffer layer 102b opposite the substrate 102a. The underlying gallium nitride layer 104 may be

VVQ-G0713365 PeT/ttS99/2805ti
between about 0.5 and 2.0um thick, and may be formed using metalorganic vapor phase epitaxy (MOVPE). The underlying gallium nitride layer generally has an undesired relatively high defect density. For example, dislocation densities of between about 108and 101 cm" may be present in the underlying gallium nitride > layer. These high defect densities may result from mismatches in lattice parameters between the buffer layer 102b and the underlying gallium nitride layer 104, and/or other causes. These high defect densities may impact the performance of microelectronic devices formed in the underlying gallium nitride layer 104.
Still continuing with the description of Figure 6. the underlying gallium nitride
1 ) layer 104 includes the plurality of sidewails 105 that may be defined by the plurality
of posts 106 and/or the plurality of trenches 107. As was described above, the
sidewails may be oblique and of various elongated shapes. Also as was described
above, the gallium nitride posts 106 are capped with a capping layer such as a mask
109, preferably comprising silicon nitride.
15 Continuing with the description of Figure 6. the lateral gallium nitride layer
108a extends laterally and vertically from the plurality of sidewails 105 of the underlying gallium nitride layer 104. The overgrown lateral gallium nitride 108b extends from the lateral gallium nitride layer 108a. The lateral gallium nitride layer 108a and the overgrown lateral gallium nitride layer 108b may be formed using 20 metalorganic vapor phase epitaxy at about 1000-1100°C and about 45 Torr.
Precursors of triethygallium (TEG) at about 13-39umoI/min and ammonia (NH3) at
about 1500 seem may be used in combination with an about 3000 seem H2 diluent, to
form the lateral gallium nitride layer 108a and the overgrown lateral gallium nitride
layer 108b.
\ 5 As shown in Figure 6. the lateral gallium nitride layer 108a coalesces at the
interfaces 108c to form a continuous lateral gallium nitride semiconductor layer 108a in the trenches. It has been found that the dislocation densities in the underlying gallium nitride layer 104 generally do not propagate laterally from the sidewails 105 with the same density as vertically from the underlying gallium nitride layer 104. !10 Thus, the lateral gallium nitride layer 108a can have a relatively low dislocation
defect density, for example less than about 104 cm-2 . From a practical standpoint, this may be regarded as defect-free. Accordingly, the lateral gallium nitride layer 108a may form device quality gallium nitride semiconductor material. Thus, as shown in
- 10'

\ Figure 6, microelectronic devices 110 may be formed in ihe lateral gallium nitride
semiconductor layer 108a.
Still referring to Figure 6, the overgrown lateral gallium nitride layer 108b K coalesces at the interfaces I08d to form a continuous overgrown lateral gallium nitride semiconductor layer 108b over the masks. It has been found that the dislocation densities ;n the underlying gallium nitride layer 104 and of the lateral gallium nitride layer 108a generally do not propagate laterally with the same density as vertically from the underlying gallium nitride layer 104 and the lateral gallium nitride layer 108a. Thus, the overgrown lateral gallium nitride layer 108b also can 0 have a relatively low defect density, for example less than about 10 cm"".
Accordingly, the overgrown lateral gallium nitride layer 108b may also form device quality gallium nitride semiconductor material. Thus, as shown in Figure 6, microelectronic devices 110 may also be formed in the overgrown lateral gallium
nitride semiconductor layer 108b.
Referring now to Figures 7 and 8, other embodiments of gallium nitride semiconductor structures and fabrication methods according to the present invention will now be described. Gallium nitride structures are fabricated as was already described in connection with Figures 1 -6 using different spacings or dimensions for the posts and trenches. In Figure 7, a small post-width / trench-width ratio is used to produce discrete gallium nitride structures. In Figure 8. a large post-width / trench-width ratio is used, to produce other discrete gallium nitride structures.
Referring now to Figure 7, using a small post-width / trench-width ratio, gallium nitride semiconductor structures of Figure 7 are fabricated as was already described in connection with Figures 1 -4. Still referring to Figure 7, growth is allowed to continue until the overgrown lateral fronts coalesce over the mask 109 at the interfaces 108d, to form a continuous overgrown lateral gallium nitride semiconductor layer over the mask 109. The total growth time may be approximately 60 minutes. As shown in Figure 7, microelectronic devices 110 may be formed in the overgrown lateral gallium nitride layer 108b.

Referring now to Figure 8, using a large post-width / trench-width ratio, gallium nitride semiconductor structures of Figure 8 are fabricated as was already described in connection with Figure 1-4. Still referring to Figure 8, growth is allowed to continue until the overgrown lateral fronts coalesce in the trenches 107 at the

interfaces 108c. to form a continuous gallium nitride semiconductor layer 108a in the
trenches 107. The total growth time may be approximately 60 minutes. As shown in
Figure 8. microelectronic devices 110 may be formed in the pendeoepitaxial gallium
nitride layer 108a.
! Additional discussion of methods and structures of the present invention will
now be provided. The trenches 107 and are preferably rectangular trenches that preferably extend along the and/or directions on the underlying gallium nitride layer 104. Truncated triangular stripes having (1101) slant facets and a narrow (0001) top facet may be obtained for trenches along the direction. 1 ) Rectangular stripes having a (0001) top facet, (1120) vertical side faces and (1 101)
slant facets may be grown along the direction. For growth times up to 3 minutes, similar morphologies may be obtained regardless of orientation. The stripes develop into different shapes if the growth is continued.
The amount of lateral growth generally exhibits a strong dependence on trench
15 orientation. The lateral growth rate of the oriented is generally much faster than those along . Accordingly, it is most preferred to orient the trenches so that they extend along the direction of the underlying gallium nitride layer 104.
The different morphological development as a function of orientation appears
20 to be related to the stability of the crystallographic planes in the gallium nitride
structure. Trenches oriented along may have wide (1100) slant facets and either a very narrow or no (0001) top facet depending on the growth conditions. This may be because (1101) is the most stable plane in the gallium nitride wurtzite crystal structure, and the growth rate of this plane is lower than that of others. The {11 01}
Z 5 planes of the oriented trenches may be wavy, which implies the existence of more than one Miller index. It appears that competitive growth of selected {1 101} planes occurs during the deposition which causes these planes to become unstable and which causes their growth rate to increase relative to that of the (1 101) of trenches
oriented along .
!'0 The morphologies of the gallium nitride layers selectively grown from
trenches oriented along are also generally a strong function of the growth

temperatures. Layers grown at 1000°C may possess a truncated triangular shape. This morphology may gradually change to a rectangular cross-section as the growth temperature is increased. This shape change may occur as a result of the increase in the diffusion coefficient and therefore the flux of the gallium species along the (0001) top plane onto the {1101} planes with an increase in growth temperature. This may result in a decrease in the growth rate of the (0001) plane and an increase in that of the {1 T01}. This phenomenon has also been observed in the selective growth of gallium arsenate on silicon dioxide. Accordingly, temperatures of 1100°C appear to be most preferred.
The morphological development of the gallium nitride regions also appears to depend on the flow rate of the TEG. An increase in the supply of TEG generally increases the growth rate in both the lateral and the vertical directions. However, the lateral/vertical growth rate ratio decrease from about 1.7 at the TEG flow rate of about 13pmol/min to 0.86 at about 39p.mol/min. This increased influence on growth rate along relative to that of with TEG flow rate may be related to the type of reactor employed, wherein the reactant gases flow vertically and perpendicular to the substrate. The considerable increase in the concentration of the gallium species on the surface may sufficiently impede their diffusion to the {110I} planes such that chemisorption and gallium nitride growth occur more readily on the (0001) plane.
Continuous 2um thick gallium nitride semiconductor layers may be obtained using 7μrn wide trenches spaced 3 μrn apart and oriented along , at about 1100°C and a TEG flow rate of about 26μmol/min. Continuous 2μm thick gallium nitride semiconductor layers may also be obtained using 3μm wide trenches spaced 2μm apart and oriented along , also at about 1100°C and a TEG flow rate of about 26μmol/min. The continuous gallium nitride semiconductor layers may include subsurface voids that form when two growth fronts coalesce. These voids may occur most often using lateral growth conditions wherein rectangular trenches and/or mask openings having vertical {1120} side facets developed.
The continuous gallium nitride semiconductor layers may have a microscopically flat and pit-free surface. The surfaces of the laterally grown gallium nitride layers may include a terrace structure having an average step height of 0.32nm. This terrace structure may be related to the laterally grown gallium nitride, because it

is generally not included in much larger area films grown only on aluminum nitride buffer layers. The average RMS roughness values may be similar to the values obtained for the underlying gallium nitride layer 104.
Threading dislocations, originating from the interface between the underlying gallium nitride layer 104 and the buffer layer 102b, appear to propagate to the top surface of the underlying gallium nitride layer 104. The dislocation density within these regions is approximately 109 cm'2. By contrast, threading dislocations do not appear to readily propagate laterally. Rather, the lateral gallium nitride layer 108a and the overgrown lateral gallium nitride layer 108b contain only a few dislocations. In the lateral gallium nitride layer 108a, the few dislocations may be formed parallel to the (0001) plane via the extension of the vertical threading dislocations after a 90° bend in the regrown region. These dislocations do not appear to propagate to the top surface of the overgrown gallium nitride layer.
As described, the formation mechanism of the selectively grown gallium nitride layers is lateral epitaxy. The two main stages of this mechanism are lateral (or pendeoepitaxial) growth and lateral overgrowth. During pendeoepitaxial growth, the gallium nitride grows simultaneously both vertically and laterally. The deposited gallium nitride grows selectively on the sidewalls more rapidly than it grows on the mask 109, apparently due to the much higher sticking coefficient, s, of the gallium atoms on the gallium nitride sidewall surface (s=l) compared to on the mask (s«l) and substrate (s

the TEG flow rate causes the growth rate of the (0001U top facets to develop faster than the (110l) side facets and thus controls the lateral growth.
In conclusion, pendeoepitaxial and lateral epitaxial overgrowth may be obtained from sidewalls of an underlying masked gallium nitride layer via MOVPE. The growth may depend strongly on the sidewall orientation, growth temperature and TEG flow rate. Coalescence of pendeoepitaxial grown and lateral overgrown gallium nitride regions to form regions with both extremely low densities of dislocations and smooth and pit-free surfaces may be achieved through 3pm wide trenches between 2μm wide posts and extending along the direction, at about 1100°C and a TEG flow rate of about 26μmol/min. The pendeoepitaxial and lateral overgrowth of gallium nitride from sidewalls via MOVPE may be used to obtain low defect density regions for microelectronic devices over the entire surface of the thin film.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

We Claim:
1. A method of fabricating a gallium nitride semiconductor layer
comprising the steps of:
providing a silicon carbide substrate (102), a gallium nitride layer
(104) on the silicon carbide substrate and a capping layer (109) on the
gallium nitride layer opposite the silicon carbide substrate, the
gallium nitride layer comprising a plurality of posts (106) and a
plurality of trenches (107) therebetween, the trenches defining a
plurality of openings in the capping layer; and
laterally growing the sidewalls (105) of the posts into the trenches to
thereby form a gallium nitride semiconductor layer (108a);
characterized by:
the plurality of trenches comprising trench floors in the silicon carbide
substrate.
2. A method as claimed in Claim 1 wherein the step of laterally
growing comprises the step of laterally growing the sidewalls of the
posts into the trenches until the laterally grown sidewalls coalesce
(108c) in the trenches to thereby form a gallium nitride semiconductor
layer.
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3. A method as claimed in Claim 1 wherein the step of laterally growing comprises the step of laterally overgrowing the laterally grown sidewalls of the posts in the trenches onto the capping layer on the tops of the posts, to thereby form a gallium nitride semiconductor layer.
4. A method as claimed in Claim 3 wherein the step of laterally growing comprises the step of laterally overgrowing (108b) the laterally grown sidewalls of the posts in the trenches onto the capping layer on the tops of the posts until the laterally grown sidewalls coalesce on the capping layer, to thereby form a gallium nitride semiconductor layer.

5. A method as claimed in Claim 1 wherein the laterally growing step is followed by the step of forming microelectronic devices (110) in the gallium nitride semiconductor layer.
6. A method as claimed in Claim 1 wherein the laterally growing step comprises the step of laterally growing the sidewalls of the posts into the trenches using metalorganic vapor phase epitaxy.
7. A method as claimed in Claim 1 wherein the underlying gallium nitride layer includes a defect density, and wherein the laterally growing step comprises the step of laterally growing the sidewalls of the posts into the trenches to thereby form a gallium nitride semiconductor layer of lower defect density than the defect density.
-17-

8. A method as claimed in Claim 1 wherein the laterally growing step
comprises the steps of:
laterally and vertically growing sidewalls of the posts into the trenches and through the openings in the capping layer to thereby form a lateral gallium nitride layer (108a) in the trenches that extends vertically through the openings in the capping layer; and laterally overgrowing the lateral gallium nitride layer that extends through the openings in the capping layer onto the capping layer to thereby form an overgrown lateral gallium nitride layer (108b).
9. A method as claimed in Claim 8 wherein the steps of laterally and
vertically growing the sidewalls and laterally overgrowing the lateral
gallium nitride layer are performed without vertically growing gallium
nitride on the capping layer.
10. A method as claimed in Claim 8 wherein the step of laterally
overgrowing the lateral gallium nitride layer comprises the step of
laterally overgrowing the lateral gallium nitride layer that extends
through the openings in the capping layer onto the capping layer until
the overgrown lateral gallium nitride layer coalesces (108d) on the
capping layer to thereby form a continuous overgrown lateral gallium
nitride layer.
-18-

11. A method as claimed in Claim 8 wherein the step of laterally overgrowing the lateral gallium nitride layer is followed by the step of forming microelectronic devices (110) in the overgrown lateral gallium nitride layer.
12. A method as claimed in claim 8 wherein the providing step
comprises the steps of:
masking an underlying gallium nitride layer on a silicon carbide substrate with a mask that includes an array of openings therein; and etching the underlying gallium nitride layer through the array of openings to define a plurality of posts in the gallium nitride layer and a plurality of trenches therebetween, the posts each comprising a sidewall and a top having the mask thereon to provide the capping layer.
13. A method as claimed in Claim 12 wherein the masking step comprises the step of masking an underlying gallium nitride layer on a buffer layer (102b) on a silicon carbide substrate with a mask that includes an array of openings therein.
14. A method as claimed in Claim 12 wherein the etching step comprises the step of etching the underlying gallium nitride layer and the silicon carbide substrate through the array of openings to define a plurality of posts in the underlying gallium nitride layer and a plurality of trenches therebetween, the posts each comprising a sidewall and a top having the mask thereon, the trenches comprising trench floors in the silicon carbide substrate.
-19-

15. A method as claimed in Claim 13 wherein the etching step comprises the step of etching the underlying gallium nitride layer, the buffer layer and the silicon carbide substrate through the array of openings to define a plurality of posts in the underlying gallium nitride layer and a plurality of trenches therebetween, the posts each comprising a sidewall and a top having the mask thereon, the trenches comprising trench floors in the silicon carbide substrate.
16. A method as claimed in Claim 8 wherein the underlying gallium nitride layer includes a defect density, and wherein the laterally and vertically growing step comprises the step of laterally and vertically growing the sidewalls of the posts into the trenches and through the openings in the capping layer to thereby form a lateral gallium nitride semiconductor layer of lower defect density than the defect density.
17. A gallium nitride semiconductor structure (100), comprising: a silicon carbide substrate (102a);
a plurality of gallium nitride posts (106) on the silicon carbide substrate, the posts each comprising a sidewall (105) and a top, and defining a plurality of trenches (107) therebetween; a capping layer (109) on the tops of the posts; and a lateral gallium nitride layer (108a) that extends laterally from the sidewalls of the posts into the trenches, characterized by: a plurality of trenches extend into the silicon carbide substrate.
-20-

18. A structure as claimed in Claim 17 wherein the lateral gallium nitride layer is a continuous lateral gallium nitride layer (108c) that extends between adjacent sidewalls across the trenches therebetween.
19. A structure as claimed in Claim 17 wherein the lateral gallium nitride layer also extends vertically in the trenches, to beyond the capping layer.
20. A structure as claimed in Claim 19 further comprising:
an overgrown lateral gallium nitride layer (108b) that extends laterally from the lateral gallium nitride layer onto the capping layer.
21. A structure as claimed in Claim 20 wherein the overgrown lateral gallium nitride layer is a continuous overgrown lateral gallium nitride layer (108c) that extends between adjacent sidewalls across the capping layer therebetween.
22. A structure as claimed in Claim 17 further comprising a plurality of microelectronic devices (110) in the lateral gallium nitride layer.
23. A structure as claimed in Claim 19 further comprising a plurality of microelectronic devices in the lateral gallium nitride layer that extends vertically in the trenches, beyond the capping layer.
-21-

24. A structure as claimed in Claim 20 further comprising a plurality of microelectronic devices in the overgrown lateral gallium nitride layer.
25. A structure as claimed in Claim 17 further comprising a buffer layer (102b) between the silicon carbide substrate and the plurality of posts.
26. A structure as claimed in Claim 25 wherein the trenches extend through the buffer layer and into the silicon carbide substrate.
27. A structure as claimed in Claim 17 wherein the posts are of a defect density and wherein the lateral gallium nitride layer is of lower defect density than the defect density.
28. A structure as claimed in Claim 20 wherein the posts are of a defect density and wherein the overgrown lateral gallium nitride layer is of lower defect density than the defect density.
Dated this the 5th day of March, 2001
[JAYANTA PAL]
Of Remfry &Sagar
ATTORNEY FOR THE APPLICANTfS]

Documents:

in-pct-2001-00247-mum-cancelled pages(29-12-2005).pdf

in-pct-2001-00247-mum-claims(granted)-(29-12-2005).doc

in-pct-2001-00247-mum-claims(granted)-(29-12-2005).pdf

in-pct-2001-00247-mum-correspondence(30-05-2006).pdf

in-pct-2001-00247-mum-correspondence(ipo)-(17-01-2006).pdf

in-pct-2001-00247-mum-form 1(05-03-2001).pdf

in-pct-2001-00247-mum-form 1(29-12-2005).pdf

in-pct-2001-00247-mum-form 19(05-05-2004).pdf

in-pct-2001-00247-mum-form 2(granted)-(29-12-2005).doc

in-pct-2001-00247-mum-form 2(granted)-(29-12-2005).pdf

in-pct-2001-00247-mum-form 3(05-03-2001).pdf

in-pct-2001-00247-mum-form 3(20-10-2003).pdf

in-pct-2001-00247-mum-form 3(29-12-2005).pdf

in-pct-2001-00247-mum-form 5(05-03-2001).pdf

in-pct-2001-00247-mum-form-pct-ipea-409(05-03-2001).pdf

in-pct-2001-00247-mum-form-pct-isa-210(05-03-2001).pdf

in-pct-2001-00247-mum-petiton under rule 137(29-12-2005).pdf

in-pct-2001-00247-mum-power of authority(03-04-2001).pdf

in-pct-2001-00247-mum-power of authority(19-01-2006).pdf

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Patent Number

204666

Indian Patent Application Number

IN/PCT/2001/00247/MUM

PG Journal Number

24/2007

Publication Date

15-Jun-2007

Grant Date

01-Mar-2007

Date of Filing

05-Mar-2001

Name of Patentee

NORTH CAROLINA STATE UNIVERSITY

Applicant Address

1 HOLLADAY HALL, CAMPUS BOX 7003, UNITED STATES OF AMERICA.

Inventors:

#	Inventor's Name	Inventor's Address
1	KEVIN J. LINTHICUM	474 CROSSKLINK DRIVE, ANGIER, NORTH CAROLINA 27501, U.S.A
2	THOMAS GEHRKE	116B BIM STREET, CARRBORO, NORTH CAROLINA 27510, USA
3	DARREN B. THOMSON	425 W. CORNWALL ROAD, NORTH CAROLINA 27511, USA.
4	ERIC P. CARLSON	1208 SOUTHERN OAKS DRIVE, RALEIGH, NORTH CAROLINA 27603, USA.
5	PRADEEP RAJAGOPAL	2502 AVENT FERRY ROAD, APARTMENT 102, RALEIGH, NORTH CAROLINA 27606, USA.
6	ROBERT F. DAVIS	5705 CALTON, RALEIGH, NORTH CAROLINA 27612, USA

PCT International Classification Number

h 01 l 29/267

PCT International Application Number

PCT/US99/28056

PCT International Filing date

1999-11-23

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	09 / 198,784	1998-11-24	U.S.A.