Title of Invention	METHOD AND SYSTEM FOR OPERATING A MULTI-STAGE COUNTER IN ONE COUNTING DIRECTION
Abstract	Method of operating a multistage counter (11) in only one counting direction, comprising the following steps: changing the counter reading of a single - stage counter (1) that can be changed in only one direction at predetermined counter readings of the multistage counter, registering the respective counter readings of the multistage counter (11) and of the single - stage auxiliary counter (1), comparing the values of the registered counter readings of the single -stage (1) and of the multistage counters (11), and generating an indicator signal on the basis of the result of the comparison, in which case, when there is agreement between the counter readings, a change in the multistage counter (11) is permitted.

Title of Invention

METHOD AND SYSTEM FOR OPERATING A MULTI-STAGE COUNTER IN ONE COUNTING DIRECTION

Abstract

Method of operating a multistage counter (11) in only one counting direction, comprising the following steps: changing the counter reading of a single - stage counter (1) that can be changed in only one direction at predetermined counter readings of the multistage counter, registering the respective counter readings of the multistage counter (11) and of the single - stage auxiliary counter (1), comparing the values of the registered counter readings of the single -stage (1) and of the multistage counters (11), and generating an indicator signal on the basis of the result of the comparison, in which case, when there is agreement between the counter readings, a change in the multistage counter (11) is permitted.

Full Text	1 DESCRIPTION The invention relates to a method and an arrangement for operating a multistage counter in one counting direction. Nowadays there are very many fields of application in which the counting of events is to take place. These events can be the frequency of use of an appliance, the passing of persons or vehicles or objects, the registration of a telephone counting cycle, but also the registration of a driving performance, be it an odometer in an automobile or an operating hours counter in any desired appliance and, not least, the registered working time or attendance time of an employee at his workplace. All these cases are characterized by the fact that they are registered with the highest possible accuracy, that is to say as a rule a high value range of counter readings is covered. In addition, in the aforementioned cases, there is generally the desire for the counter result not to be open to manipulation, that is to say it cannot be reset. A requirement of this case may be met reliably by a single - stage counter which can count only upward or downward from its previous counter reading. This may be implemented simply, for example by means of an EEPROM, it then being necessary for there to be one EEPROM cell for each counter reading, and for the EEPROM to be capable of being only written or erased, depending on whether upward or downward counting is provided. For the first requirement, namely that the greatest possible value range is to be registered by the counter, then leads to the result that, in the case of such an implementation , an EEPROM memory with appropriately many storage cells has 2 to be provided. Expressed in numerical terms, this means that, for example in order to achieve a maximum counter reading of 255, exactly 255 counter cells are needed. However, it is nowadays usual to construct arrangements of this type to be as small as possible. The use of a multistage counter with 8 bits, that is to say 8 counter cells, likewise leads to a maximum counter reading of 255. A multistage counter of this type (8 - bit binary counter) has the drawback, however, that when there is a change in the next counter digit, the preceding counter digit is reset. This leads to the situation where the implementation of a multistage counter which counts only in one direction and at the same time is not open to manipulation can be realized only with great difficulty. EP 0 321 727 describes a circuit arrangement in which a number of EEPROM cells are arranged in a row. In this case, a number or rows are in turn connected together. The storage cells of one row in each case constitute a uniform value level, it being possible for the stored contents of one row to be erased by a logical monitoring means only when an overflow into the next higher row has taken place. The arrangement disclosed in this printed specification exhibits precisely the drawbacks previously explained of being open to manipulation, in that unidirectional counting is not insured with certainty by exerting an influence on the logic circuit. A similar but somewhat more complicated arrangement is explained in EP 0 618 591, an auxiliary storage cell being provided for rewriting each next higher row, being capable of being programmed and also erased again, but this arrangement can also be manipulated easily, since the auxiliary storage cells can be both written and erased. 3 JP 02 090726A describes an arrangement for measuring a signal A, using two counters 4 and 6. The periodic signal A is fed to both of the counters, in each case via a gate 1 and 2. It is possible to assume that the counters are not those which count in only one direction, but can atleast be reset. Since this is a measuring arrangement, in this case the respective opening time of the two is different by 1/N. The counter result of the counter 4 is indicated by flashing until the ratio between the two counter results is likewise 1/N. The result of the counter 4 is then indicated continuously. As a result, the counter results from the two counters do not depend on each other but on the frequency of the signal A and the ratio of the opening times of the two gates 1 and 2. The invention is therefore based on the object of providing a method and a circuit arrangement for operating a multistage counter in which security against manipulation is increased. According to the invention, this object is achieved by the features specified in patent claims 1 and 4, respectively. By means of the simultaneous operation of a single - stage counter which counts only either upward or downward, in addition to the multistage counter, which counts the actual event, a comparison is used to insure that the counter reading of the multistage counter agrees with the counter reading of the single - stage counter, atleast in terms of order of magnitude. The possibility of manipulation is therefore eliminated with simple means. If agreement, with a predefined ratio between the two counters, is not provided, then the indicator signal according to claim 2 indicates the lack of reliability, a check being made to see whether the 4 counter reading of the single - stage counter is in a predetermined relationship with the counter reading of the multistage counter. According to patent claim 3, reliability is provided when the counter readings agree. In the following text, the invention will be described with reference to the figure, an exemplary embodiment being illustrated in the form of a block diagram. The exemplary embodiment illustrated in the figure has an m - stage counter with m = 8. In the illustration, this is to be understood as an 8 - bit binary counter. The counter 11 is therefore able to count from 0 to 255, that is to say 256 counting digits. The counter 11 is connected to a control unit 3, which feeds the counter 11 with a counting signal Sll. Each time the counting signal S11 is fed, the counter 11 is changed by 1, the change taking place in the same direction as a preceding change. This means that the counter illustrated symbolically in the figure is configured in such a way that it counts either upward or only downward. The respective counter reading of the multistage counter 11 is fed as a counter - reading signal 211 to test logic 4. Also provided is a single -stage counter 1 which, in this exemplary embodiment, has n cells with n = 16. This counter, illustrated symbolically in the figure, is intended to be constructed in such a way that it also counts only in one counting direction, namely from 0 to 15, that is to say 16 counting digits. The single - stage counter 1 receives a counting signal S1 from the control unit 3, on receipt of which it is incremented by one counting value. The counter reading of the single - stage counter 1 is fed to the control unit 3 as a monitoring counter - reading signal Zl, and therefore 5 to the test logic 4. The test logic 4 compares the counter - reading signal Z11 with the monitoring counter - reading signal Z1 and outputs a signal determined on the basis of the comparison to a counter controller 5. The counter controller 5 in turn outputs an error signal F on the basis of the test signal P received from the test logic 4. The two counters 11 and 1 can be constructed, for example, as EEPROM cells. In this case, provision is made for the individual storage cell to be written or erased in accordance with the rules of upward or downward counting, corresponding to the known operation of a binary counter. In the same way, the single - stage monitoring counter 1 is also composed of EEPROM cells, it being possible for the individual cells 1 to n only to be written or erased one after another. The typical operation of the arrangement illustrated in the figure will now be described. In principle, provision is made for a counting signal S11 to be output by the control unit 3 in response to each input signal E. In this case, the test logic 4 has previously checked the counter readings of the two counters 1 and 11 by means of the counter - reading signal Z11 and the monitoring counter -reading signal Zl. If both are 0, for example, the test logic 4 determines that there is agreement and, by means of the test signal P, permits the counter controller 5 to output the counting signal SF. Provision is now made for both counters to count from 0 to 255. This means that at each sixteenth counting signal Sll which goes to the multistage counter 11, the single - stage monitoring counter 1 likewise receives a monitoring counting signal SI from the counter controller 5 in the control unit 3. For non -manipulated operation, the test logic is then designed in such a way that it 6 monitors the fact that the counter reading of the counter 11 matches the counter reading just reached by the monitoring counter 1. This means that, in the case of the exemplary embodiment illustrated, the counter reading of the counter 1 i must not be less than (i x 16) - 1. This is correspondingly true for an arrangement which counts downwards; here, too, the counter 11 must be located in a range which matches the counter reading of the monitoring counter 1, in accordance with the counting logic. As soon as the test logic 4 determines that there is no agreement, an error signal F is output. However, the invention is not restricted to the exemplary embodiment illustrated in the figure. Instead, it is also possible to imagine that, in particular in the case of a very large counter - reading range of the counter 11 which is to be exceeded, in order to save counter cells in the single - stage counter, the latter is not operated linearly but, for example, in decades. This means that the single - stage counter would receive a monitoring counting signal S1 from the counter controller 5, for example, at each 10th, 100th, 1000th counting signal S11, and so on. In order to monitor the non - manipulated operation, the test logic 4 must be constructed accordingly, that is to say in such a case the counter reading of the counter 11 must correspond to the order of magnitude associated with the respective counter reading of the monitoring counter 1. It is equally well possible to imagine that the relationship between the counter reading of the counter 11 and the counter reading of the monitoring counter 1 corresponds to a logarithmic, exponential or any other suitable and desired function. This can then be applied both to counter arrangements which count upward and to those which count downward. 7 In conclusion, it should be pointed out that the counter 11 and the monitoring counter 1 do not necessarily have to count in the same direction. Instead, provision can also be made for the one counter to count upward and for the respective other counter to count downward. The sole precondition for non -manipulated operation is that the monitoring counter counts in only one direction and the test logic 4 is constructed in such a way that the counter reading of the counter 11 has a logical relationship with the counter reading of the monitoring counter 1. 8 We Claim 1. Method of operating a multistage counter (11) in only one counting direction, comprising the following steps: - changing the counter reading of a single - stage counter (1) that can be changed in only one direction at predetermined counter readings of the multistage counter, - registering the respective counter readings of the multistage counter (11) and of the single - stage auxiliary counter (1), - comparing the values of the registered counter readings of the single - stage (1) and of the multistage counters (11), and - generating an indicator signal on the basis of the result of the comparison, in which case, when there is agreement between the counter readings, a change in the multistage counter (11) is permitted. 2. Method as claimed in claim 1, wherein the indicator signal indicates the reliability of the counter reading of the multistage counter if said reading is in a predetermined relationship with the counter reading of the single -stage counter. 9 3. Method as claimed in claim 2, wherein the indicator signal indicates the reliability of the counter reading of the multistage counter that the counter reading of the multistage counter agrees with the counter reading of the single - stage counter. 4. Circuit device for implementing the method as claimed in one of claims 1 to 3, comprising: a multistage counter (11) which counts only upwards or downwards and in which the counter reading of one stage is reset to an initial value when a counter reading of the following stage is changed, a single - stage auxiliary counter (1), which is operated such that it counts only upwards or only downwards and which is changed at predetermined counter readings of the multistage counter (11), and a comparison means (4), which is connected to the counter (11) and the auxiliary counter (1) in such a way that it compares the counter readings (Z1 and Z11) of the two counters in each case and outputs a signal corresponding to the comparison which permits the change in the multistage counter (11). Method of operating a multistage counter (11) in only one counting direction, comprising the following steps: changing the counter reading of a single - stage counter (1) that can be changed in only one direction at predetermined counter readings of the multistage counter, registering the respective counter readings of the multistage counter (11) and of the single - stage auxiliary counter (1), comparing the values of the registered counter readings of the single -stage (1) and of the multistage counters (11), and generating an indicator signal on the basis of the result of the comparison, in which case, when there is agreement between the counter readings, a change in the multistage counter (11) is permitted.

Full Text

1
DESCRIPTION
The invention relates to a method and an arrangement for operating a multistage counter in one counting direction.
Nowadays there are very many fields of application in which the counting of events is to take place. These events can be the frequency of use of an appliance, the passing of persons or vehicles or objects, the registration of a telephone counting cycle, but also the registration of a driving performance, be it an odometer in an automobile or an operating hours counter in any desired appliance and, not least, the registered working time or attendance time of an employee at his workplace. All these cases are characterized by the fact that they are registered with the highest possible accuracy, that is to say as a rule a high value range of counter readings is covered. In addition, in the aforementioned cases, there is generally the desire for the counter result not to be open to manipulation, that is to say it cannot be reset. A requirement of this case may be met reliably by a single - stage counter which can count only upward or downward from its previous counter reading. This may be implemented simply, for example by means of an EEPROM, it then being necessary for there to be one EEPROM cell for each counter reading, and for the EEPROM to be capable of being only written or erased, depending on whether upward or downward counting is provided.
For the first requirement, namely that the greatest possible value range is to be registered by the counter, then leads to the result that, in the case of such an implementation , an EEPROM memory with appropriately many storage cells has

2
to be provided. Expressed in numerical terms, this means that, for example in order to achieve a maximum counter reading of 255, exactly 255 counter cells are needed. However, it is nowadays usual to construct arrangements of this type to be as small as possible. The use of a multistage counter with 8 bits, that is to say 8 counter cells, likewise leads to a maximum counter reading of 255. A multistage counter of this type (8 - bit binary counter) has the drawback, however, that when there is a change in the next counter digit, the preceding counter digit is reset. This leads to the situation where the implementation of a multistage counter which counts only in one direction and at the same time is not open to manipulation can be realized only with great difficulty.
EP 0 321 727 describes a circuit arrangement in which a number of EEPROM cells are arranged in a row. In this case, a number or rows are in turn connected together. The storage cells of one row in each case constitute a uniform value level, it being possible for the stored contents of one row to be erased by a logical monitoring means only when an overflow into the next higher row has taken place. The arrangement disclosed in this printed specification exhibits precisely the drawbacks previously explained of being open to manipulation, in that unidirectional counting is not insured with certainty by exerting an influence on the logic circuit. A similar but somewhat more complicated arrangement is explained in EP 0 618 591, an auxiliary storage cell being provided for rewriting each next higher row, being capable of being programmed and also erased again, but this arrangement can also be manipulated easily, since the auxiliary storage cells can be both written and erased.

3
JP 02 090726A describes an arrangement for measuring a signal A, using two counters 4 and 6. The periodic signal A is fed to both of the counters, in each case via a gate 1 and 2. It is possible to assume that the counters are not those which count in only one direction, but can atleast be reset. Since this is a measuring arrangement, in this case the respective opening time of the two is different by 1/N. The counter result of the counter 4 is indicated by flashing until the ratio between the two counter results is likewise 1/N. The result of the counter 4 is then indicated continuously. As a result, the counter results from the two counters do not depend on each other but on the frequency of the signal A and the ratio of the opening times of the two gates 1 and 2.
The invention is therefore based on the object of providing a method and a circuit arrangement for operating a multistage counter in which security against manipulation is increased.
According to the invention, this object is achieved by the features specified in patent claims 1 and 4, respectively.
By means of the simultaneous operation of a single - stage counter which counts only either upward or downward, in addition to the multistage counter, which counts the actual event, a comparison is used to insure that the counter reading of the multistage counter agrees with the counter reading of the single - stage counter, atleast in terms of order of magnitude. The possibility of manipulation is therefore eliminated with simple means. If agreement, with a predefined ratio between the two counters, is not provided, then the indicator signal according to claim 2 indicates the lack of reliability, a check being made to see whether the

4
counter reading of the single - stage counter is in a predetermined relationship with the counter reading of the multistage counter. According to patent claim 3, reliability is provided when the counter readings agree.
In the following text, the invention will be described with reference to the figure, an exemplary embodiment being illustrated in the form of a block diagram.
The exemplary embodiment illustrated in the figure has an m - stage counter with m = 8. In the illustration, this is to be understood as an 8 - bit binary counter. The counter 11 is therefore able to count from 0 to 255, that is to say 256 counting digits. The counter 11 is connected to a control unit 3, which feeds the counter 11 with a counting signal Sll. Each time the counting signal S11 is fed, the counter 11 is changed by 1, the change taking place in the same direction as a preceding change. This means that the counter illustrated symbolically in the figure is configured in such a way that it counts either upward or only downward. The respective counter reading of the multistage counter 11 is fed as a counter - reading signal 211 to test logic 4. Also provided is a single -stage counter 1 which, in this exemplary embodiment, has n cells with n = 16. This counter, illustrated symbolically in the figure, is intended to be constructed in such a way that it also counts only in one counting direction, namely from 0 to 15, that is to say 16 counting digits. The single - stage counter 1 receives a counting signal S1 from the control unit 3, on receipt of which it is incremented by one counting value. The counter reading of the single - stage counter 1 is fed to the control unit 3 as a monitoring counter - reading signal Zl, and therefore

5
to the test logic 4. The test logic 4 compares the counter - reading signal Z11 with the monitoring counter - reading signal Z1 and outputs a signal determined on the basis of the comparison to a counter controller 5. The counter controller 5 in turn outputs an error signal F on the basis of the test signal P received from the test logic 4.
The two counters 11 and 1 can be constructed, for example, as EEPROM cells. In this case, provision is made for the individual storage cell to be written or erased in accordance with the rules of upward or downward counting, corresponding to the known operation of a binary counter. In the same way, the single - stage monitoring counter 1 is also composed of EEPROM cells, it being possible for the individual cells 1 to n only to be written or erased one after another.
The typical operation of the arrangement illustrated in the figure will now be described. In principle, provision is made for a counting signal S11 to be output by the control unit 3 in response to each input signal E. In this case, the test logic 4 has previously checked the counter readings of the two counters 1 and 11 by means of the counter - reading signal Z11 and the monitoring counter -reading signal Zl. If both are 0, for example, the test logic 4 determines that there is agreement and, by means of the test signal P, permits the counter controller 5 to output the counting signal SF.
Provision is now made for both counters to count from 0 to 255. This means that at each sixteenth counting signal Sll which goes to the multistage counter 11, the single - stage monitoring counter 1 likewise receives a monitoring counting signal SI from the counter controller 5 in the control unit 3. For non -manipulated operation, the test logic is then designed in such a way that it

6
monitors the fact that the counter reading of the counter 11 matches the counter reading just reached by the monitoring counter 1. This means that, in the case of the exemplary embodiment illustrated, the counter reading of the counter 1 i must not be less than (i x 16) - 1. This is correspondingly true for an arrangement which counts downwards; here, too, the counter 11 must be located in a range which matches the counter reading of the monitoring counter 1, in accordance with the counting logic.
As soon as the test logic 4 determines that there is no agreement, an error signal F is output.
However, the invention is not restricted to the exemplary embodiment illustrated in the figure. Instead, it is also possible to imagine that, in particular in the case of a very large counter - reading range of the counter 11 which is to be exceeded, in order to save counter cells in the single - stage counter, the latter is not operated linearly but, for example, in decades. This means that the single - stage counter would receive a monitoring counting signal S1 from the counter controller 5, for example, at each 10th, 100th, 1000th counting signal S11, and so on. In order to monitor the non - manipulated operation, the test logic 4 must be constructed accordingly, that is to say in such a case the counter reading of the counter 11 must correspond to the order of magnitude associated with the respective counter reading of the monitoring counter 1. It is equally well possible to imagine that the relationship between the counter reading of the counter 11 and the counter reading of the monitoring counter 1 corresponds to a logarithmic, exponential or any other suitable and desired function. This can then be applied both to counter arrangements which count upward and to those which count downward.

7
In conclusion, it should be pointed out that the counter 11 and the monitoring counter 1 do not necessarily have to count in the same direction. Instead, provision can also be made for the one counter to count upward and for the respective other counter to count downward. The sole precondition for non -manipulated operation is that the monitoring counter counts in only one direction and the test logic 4 is constructed in such a way that the counter reading of the counter 11 has a logical relationship with the counter reading of the monitoring counter 1.

8 We Claim
1. Method of operating a multistage counter (11) in only one counting direction, comprising the following steps:
- changing the counter reading of a single - stage counter (1) that
can be changed in only one direction at predetermined counter
readings of the multistage counter,
- registering the respective counter readings of the multistage
counter (11) and of the single - stage auxiliary counter (1),

- comparing the values of the registered counter readings of the
single - stage (1) and of the multistage counters (11), and
- generating an indicator signal on the basis of the result of the
comparison, in which case, when there is agreement between the
counter readings, a change in the multistage counter (11) is
permitted.
2. Method as claimed in claim 1, wherein the indicator signal indicates the reliability of the counter reading of the multistage counter if said reading is in a predetermined relationship with the counter reading of the single -stage counter.

9
3. Method as claimed in claim 2, wherein the indicator signal indicates the
reliability of the counter reading of the multistage counter that the
counter reading of the multistage counter agrees with the counter reading
of the single - stage counter.
4. Circuit device for implementing the method as claimed in one of claims 1
to 3, comprising:
a multistage counter (11) which counts only upwards or downwards and in which the counter reading of one stage is reset to an initial value when a counter reading of the following stage is changed,
a single - stage auxiliary counter (1), which is operated such that it counts only upwards or only downwards and which is changed at predetermined counter readings of the multistage counter (11), and
a comparison means (4), which is connected to the counter (11) and the auxiliary counter (1) in such a way that it compares the counter readings (Z1 and Z11) of the two counters in each case and outputs a signal corresponding to the comparison which permits the change in the multistage counter (11).
Method of operating a multistage counter (11) in only one counting direction, comprising the following steps: changing the counter reading of a single - stage counter (1) that can be changed in only one direction at predetermined counter readings of the multistage counter, registering the respective counter readings of the multistage counter (11) and of the single - stage auxiliary counter (1), comparing the values of the registered counter readings of the single -stage (1) and of the multistage counters (11), and generating an indicator signal on the basis of the result of the comparison, in which case, when there is agreement between the counter readings, a change in the multistage counter (11) is permitted.

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Patent Number

203261

Indian Patent Application Number

IN/PCT/2000/0613/KOL

PG Journal Number

10/2007

Publication Date

09-Mar-2007

Grant Date

09-Mar-2007

Date of Filing

08-Dec-2000

Name of Patentee

INFINEON TECHNOLOGIES AG

Applicant Address

ST.-MARTIN -STRASSE 53, D-81541 MUNCHEN,

Inventors:

#	Inventor's Name	Inventor's Address
1	ALLINGER ROBERT	TURNERSTRASSE 39, D-81827 MUNCHEN
2	HOLLFELDER ,ROBERT	TURNERSTRASSE 39, D-81827 MUNCHEN
3	POCKRANDT ,WOLFGANG	ILMSTRASSE 1, D-85293 REICHERTSHAUSEN
4	WEDEL ,ARMIN	BOGENFELDSTRASSE 1, D-86415 MERING

PCT International Classification Number

H 03 K 21/40

PCT International Application Number

PCT/DE99/01570

PCT International Filing date

1999-05-28

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	198 23 955.6	1998-05-28	Germany