Title of Invention

A METHOD AND A TRANSCODING DEVICE FOR MODIFYING DATA IN AN ENCODED SIGNAL

Abstract

The invention relates to a method of modifying data in an encoded data signal (128) corresponding to successive pictures divided into sub-pictures, for providing an output modified data signal (129). In particular, this invention can be used for the insertion of an additional data signal (130) into a compressed video data signal (128). The proposed arrangements/diagrams according to the invention are based on a transcoder arrangement including at least partial decoding means and partial re-encoding means. This method leads to a cost-effective solution compared with the prior art comprising a minimum number of functional DCT/IDCT sub-steps, taking advantage of simplifications and combinations between different sub-steps. Use Data insertion into an encoded video signal.

Full Text

FIELD OF THE INVENTION The present invention relates to a method of modifying data in an encoded data signal, comprising at least: a decoding step for decoding said encoded data signal and providing a decoded data signal, a re-encoding step performed on a modified data signal. The invention also relates to video processing devices for carrying out said method. This invention may be used, for instance, when a broadcaster wants to introduce additional data into a sequence of coded pictures. This invention finds applications not just in the field of MPEG-2 compression, but more generally in any digital video data compression system. BACKGROUND OF THE INVENTION Modifying data in an encoded data signal has become a vital function in studio editing environments. A possible solution has been proposed in the international patent application WO 99/51033 (PHF98546). This patent application describes a method and its corresponding device for modifying data in an mcoded data signal. This method allows an additional data signal insertion, e.g. a logo insertion, in an MPEG-2 bitstream by means of bit rate transcoding. Logo insertion comes as an extension of the bit rate transcoder. The corresponding diagram, depicted in Fig.l, comprises a transcoding module 101 and a logo addition branch 102. The gena:al outline of the transcoding module 101, well known to a person skilled in the art, comprises: a partial decoding branch 119 for receiving the input signal 128 and providing a decoded data signal £iTor_r(n), also called error residue. This branch comprises in series a variable length decoding 107, an inverse quantization 108 providing a decoded data signal Eiror_I(n) in the frequential domain, and an inverse discrete cosine transform (IDCT) 109 for providing a decoded data signal Error_r(n) in the pixel domain. a re-encoding branch 121 for providing an output signal 129 and generating a coding error. Said re-encoding branch, acting on the modified data signal A"(n) for providing said output signal 129, comprises in series a discrete cosine transform (DCT) 110, a quantization 111, a variable length coding 112 followed by a buffer 113, and regulation means 114 ensuring a constant picture quality of the output signal 129. A local decoding is also performed mside said re-encoding branch. It comprises in series an inverse quantization 115 followed by an inverse discrete cosine transform 116. A subtracting sub-step is performed for providing said coding error resulting fi-om the difTorence between the output signal of said sub-stq) 116 and said signal A"(n). an intermediate branch 120 comprising a motion conq>ensation 105 using motion vectors V(n) of the input signal, its associated memory 106 storing a previous signal, and a second subtracter 124. This branch, also called prediction loop, avoids the quality drift in the ou^ut signal 129 by subtracting the motion-compensated coding error firom said decoded data signal, by means of subtracting sub-step 124. The logo addition branch 102 is impl«nented through to the addition of a pixel-based residual signal to the decoded signal Error_r(n) by means of the adding sub-step 122. This branch provides a pixel-based residual signal resulting from the subtraction between an additional data signal Logo(n) referenced 130 and a motion-compensated logo predicted signal PR£D(Logo(n-l), V(n)) referenced 127, obtained by means of the motion compensation sub-step 103 and based on reference pictures containing logo previously stored in memory 104 with the use of the same vectors V(n) as the main input signal. In the prior art diagram depicted in Fig. 1, two inverse discrete cosine transforms designated as 109 and 116 are performed, as well as one discrete cosine transform designated as 110. The first inverse discrete cosine transform 109 is £q>phed to dequantized fi-equential coefBcients obtained after the inverse quantization 108. Said sub-step 109 allows to access in the pixel domain to access a pixel-based error residue relative to the input signal 128 and thus to perform the data addition in the pixel domain by means of the adding sub-step 122. The pixel-based signal resulting from this addition, after subtraction of the drift correction signal generated by 105, is then re-encoded by processing means. To this end, the discrete cosine transform 110 is dedicated to convert pixel-based data into frequential data, said fi-equential data being afterwards quantized and entropy-coded in order to generate the output signal 129. A second inverse discrete cosine transform 116 is also done in the re-encoding branch so that the motion compensation 105 is performed on pixel-based data. Such DCT/IDCT are block-based processes performed on 8*8 pixel blocks defining the respective data content of each picture in the pixel/frequential domain. Dealing with the so-called widespread 4:2:0-625 or 4:2:2-625 video formats, each picture is defined by a large number of 8*8 blocks whose DCT/IDCT processes lead to a dramatically high CPU load, hideed, such processes necessitating a huge quantity of addition-multiplication steps of high resolution, they can only be done with powCTfiil digital signal processors, thus excluding the definition of relatively low-cost devices or products. This prior art solution then remains expensive in terms of the CPU load, which also results in a lack of flexibiUty in its hardware implementation. SUMMARY OF THE INVENTION It is an object of the invention to provide a method of modifying data in an encoded data signal, derived fi-om the prior art, which imposes a lesser burden on central processing units (CPU). In a first application, the method of modifying data according to the invention is characterized in that it comprises: a conversion step for providing a frequential residual signal resulting from the &equential conversion of said pixel-based residual signal, said frequential residual signal being added to said decoded data signal, a sub-step for adding said fi"equential residual signal to said decoded data signal so as to provide said modified data signal. In a second £q>phcation, the method of modifying data according to the invention, comprising an intennediate step providing a motion-compensated signal fix)m said coding error, is characterized in that said motion-compensated signal is subtracted fix>m said modified data signal before said re-encoding step. In a third application, the method of modifying data according to the invention, comprising a residual signal resulting fix)m the difference between an additional data signal and its predicted version, is characterized in that it comprises sub-steps for inserting said additional data signal into said intennediate step. In a fourth application, the method of modifying data according to the invention is characterized in that it comprises a sub-step for adding said additional data signal to said modified data signal before said re-encoding step. The corresponding diagrams, depicted in Fig.2 to Fig.7, respectively, are based on data addition of the additional data signal 130 to the decoded data signal relative to the input data signal or to a signal situated in the transcoder drift correction loop by means of said adding or subtracting sub-steps. According to the invention, compared with the prior art solution, C3*U-consuming DCT/IDCT sub-steps are replaced with DCT/IDCT sub-steps involving a limited load on the CPU, in return for which the structure of the data insertion is modified, such simplifications being possible in that advantage is taking of combinations between different sub-steps and in using their own properties, such as the linearity of the motion compensation or the distributivity of DCT as compared with addition. The invention thus comprises a Tninimuin number of fimctional sub-stq)s, which results in a cost-efTective solution. Anotho* object of the invention is to propose devices for implementing the above-mentioned methods. To this end, in a first implementation, the invention relates to a transcoding device for adding data to an encoded data signal, characterized in that it comprises : conversion means for providing a fi^uential residual signal resulting fiiom the frequoitial conversion of said pixel-based residual signal, said firequential residual signal being added to said decoded data signal, means for adding said fi^uential residual signal to said decoded data signal so as to provide said modified data signal. In a second inmlementation, the invention relates to a transcoding device for adding data to an encoded data signal characterized in that it comprises data insertion means for inserting a modifying data signal into said intennediary branch. In a third implementation, the invention relates to a transcoding device for adding data to an encoded data signal, characterized in that it comprises means for adding an additional data signal to said modified data signal before said re-encoding. Detailed explanations and other aspects of the invention will be given below. BRIEF DESCRIPTION OF THE DRAWINGS The particular aspects of the invention will now be explained with reference to the embodimoits described hereinafter and considered in connection with the accompanying drawings, in which identical parts or sub-steps are designated in the same manner: Fig. 1 illustrates the outline, as blown in the prior art, of a transcoder with its logo addition branch, Fig.2 illustrates a first embodimoit of the technical solution according to the present invention. Fig.3 illustrates a second embodiment of the technical solution according to the present invention. Fig.4 illustrates a third embodiment of the technical solution according to the present invention. Fig.5 illustrates a fourth embodiment of the technical solution according to the present invention. Fig.6 illustrates a fifth embodiment of the technical solution according to the present invention. Fig.7 illustrates a sixth embodiment of the technical solution according to the present invention. DETAILED DESCRIPTION OF THE INVENTION As was stated above, the present invention aims at reducing the cost of the prior art method for modifying data in an oicoded data signal. Such an invention is well adapted to the case of MPEG-2 coded video signals as input signal, but it will be apparent to a person skilled in the art that such a method is applicable to any coded signal that has been encoded with a block-based conq}ression method such as, for example, the one described in MPEG-4, H.261 or H.263 standards. In the following, the invention will be detailed assmning that encoded video signals comply with the MPEG-2 intemational video standard (Moving Pictures Experts Group, ISO/IEC 13818-2). Fig J is a diagram of the first data insertion of an additional data signal Logo(n) referenced 130 into an encoded data signal 128. It is derived from the prior art diagram depicted in Fig.l, using the properties of DCT and IDCT operations. Indeed, data insertion in the pixel domain as depicted in Fig.l can be transformed so as to insert data in the frequential domain while reducing the cost of the algoiidim in view of a hardware implementation. The following notations will be adopted for the demonstration: V(n): vectors of picture number n, £rror_I(n) : error residue of input picture number n in the frequential domain, Error_r(n): error residue of input picture number n in the pixel domain, MEMl (n) : picture number n stored in the frame memory 106, PREDCX:(n), V(n+1)): motion compensation of signal X(n) using vectors V(n+1). It corresponds to a predicted version of signal X(n+1), DCT( X(n)) : discrete cosine transform of signal X(n), n)CT( X(n)): inverse discrete cosine transform of signal X(n). Starting fipom the prior art, it can be written: 1) A(n) = DCT(A*(n)) 2) A(n) = DCT(Error_r(n) + Logo(n)-PRED(Logo(n-l), V(n))-PRED( MEMl(n-l), V(n))) Using the property of distributivity of DCT as compared with addition : 3) A(n) = DCT( ErrorJ"Cn) ) + DCT( Logo(n) - PRED( Logo(n-1), V(n))) - DCT( PRED( MEMl(n-l), V(n))) Considering the linearity of DCT and IDCT operations, and the fact that appl3ing a DCT to a signal which has passed through an IDCT equals the unity transfer: 4) DCT( IDCT( X(n) ) ) = X(n) with X(n) defining a digital video signal and 5) ErTor_r(n) = IDCT(Error_I(n)) Using relations 0 and 0, A(n) becomes: 6) A(n) = EirorJ(n) + DCT( Logo(n) - PRED( Logo(n-l), V(n)) ) - DCT( PRED( MEMl(n-l), V(n))) This relation 6) can thus be implemented according to the arrangement of Fig.2. Such an arrangement has the same structure as the one of the prior art in the sense that it also comprises a partial decoding branch 219, a re-encoding branch 221, an intermediate branch 220, a data addition branch 202, all linked in the same manna- but coiiq)osed of different sub-steps so that new data insertion is performed in the frequential domain. The partial decoding branch 219, providing a decoded data signal, comprises a variable length decoding sub-step 107 followed by fhe inverse quantization sub-stq) 108. The re-encoding branch 221, acting on a modified data signal, comprises in series a quantization sub-step 211, a variable length coding sub-step 212, and buffer regulation means 213-214. It also comprises an inverse quantization sub-step 215 receiving the output signal ofsah-step 211, a subtracting sub-step 123 delivering the difference between two signals in die frequeatial domain, the first one corresponding to the output of sub-step 215 and the second one corresponding to the output of sub-stq) 124, and an inverse discrete cosine transform 216 receiving the output signal of said sub-step 123 and delivering a coding error. The intennediate branch 220 comprises in series a memory defined by sub-step 206 and storing a previous picture number MEM2(n-l), a motion compensation sub-step 205 performed on the contents of 206 and delivering a pixel-based motion-compensated signal PRED(MEM2(n-l), V(n)), also called predicted signal, a discrete cosine transform 217 ensuring a frequential conversion of said pixel-based motion-compensated signal, and a subtracting sub-step 124 deriving said modified data signal fiom the difference between said decoded data signal and the output signal of sub-step 217. The intermediate branch 220 avoids a quality drift in time by subtracting fix)m said decoded data signal a motion-compensated signal obtained from said coding error. The data addition branch 202, providing a fi-equential residual signal to be added to the ou^ut signal of the partial decoding branch by means of the sub-st^ 122, comprises the generation of a residual signal fonned by subtracting from the additional data signal 130 with a motion-compensated logo prediction, a discrete cosine transform 218 ensuring a frequential conversion of said residual signal defined by Logo(n)-PRED(Logo(n-l),V(n)). This sub-step 218 relative to said residual signal treats a small number of blocks, because logo will usually occupy little space, its CPU occupation being then limited. Considering that the difference in complexity between a discrete cosine transform and an inverse discrete cosuie transform is very small in terms of CPU consumption, the sub-step 217 has nearly the same complexity as the sub-step 216 and is applied to all blocks defining coding error pictures. As regards the partial decoding branch 219, no more IDCT are performed since data insertion is now done in the frequential domain. It is the same for the re-encoding branch, where no more DCT are performed since modified data are all in the frequential domain. Globally, these suppressions/insertions of DCT/IDCT sub-steps represent a significant gain of CPU capacity since the sub-steps 109 and 110 performed on entire pictures have been suppressed, and the sub-step 217 performed on entire pictures and the sub-step 218 only performed on a reduced number of blocks per pictures have been added. The proposed solution thus represents a cost-effective solution compared with the one of the prior art. Fig.3, derived fix>m Fig.2, depicts another embodiment of the present invention. It is also based on a transcoder arrangement comprising a partial decoding branch for providing a decoded data signal, a re-encoding branch acting on a modified data signal for providing an ou^ut signal, and a data addition branch 202 aiming at introducing the additional data into the decoded data signal Error_I(n). The partial decoding branch, comprising a variable length decoding 107 and an inverse quantization sub-step 108, aims at decoding the input data signal 128 in order to access the decoded data signal £rTor_I(n), also called error residue relative to the input stream, in the frequential domain. This error residue is modified by frequoitial residual data issued from the addition branch 202 by means of the adding sub-step 122. Said frequential residual data results fix}m the frequential conversion by means of the discrete cosine transform 218 appUed to a residual signal formed by the difference between said additional data signal 130 and its motion-compensated version referenced 127 using the same motion vectors V(n) as the motion vectors contained in the input stream. This sub-step 218 treats a small number of blocks since logo usually occupies little space, its CPU consumption being tiien limited. The signal resulting from this addition, defining said modified data signal, between said fi^uential residual data and ErTor_I(n) is re-encoded by means of tiie re-encoding step conq)rising in series a quantization 211, a variable loigth coding 212 and buffer regulations means 213-314. The absence of drift correction does not reduce the output stream quahty to a large extent, since the input stream and data relative to logo have the same motion vector charactoistics, as in the case with a fixed logo inserted into a still iiq)ut video stream such as a still background. In this proposed arrangement, since no more drift correction is performed, a substantial gain in terms of CPU capacity is realized while ensuring a comparatively good video quality. Fig.4, derived finm Fig.2, depicts another embodiment of the present invoation. From an algorithmic point of view, starting fix>m relation 0 relativing to the prior art and using the distributivity of DCT compared to addition/subtraction, it can be written : 7) A(n) = Error_I(n)- DCT( PRED(MEM3(n-l), V(n)) + PRED(Logo(n-1), V(n)) -Logo(n))) With the following notations 03(n): decoded picture number n corresponding to the output signal of Fig.4, I(n): decoded input picture number n> MEM3(n) : picture number n stored in the fi-ame memory 206, The corresponding diagram of Fig.4 governed by relation 7) is close to the one of Fig2. It is also based on a transcoder arrangement comprising a partial decoding branch 219 for providing a decoded data signal, a re-encoding branch 221 acting on a modified data signal for providing an ou^ut signal, an intennediate branch 420 for avoiding a quality drift in time, and a data addition branch 102 for providing a residual signal resulting fix)m Hbs difference between said additional data signal 130 and its motion-compensated version. It differs at said data addition branch level in that it deUvers said residual signal in said intomediate branch by means of a subtracting sub-step 425. Inserted between the motion compensation 205 and the discrete cosine ti^nsform 217 tiiis subtracting sub-stqi delivers to sub-step 217, the difference between the motion-compensated coding error issued from sub-step 216 and said residual signal. Relation 7) demonstrates that only one DCT sub-step is needed to perform the data addition. That is done with tiie sub-stq) 217 ensuring the Sequential conversion both for said residual signal and said motion-compensated coding BOOT in one and the same operation, leading to a cost-effective solution in terms of CPU capacity. This arrangement also preserves a high flexibility in its hardware implementation. Indeed, motion compensation 103 applied to said additional data signal and motion compensation 205 applied to said coding error may be performed by two separate digital signal processors adapted and optimized to characteristics of said residual signal and said coding error. First, considering that the signal contained in the picture memory 206 is defined by the relation 03(n)- I(n)-Logo(n) and that said signal is composed of values of small amplitude corresponding to the coding error generated by the re-encoding step, the motion compensation 205 can thus be done with a limited resolution, while ensuring a good quality as regards the drift correction. Typically, a 4-bits resolution may be used to obtain an acceptable quality, which offers the opportunity of implementation with a dedicated processor including 4-bit macro-instmctions and requiring a little CPU occupation. As regards the motion compensation 103 performed on the signal 130 of greater amplitude, a higher resolution must be used to guarantee a good quality of areas corresponding to the logo. To this end, a generic digital processor may be used with a higher resolution, typically of 8 bits, only on blocks defining the logo area. Fig.5 and Fig.6, derived fit>m Fig.4, depict further embodiments of the present invention. They are also based on a transcoder arrangement comprising a partial decoding branch for providing a decoded data signal, a re-encoding branch acting on a modified data signal for providing an output signal, an intomediate branch for avoiding a quality drift in time, and a data addition branch. They differ at said data addition branch level in that no more motion compensation is performed on the additional data signal 130, thus offering a substantial gain in terms of CPU. It is mdeed possible, fix)m an algorithm point of view and without any quality loss, to use the motion compensation sub-step of the intermediate branch and dedicated to drift correction for said additional data signal by inserting a fiaction of said additional data signal into the coding error generated by the re-encoding branch before motion compensation. In Fig.5, the data addition branch is only composed of a discrete cosine transform 218 applied to signal 130 and delivering a fi-equential additional data signal. This sub-step 218 processes only a small number of blocks corresponding to the logo, so its CPU occupation is limited. Said additional fiiequential data signal is simultaneously inserted into the decoded data signal by means of a first adding sub-step 122 and into the coding error issued from sub-step 123 by means of a second adding sub-step 526. Sub-step 122 delivers the sum of the decoded data signal issued from the partial decoding branch and said frequential additional data signal to die positive input of subtracting sub-step 124. Sub-step 526, at no cost for most digital signal processors, delivers to sub-step 216 the signal representing the sum of the coding error dehvered by sub-step 123 and said frequential additional data signal. In Fig.6, the data insertion is performed by directly inserting said additional data signal 130 into the intermediate branch by means of sub-steps 425 and 526. No more fiiequ«itial conversion is performed on said additional data signal, which represents a gain of CPU capacity. Sub-stq> 526, at no cost for most digital signal processors, delivers to picture memory 206 the signal resulting from the addition between the coding error issued from sub-step 216 and said additional data signal. Sub-step 425, at no cost for most digital signal processors, delivers to sub-step 217 the signal representing the difiTorence between the motion-compensated coding eiror and said additional data signal. Contrary to the arrangement depicted in Fig.4, which allows and justifies the use of a dedicated processor including macro-instructions for motion compensation performed on the coding «Tor, it is not possible to do the same with the arrangements of Fig.5 and Fig.6 since the motion compensation 205 is performed on the coding enor defined by the relation 0(n) - I(n), 0(n) defining any one of die decoded picture number n which coiresponds to the output signal in Fig.5 or Fig.6. Indeed, the amplitude of this signal being approximately that of the signal relative to additional data signal 130, a high resolution motion compensation is required to ensure a good quality of the inserted data, which excludes the use of a specific processor dedicated to low resolution signals. However, Fig.5 and Fig.6 represent an appreciable improvement in terms of gain of CPU capacity over the prior art Fig. 7, derived from Fig.5 and Fig.6, depicts another embodimoit of the present invention. It is also based on a transcoder arrangement comprising a partial decoding branch for providing a decoded data signal, a re-encoding branch acting on a modified data signal for providing an output signal, an intermediate branch for avoiding a quaUty driit in time, and a data addition branch. It di£fers at said data addition branch level, which allows the modification of the input signal by the insertion of a frequential additional data, in that it has only one adding sub-step 122. From an algorithmic point of view, the arrangonent depicted in Fig.7 according to the invention is equivalent to the one described in the prior art of Fig. 1. Indeed, the relation A(n) = B(n) being verified, the relation BUF(VLC(Q(A(n)))) = BUF(VLC(Q(B(n)))) is also verified, wtucn raipues mat me same outpui siream wiu oe obtained, BUF-VLC-Q corresponding to operations pa-formed by respective sub-steps 111/211-112/212-113/213. This proposed arrangement allows that no more separate motion compensation and its associated memory for the signal 130 are used, since said data can be directly inserted into the uitomediate branch, this simplification bdng justified by the linearity of the motion compensation. This merging of the two motion compensations - if the insertion of the adding sub-step 122, at no cost for most digital signal processors, is excluded - represents a substantial gain in terms of CPU occupation and also monory storage. The input signal is then modified by only two sub-steps. The first one corresponds to the discrete cosine transform 218 only applied to die additional data signal 130 and providing a fi-equential additional data signal, this operation being performed only on the few blocks defining the logo area and being thus a low CPU burden. The second one corresponds to the adding sub-step 122 delivering said modified data signal to the re-encoding branch, said modified data signal resulting fi In Fig.2 to Fig.7 described above according to the invention, the input signal data is modified through to the insertion of pixel-based data, designated as the additional data signal 130, by means of adding sub-steps. These inserted data may correspond to a logo, i.e. a single small picture, or a ticker, i.e. successive small different pictures. In both cases, each picture must be pixel-based, e.g. in being encoded according to the so-called bitmap format which corresponds to a roug^ digital image coding. Of course, before insertion by means of the adding or subtracting sub-steps, said signal 130 may derive fitim an adsqited data signal Logo_ori(n), referenced as 731, in order to optimize the quality of the ou^ut signal, as it is only represented in Fig.7 with step 732, for example by changing the luminance or the chrominance levels, as far as their format is still compatible. It is obvious diat such an adaptation does not restrict the scope and the degree of protection of the present invention. This method of modifying data in an encoded data signal can be implemented in several manners, such as by means of wired electronic circuits or, alternatively, by means of a set of instructions stored in a computer-readable medium, said instructions replacing at least a portion of said circuits and being executable under the control of a computer or a digital processor in order to carry out the same functions as fulfilled in said replaced circuits. The invention then also relates to a computer-readable medium comprising a software module which includes computer executable instmctions for performing the steps, or some steps, of the method described above. WE CLAIM : 1. A method of modifying data in an encoded data signal comprising: a) a decoding step for decoding said encoded data signal and providing a decoded data signal, b) a re-encoding step performed on a modified data signal, c) a step for providing a pixel-based residual signal, which is added to said decoded data signal, and which results from the difference between a predicted signal of an additional data signal and said additional data signal, characterized in that it comprises: d) a conversion step for providing a frequential residual signal resulting from the frequential conversion of said pixel-based residual signal, said frequential residual signal being added to said decoded data signal, e) a sub-step for adding said frequential residual signal to said decoded data signal, so as to provide said modified data signal. 2. A method as claimed in claim 1, in which an intermediate step is inserted between said decoding and re-encoding steps, comprising at least means for providing a motion-compensated signal from a coding error generated by said re-encoding step, characterized in that said motion-compensated signal is subtracted from said modified data signal before said re-encoding step. 3. A method of modifying data in an encoded data signal comprising: a) a decoding step for decoding said encoded data signal and providing a decoded data signal, b) a re-encoding step performed on a modified data signal and generating a coding error, (c) an intermediate step inserted between said decoding and re-encoding steps, comprising at least a subtracting operation between said decoded data signal and a motion-compensated signal obtained from said coding error, said subtracting operation defining said modified data signal, characterized in that it comprises sub-steps for inserting an additional data signal into said intermediate step. A method as claimed in claim 3 in which a definition step of a residual signal is carried out, said residual signal resulting from the difference between said additional data signal and its predicted version, characterized in that said residual signal is subtracted from said motion-compensated signal by means of a subtracting sub-step. A method as claimed in claim 3, wherein : a) said additional data signal is added to said coding error by means of an adding sub-step, b) said additional data signal is added to said decoded data signal by means of an adding sub-step. A method as claimed in claim 3, wherein : a) said additional data signal is added to said coding error by means of an adding sub-step, b) said additional data signal is subtracted from said motion-compensated signal by means of a subtracting sub-step. A method of modifying data in an encoded data signal as claimed in claim 3, comprising: a) a decoding step for decoding said encoded data signal and providing a decoded data signal, b) a re-encoding step performed on a modified data signal and generating a coding error, c) an intermediate step for obtaining a motion-compensated signal from said coding error, and comprising at least a subtracting sub-step between said decoded data signal and said motion-compensated signal for providing said modified data signal, characterized in that the sub-steps for inserting the additional data signal into said intermediate step includes adding the additional signal to said modified data signal before said re-encoding step. A transcoding device for adding data to an encoded data signal, comprising: a) decoding means (219) step for decoding said encoded data signal and providing a decoded data signal, b) re-encoding means (221) acting on a modified data signal and generating a coding error, (c) an intermediate branch (220) inserted between said decoding and re-encoding means, comprising at least a subtracting operation between said decoded data signal and a motion-compensated signal obtained from said coding error, said subtracting operation defining said modified data signal, characterized in that it comprises data insertion means (202) for inserting a modifying data signal into said intermediate branch. A transcoding device as claimed in claim 8, comprising: a) decoding means (219) for decoding said encoded data signal, and providing a decoded data signal, b) re-encoding means (221) acting on a modified data signal and generating a coding error, c) an intermediate branch (220) for providing a motion-compensated signal from said coding error, and comprising at least a subtracting sub-step between said decoded data signal and said motion-compensated signal for generating said modified data signal, characterized in that the data insertion means (202) adds the additional data signal to said modified data signal before re-encoding.

Documents:

in-pct-2001-1271-che abstract duplicate.pdf

in-pct-2001-1271-che abstract.pdf

in-pct-2001-1271-che claims duplicate.pdf

in-pct-2001-1271-che claims.pdf

in-pct-2001-1271-che correspondence others.pdf

in-pct-2001-1271-che correspondence po.pdf

in-pct-2001-1271-che description (complete) duplicate.pdf

in-pct-2001-1271-che description (complete).pdf

in-pct-2001-1271-che drawings.pdf

in-pct-2001-1271-che form-1.pdf

in-pct-2001-1271-che form-19.pdf

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in-pct-2001-1271-che others.pdf

in-pct-2001-1271-che pct search report.pdf

in-pct-2001-1271-che pct.pdf

in-pct-2001-1271-che petition.pdf