Title of Invention


Abstract A soluble Conducting printed pillar technology [soluble PPT] route for making small via holes in printed wiring boards technology is developed for the first time, which can be used by the PWB manufactures all over the world.
Full Text

This invention relates to soluble conducting Printed Pillar route for making High Density interconnections on Printed wiring boards used in electronics.
Printed wiring boards are used extensively in all electronics assemblies. They essentially built using double-sided copper clad organic glass epoxy laminates. Holes are drilled mechanically at required locations, and hole barrels metallised through electroless copper plating to establish interlayer electrical connections. The electronics circuit is then etched on the copper planes using standard methods. This type of board is called as Double Sided Plated Through Hole Printed Wiring Board.
As the complexity of the circuit grows, more layers of circuitry are required. Such boards are called as multilayer printed wiring boards [MLBs]. They are produced by separately making several DS boards, and laminating them together using a hot press.
In constructing such multilayer boards, there is need for electrically coimecting the different layers as per the design. This is done by using different "electrical via" connections.
There are three types of such "electrical via" connections possible. They are blind, buried, and through via connections [Refer Fig.l]
'Through vias" are always achieved by drilling, typically 0.60 to 0.40 mm diameter holes, through and through the laminated structure at desired locations, followed by copper plating through the hole barrel to establish electrical connectivity.
However, it is not simple to obtain blind and buried via interconnections by these conventional MLB technologies.
In the drive for miniaturization, the size of the typical drilled hole has reduced from 0.60 mm diameter to less than 0.20 mm diameter. The need for "blind and buried via conections" has drastically increased with the usage of high pin count packages by the

designers. Boards incorporating "blind and buried vias", with hole smaller than 0.20 mm are called as "micro-via boards" and the technologies of making such boards as "micro via technologies", or broadly as high-density interconnections [HDI].
HDI boards require special manufacturing methods, and are built sequentially adding layer by layer of dielectric and conducting layers. Such construction approach is known as build up Multilayer [BuM] constructions.
BuM Constructions use different methods of making small holes [Le. holes less than 200 microns in dia]. Some of the well-known commercial approaches are:
1. Mechanical drilling: Small holes up to 200 microns in dia can be drilled using mechanical drilling machines. It is used to make BuM boards only for through and through hole interconnections.
2. Photo definition: In this method UV light is used create small holes through standard imaging methods. On a core substrate, a photosensitive dielectric material is coated, and imaged for micro vias, which is subsequently metalised by standard methods.
3. Laser ablation: Laser drilling is a well-known technique for making precise holes. Holes as small as 50 microns are drilled and metalised by standard methods.
4. Plasma etching: Plasma is another source used for etching holes in the dielectric
material in the required locations, using copper as metal mask.
5. Chemical milling:Certain dielectric materials such as polyimides can be dissolved in
some solvents. Solvent etching of small holes is another method of making microvia
Limitations of the Prior Art:
In mechanical drilling holes less than 200 microns, and ability go blind or buried is a great challenge. Special drill geometry and machines are required. These dedicated machines are expensive, operating costs high, and productivity is low. Controlling drilled depth makes the machine further complex, niore expensive, and less productive.

Photo definition appears simple, but calls for operations in tighter process windows, and special materials, as well as coating methods are required
Laser ablation is elegant, but require very large investments in infrastructure.
Plasma etching provides very clean holes but is not productive as it calls for batch operations.
Chemical milling is very limited in its applications; can be used only for special dielectrics like polyamides, process steps are cumbersome, and not eco friendly.
Proposed solutions (with examples):
All these above listed BuM methods involve applying the dielectric material over the ntire surface area of the board and then selectively removing the applied material to create micro holes, using techniques described as above.
The approach presented in this patent is novel and new in the sense, as it involves selectively printing the micro-pillars wherever the micro holes are desired, followed by filling the required dielectric material in the rest of the surface to the pillar levels. This is followed by removing the soluble micro-pillars to create micro holes, which is later metalised.
In the accompanying drawings:
Fig. 1 illustrates the three types of "electrical via" connections made in multilayer boards; and
Fig. 2 illustrates the steps of making the micro hole formation according to the process of the present invention.
There are three types of such "electrical via" connections possible. They are blind, buried, and through via connections marked as A, B and C respectively. This is depicted pictorially in Fig. 1.

On a Copper clad laminate D, the first layer image E was etched and the conducting pillars F were formed on the pillar pads. The dielectric G was filled to the pillar height and was cured. The pillars were dissolved to form the microholes H and then the board was metalised to provide the metal plate layer two as shown in I. This is depicted pictorially in Fig.2.
Copper Clad Laminate [FR-4-1.6 mm/DS-18 micron copper] in the size 3" x 6 " was taken. The surface of copper was brush cleaned, and the first layer patterns was achieved through image transfer, development, and etching [or screen printing]. The first layer pattern includes the receiving pads of appropriate dimension.
In the next step the entire surface was coated with a water-soluble screen emulsion [typically poly vinyl alcohol- sensitized with potassium dichromate], followed by drying in hot air oven. The thickness of the emulsion was 60 microns after drying. The emulsion pillars were formed on the corresponding lands by appropriate image exposure and development.
The dielectric material [Epoxy resin] was coated to the height of the pillars using a metal stencil, and cured at 130 C for 45 minutes, followed by second cycle of curing at 155 C for 60 mins in a hot air oven.
The surface was brushed to remove about 10 microns of material, washed with 6% alkali under high pressure to remove the pillar emulsion material. The board now contains micro holes in the respective places.
The board was metalised by known methods of electroless-plating/electroplating, which provided the second copper plane for further similar operations. By repeating the same procedure a sequence of copper layers can be built on either side of the Copper Clad Laminate.

We Claim:
1. Soluble printed pillar route for making high density interconnections on printed
wiring boards comprising of steps:
a. Selectively printing soluble micro-pillars using a soluble paste on the
corresponding lands on the board;
b. Treating the board obtained in step (a) at 80 degrees Centigrade for 15 minutes to
render the pillars partly hard and partly conducting;
c. Coating the laminate/core carrying the partly hard/ conducting pillars with liquid
epoxy material to the height of the pillars and fully curing the epoxy material;
d. Dissolving the soluble pillars to create micro holes followed by metalising the
board; and
e. Making the desired patterns on the top metalised layer by photolithographic
2. Soluble printed pillar route as claimed in claim 1, wherein the core is a copper clad
3. Soluble printed pillar route as claimed in the preceding claims, wherein steps (a) to
(e) of claim 1 are repeated to build further copper layers on both sides of the core
4. Soluble printed pillar route for making microvias for high density interconnections on
multiplayer printed wiring boards.



163-che-2004-claims filed.pdf

163-che-2004-claims granted.pdf



163-che-2004-description(complete) filed.pdf

163-che-2004-description(complete) granted.pdf


163-che-2004-form 1.pdf

163-che-2004-form 19.pdf

163-che-2004-form 26.pdf

163-che-2004-form 3.pdf

Patent Number 202780
Indian Patent Application Number 163/CHE/2004
PG Journal Number 05/2007
Publication Date 02-Feb-2007
Grant Date 26-Oct-2006
Date of Filing 01-Mar-2004
Applicant Address BANGALORE-560 012, KARNATAKA
# Inventor's Name Inventor's Address
PCT International Classification Number H05K 3/40
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA