Title of Invention

A DATA CARRIER AND AN INTEGRATED CIRCUIT

Abstract

A data carrier receives at least two carrier signals which are modulated in respect of the same signal parameter but with different modulation intensities. The data carrier has at least two demodulation stage, each of which having a sensitivity adapted to a modulation intensity used for a modulated carrier signal. The data carrier further has priority means capable of granting priority each time to one demodulation stage in such a manner that a demodulated carrier signal reaches signal processing means only from that modulation stage. [figure 1]

Full Text

We claim: 1. A data carrier (1), which comprises receiver means (2) for receiving a carrier signal (CSM1) modulated in respect of a signal parameter (amplitude) and with a given modulation intensity (100%), and comprises an integrated circuit (4) which comprises connection means (5) which are connected to the receiver means (2), a demodulation stage (15) which is connected to the connection means (5), is arranged to demodulate the modulated carrier signal (CSMI) and to output a demodulated carrier signal (CSI), and has a sensitivity adapted to the given modulation intensity (100%) used for the modulated carrier signal (CSMI), and comprises signal processing means (18) which succeed the demodulation stage (15) and are arranged to process the demodulated carrier signal (CSI), characterized in that the data carrier (1) is arranged to receive at least one additional carrier signal (CSM2, CSM3) which is modulated in respect of the same signal parameter (amplitude) but with an other, given modulation intensity (50%, 10%), the circuit (4) comprising at least one additional demodulation stage (19, 20) which is also connected to the connection means (5) and has an other sensitivity which is adapted to the other, given modulation intensity (50%, 10%) used for the additional modulated carrier signal (CSM2, CSM3), and which is different to the sensitivity of the demodulation stage (15), there being provided priority means (25) which ensure that priority is granted each time to one demodulation stage (15, 19 or 20) only, that a demodulated carrier signal (CSI, CS2 or CS3) reaches the signal processing means (18) only from this one demodulation stage (15, 19 or 20) and that, in the case of simultaneous demodulation of a modulated carrier signal (CSM1, CSM2) by means of at least two demodulation stages (15, 19,20 or 19,20), priority is granted each time to the demodulation stage (15 or 19) having the each time lowest sensitivity, and that a demodulated carrier signal (CS1 or CS2) reaches the signal processing means (18) only from this one demodulation stage (15 or 19). 2. The data carrier (1) as claimed in Claim 1, wherein for each demodulation stage-(t5,-19;"20), the priority means (25) comprise a detection stage (26, 27,28) for detecting the output of a demodulated carrier signal (C51, C52, C53) by the relevant demodulation stage (15, 19,20), that each detection stage (26, 27, 28) can output a detection signal (D51, D52, D53), that there are provided control means (12) which can be supplied with the detection signals (D51, D52, D53) and ensure that, in dependence on the detection signals (D51, D52, D53), priority is granted each time to one demodulation stage (15, 19 or 20) only, that a demodulated carrier signal (C51, C52 or C53) reaches the signal processing means (18) only from this one demodulation stage (15, 19 or 20) and that, in the case of simultaneous demodulation of a modulated carrier signal (C5M1, C5M2) by means of at least two demodulation stages (15, 19,20 or 19, 20), priority is granted each time to the demodulation stage (15 or 19) having the each time lowest sensitivity, and that a demodulated carrier signal (C51 or C52) reaches the signal processing means (18) only from 15 this one demodulation stage (15 or 19). 3. The data carrier (1) as claimed in Claim 2, wherein the priority means (25) comprise the demodulation stages (15, 19,20), that the demodulation stages (15, 19,20) are arranged so as to be deactivatable and activatable 20 by means of control signals (554, 555, 556), and that the control means (12) are arranged to generate and output control signals (554, 555, 556) for deactivating and activating the demodulation stages (15, 19,20). 4. The data carrier (1) as claimed in Claim 2, wherein the priority means (25) comprise signal forwarding stages (32, 33, 34) which are connected in series with the demodulation stages (15, 19,20), that the signal forwarding stages (32,33,34) are arranged so as to be deactivatable and activatable by means of control signals (551, 552, 553), and that the control means (12) are arranged to generate and output control signals (551, 552, 553) 30 for deactivating and activating the signal forwarding stages (32, 33, 34). 5. The data carrier (1) as claimed in Claim 1, wherein the priority means (25) are arranged, after having granted priority to a demodulation stage (15, 19 or 20), to sustain the granted priority for a given priority period with a given duration. 6. An integrated circuit (4) for a data carrier (1), which circuit comprises connection means (5) for receiving a carrier signal (CSM1) modulated .in respect of a signal parameter (amplitude) and with a given modulation intensity (100%), comprises a demodulation stage (15) which is connected to the connection means (5), is arranged to demodulate the modulated carrier signal (CSMI) and to output a demodulated carrier signal (CSI), and has a sensitivity adapted to the given modulation intensity (100%) used for the modulated carrier signal (CSMI), and comprises signal processing means (18) which succeed the demodulation stage (15) and are arranged to process the demodulated carrier signal (CSI), wherein the data carrier (1) is arranged to receive at least one additional carrier signal (CSM2, CSM3) which is modulated in respect of the same signal parameter (amplitude), but with an other, given modulation intensity (50%, 10%), the circuit (4) comprising at least one additional demodulation stage (19, 20) which is also connected to the connection means (5) and has an other sensitivity, which is adapted to the other, given modulation intensity (50%, 10%) used for the additional modulated carrier signal (CSM2, CSM3) and which is different to the sensitivity of the demodulation stage (15), there being provided priority means (25) which ensure that priority is granted each time to one demodulation stage (15, 19 or 20) only, that a demodulated carrier signal (CSI, CS2 or CS3) reaches the signal processing means (18) only from this one demodulation stage (15, 19 or 20) and that, in the case of simultaneous demodulation of a modulated carrier signal (CSM1,CSM2) by means of at least two demodulation stages (15, 19,20 or 19,20), priority is granted each time to the modulation stage (15 or 19) having the each time lowest sensitivity, and that a demodulated carrier signal (CSI or CS2) reaches the signal processing means (18) only from this one demodulation stage (15 or 19). 7. The integrated circuit (4) as claimed in Claim 6, wherein for each demodulation stage (15, 19,20) the priority means (25) comprise a detection stage (26, 27,28) for detecting the output of a demodulated carrier signal (CS1, CS2, CS3) by the relevant demodulation stage (15, 19,20), that each detection stage (26, 27, 28) can output a detection signal (DSl, DS2, DS3), that there are provided control means (12) which can be supplied with the detection signals (DSl, DS2, DS3) and ensure that, in dependence on the detection signals (DSl, DS2, DS3), priority is granted each time to one demodulation stage (15, 19 or 20) only, that a demodulated carrier signal (C51, C52 or C53) reaches the signal processing means (18) only from this one demodulation-Stage (15;-19 or 20) and that, in the case of simultaneous demodulation of a modulated carrier signal (C5M1, C5M2) by means of at least two "demodulation stages (15, 19,20 or 19,20), priority is granted each time to the demodulation stage (15 or 19) having the each time lowest sensitivity, and that a demodulated carrier signal1 (C51 or C52) reaches the signal processing means (18) only from this one demodulation stage (15 or 19). 8. The integrated circuit (4) as claimed in Claim 7, wherein the priority means (25) comprise the demodulation stages (15, 19,20), that the demodulation stages (15, 19,20) are arranged so as to be deactivatable and activatable by means of control signals (554, 555, 556), and that the control means (12) are arranged to generate and output control signals (554, 555, 556) for deactivating and activating the demodulation stages (15, 19,20). 9. The integrated circuit (4) as claimed in Claim 7, wherein the priority means (25) comprise signal forwarding stages (32, 33, 34) which are connected in series with the demodulation stages (15, 19,20), that the signal forwarding stages (32,33,34) are arranged so as to be deactivatable and activatable by means of control signals, and that the control means (12) are arranged to generate and output control signals (551,552,553) for deactivating and activating the signal forwarding stages (32, 33, 34). 10. The integrated circuit (4) as claimed in Claim 6, wherein the priority means (25) are arranged, after having granted priority to a demodulation stage (15, 19 or 20), to sustain the granted priority for a given priority period with a given duration.

Documents:

abs-in-pct-2000-che-31.jpg

in-pct-2000-che-031-abstract.pdf

in-pct-2000-che-031-claims (original).pdf

in-pct-2000-che-031-claims duplicate.pdf

in-pct-2000-che-031-correspondance others.pdf

in-pct-2000-che-031-correspondance po.pdf

in-pct-2000-che-031-description complete duplicate.pdf

in-pct-2000-che-031-description complete original.pdf

in-pct-2000-che-031-drawings.pdf

in-pct-2000-che-031-form 1.pdf

in-pct-2000-che-031-form 26.pdf

in-pct-2000-che-031-form 3.pdf

in-pct-2000-che-031-form 5.pdf

in-pct-2000-che-031-other documents.pdf

in-pct-2000-che-031-pct.pdf