Title of Invention	A PRINT CONTROLLER TO DRIVE AN INK DROP PRINT HEAD
Abstract	"A PRINT CONTROLLER TO DRIVE AN INK DROP PRINT HEAD" A print controller to drive an ink drop print head comprising an interface at which to receive compressed page data; decoders to decode respective types of image planes in the received compressed page data; and a half-toning and composing unit to composite image plane data; the half-toning and composing unit comprising a dot merger unit taking bits from the respective planes as inputs; and a color mask register holding masking bits in number equal to the number of image planes; respective input bits to the dot merger unit being ANDed with respective color mask register bits and the resultant bits ORed together to form an output bit in a channel for which there is an ink at the print head.

Title of Invention

A PRINT CONTROLLER TO DRIVE AN INK DROP PRINT HEAD

Abstract

"A PRINT CONTROLLER TO DRIVE AN INK DROP PRINT HEAD" A print controller to drive an ink drop print head comprising an interface at which to receive compressed page data; decoders to decode respective types of image planes in the received compressed page data; and a half-toning and composing unit to composite image plane data; the half-toning and composing unit comprising a dot merger unit taking bits from the respective planes as inputs; and a color mask register holding masking bits in number equal to the number of image planes; respective input bits to the dot merger unit being ANDed with respective color mask register bits and the resultant bits ORed together to form an output bit in a channel for which there is an ink at the print head.

Full Text	PRINT ENGINE/CONTROLLER WITH COLOR MASK FIELD OF THE INVENTION The invenlLon relates to a print engine/coniroller (PEC) able to receive print data and generate and output in a formal suited to what inks are available at the print head. BACKGROUND OF THE INVENTION Arangeofprinleriypes have evolved wherein an image is constructed from ink selectively applied to a page in dot formal. !n US patent number 6045710 titled "Self-aligned construction and manufacturing process for monolithic print heads' lo the inventor Kia Silverbrook there is sei out an assessment of the prior art to drop on demand printers along with its panicular manufacturing process. A mieroelectomechanical drop on demand prim head hereafter referred to as a Memjet print head has been . described in co-pending United States Paient Applications filed simultaneously to the present application and hereby incorporated by cross reference: A distribution system of the above kind will output page data in a particular format, providing image data in a range of image planes. These image planes may be received at printers with print heads not fitted with a corresponding number of ink channels. Some clients to the system might desire to move image planes from one ink channel lo another. A print engine/controller ideally addresses these issues. More speed and flexibility in selection of output channels at the print head depends on development of both print head and its engine/controller. The print engine/controller architecture ideally needs to be designed to push data in volume to selected ink chanriels in the print head at high speed. SUMMARY OF THE INVENTION In one form ihe invention resides in a print engine/controller to drive an ink drop print head comprising: an interface at ivhich lo receive compressed page dala; decoders lo decode respective types of image planes in Ihe received compressed page data; and a half-loner/compositor to composite image plane data; the half-toner/compositor including; a dot merger unit taking bits from the respective planes as inputs; and a color mask register holding masking bits in number equal to the number of image planes; tespective input bits, to the dot merger unit being ANDed with respective color mask register bits and the resullant bils Ored together to form an output bit in a channel for which there is an ink at the print head. The dot merger unit provides a means by which to map data bits to the respective inks at a print head. A color mask register within the dot merger unit holds a pattern of bits that effect the mapping of image bils input to ihe dot merger unit. Image data might be delivered to a client with image planes in all of CMY and K together with data lo go into tags on an output page in infrared ink. Speed might be such that a fixative needs to be used. The ideal print head then works with six ink channels. Some printers may not provide for all of CMY and K and K may need to be expressed through use of the CMY channels. It might be desired in some circumstances to put a high-resolution plane otherwise destined for the K channel into one of the color channels. These outcomes are met through what bits are loaded into the color mask register. BRIEF DESCRIPTION OF THE DRAWINGS FiG. 1 is a diagram illuslraiing data How and .the functions performed by the print engine controller. FIG. 2 shows the print engine controller in the context of the overall printer system architecture. FiG. 3 illustrates the print engine controller architecture. FIG. 4 illustrates the external interfaces to the halfloner/compositor unit (HCU) of FIG. 3. FIG. 5 is a diagram showing internal circuitry to the HCU of FIG. 4. FIG. 6 shows a block diagram illustrating the process within the dot merger unit of FIG. 5. FIG. 7 shows a diagram illuslraiing the process within the dot reorganization unit of FIG. 5. FIG. 8 shows adiagramillusiratinglheprocess within the line loader/format unit (LLFU) of FIG. 5. FIG. 9 is a diagram showing internal circuitrj'to generate color data in the LLFU of FIG. 8. FIGs. !0 and 11 illustrate components of the LLFU seen in FIG. 9, DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typically 12 mch print head width is controlled by one or more I'BCs. as described below, to allow full-bleed printing of both A4 and Letter pages. Six channels of colored ink are the expected maximum in the present printing environment, these being; • CMY. for regular color printing. • K. for black text and other black printing. • IR (infrared), for tag-enabled applications, • F (fixative), to enable printing at high speed. Because the printer is to be capable of fast printing, a fixative may be required to enable the ink to dry before the next page has completed printing at higher speeds. Otherwise the pages might bleed on each other. In lower speed printing environments the fixative will not be required. A PEC might be built in a single chip ii> interface with a print head It will contain four basic levels of functionality: receiving compressed pages via a serial interface such as lEEF. 1394 • a prim engine for producing a page from a compressed form. The print engine functionality includes expanding the page image, dithering the contone layer, compositing the black layer over the contone layer, optionally adding infrared tags, and sending the resultant image to the prim head. • a print controller for controlling the print head and stepper motors. • iwo standard low-speed serial ports far communication with QA chips. Note that there ought to be two ports and not a single port to ensure strong security during the authentication procedure. In Figure 1 is seen the flow of data to send a document from computer syswm to printed page. A document is received at 11 and loaded to memory buffer 12 wherein page layouts may be effected and any required objects might be added. Pages from memory 12 are rasierized at 13 and compressed at 14 prior to transmission to the print engine controller 10, Pages are received as compressed page images within the prim engine controller 10 into a memory buffer 15, from which they are fed to a page expander 16 wherein page images are retrieved. Any requisite dither might be applied to any contone layer at 17, Any black bi-level layer might be composited over the conlone layer at 18 together with any infrared tags at \9. The composited page data is printed at 20 to produce page 21, The print engine/controller takes the compressed page image and starts the page expansion and printing in pipeline fashion. Page expansion and printing is preferably pipelined because it is impractical to store a sizable bi-level CMYK+IR page image in memory. The first stage of the pipeline expands a JPEG-compressed conlone CMYK layer (see below), expands a Group 4 Fax-compressed bi-level dither matrix selection map (see below), and expands a Group 4 Fax-compressed high resolution black layer (sec below), all in parallel. In parallel with this, the tag encoder encodes bi-lcvel IR tags with data from the compressed page image. The second stage dithers the contone CMYK layer using a ililher matrix selected by the dither matrix select map, composites the bi-level black layer over the resulting bi-lcvel K layer and adds the IR layer to the page, A fixative layer is also generated at each dot position wherever there is a need in any of C, M, Y, K, or IR channels. The last stage prints the bi-level CMYK+IR data through the print head via a print head interface (see below). In FIG. 2 is seen how the print engine/controller 10 fits within the overall printer system architecture. The various components of the printer system might include ■ a Prinl Engine'ConiroUer (PEC) A PEC chip 10. or chips, is responsible for receiving the compressed page images for storage in a memory buffer 24, performing the page expansion, black layer compositing and sending the dot data to the print head 23. It may also communicate with QA chips 25,26 and provides a means of retrieving print head characteristics to ensure optimum printing The PEC is the subject of this specification. ■ a memory buffer. The memory buffer 24 is for storing the compressed page image and for scratch use during the printing of a given page. The construction and working of memory buffers is known to those skilled in (he art and a rangeof standard chips and techniques for their use might be utilized in use of the PEC of the invention. a masier QA chip. The master chip 25 is ideally matched to replaceable ink cartridge QA chips 26. The construction and working of QA units is known to those skilled in the art and a range of known QA processes might be utilized in use of the PEC of the invention. For example, a QA chip is described in co-pending United Slates Patent Applications; USSN Our Docket IN umber Our Title TBA AUTHOl Validation Protocol and System 09/112,763 AUTH02 Circuit for Protecting Chips Against IDD Fluctuation Attacks 09/112,737 AUTH04 Method for Protecting On-Chip Memory (Flash and RAM) 09/112,761 AUTH05 Method for Making a Chip Tamper-Resistant 09/113,223 AUrH06 A system for authenticating physical objects TBA AUTH07 Validation Protocol and System TBA AUTH08 Validation Protocol and System 09/505,003 AUTI109 Consumable Authentication Protocol and System 09/517,608 AUTHIO Consumable Authentication Protocol and System 09/505,147 AUTHll Consumable Authentication Protocol and System 09/505,952 AUTH12 Unauthorized Modification of Values Stored in Flash Memory TBA AUTH13 A System for the Manipulation of Secure Data 09/516.874 AUTH14 An Authentication Chip with Protection from Power Supply Attacks TBA AUTHI5 Shielding Manipulations of Secret Data QA chip communication may be best included within the overall functionality of the PEC chip since it has a role in the expansion of the image as vvell as running the physical print head. By locating QA chip communication there it can be ensured ihal there is enough ink to print the page. Preferably the QA embedded in the print head assembly is implemented using an authentication chip. Since it is a master QA chip, it only contains authentication keys, and does not contain user-data. Howevet, it must match the itik catltidge's QA chip, The QAchip in the ink cartridge contains information required for maintaining the best possible print quality', and is implemented using an authentication chip. Preferably a 64 MBit (8 MByte) memory buffer is used to store the compressed page image. While one page is being written to the buffer another is being read (double buflering). In addition, the PEC uses the memory to buffer the calculated dot information during the printing of a page. During the printing of page N, the buffer is used for: • Reading compressed page N • Reading and writing the bi-level dot information for page ;V • Writing compressed page ,V+ / Preferably a PEC chip will incorporate a simple micro-controller CPU core 35 to perform the following functions: perform QAchip authentication protocols via serial interface 36 between print pages run Ihe stepper motor via a parallel interface 91 during a print (the stepper motor requires a 5 KHz process) synchronize Ihe various portions of the PEC chip during a print provide a means of interfacing with external data requests (programming registers etc.) provide a means of interfacing with print head segment low-speed data requests (such as reading the characterization vectors and writing pulse profiles) ■ provideameansof writing the portrait and landscape tag structures to external DRAM Since all of the image processing is performed by dedicated hardware, the CPU does not have to process pixels. As a result, the CPU can be extremely simple. A wide variety ofknown CPU cores are suitable: it can be any processor core with sufficient processing power to perform the required calculations and control funcfions fast enough. An example ofa suitable core is a Philips 8051 micro-controller running at about 1 MHz, Associated with the CPU core 35 may be a program ROM and a small program scratch RAM. The CPU communicates with the other units within the PEC chip via memory-mapped I/O. Particular address ranges may map to particular units, and within each range, to particular registers within that particular unit. This includes the serial 36 and parallel 91 interfaces, A small program flash ROM may be incorporated into the PLC chip. Its size depends on the CPU chosen, but should not be more than 8KB. Likewise, a small scratch RAM area can be incorporated into the PEC chip. Since the program code does not have to manipulate images, there is no need for a large scratch area. The R.AM size depends on the CPU chosen (e.g. stack mechanisms, subroutine calling convenfions. register sizes etc), but should not be more than about 2 KB, A PEC chip using the above referenced segment based page wide print head can reproduce black at a full dot resolution (typically 1600 dpi), but reproduces contone color at a somewhat lower resolution using halftoning. The page description is therefore divided into a black bi-level layer and a contone layer. The black bi-level layer is defined to composite over the contone layer. The black bi-level layer consists ofa bitmap containing a 1-bit opacity for each pixel, fhis black layer malle has a resolution that is an integer factor of the printer's dot resolution. The highest supported resolufion is 1600 dpi, i.e. the printer's full dot resolution. The contone layer consists ofa bitmap containing a 32-bit CMYK color for each pixel, where K is optional. This contone image has a resolution thai is an integer factor of the primer's dot resolution. The highest supported resolution is320ppi over 12 inches for a single PEC, i,e. one-fifth the printer's dot resolution. For higher contone resolutions multiple PECs are tequived, with each PEC producing an strip of the output page. The contone resolution is also typically an integer factor of the black bi-level resolufion, to simplify calculations in the RlPs, This is not a requirement, however. The black bi-level layer and the contone layer are both in compressed form for efficient storage in the printer's internal memory. In FIG, 3 is seen the print engine architecture. The print engine's page expansion and printing pipeline consists ofa high speed serial interface 27 (such as a standard IEEE 1394 interface), a standard JPEG decoder 28, a standard Group 4 Fax decoder. a custom halttoncr/compositor unit 29, a custom tag encoder 30, a line loader/fotTnatter unit 31, and a custom interface 32 to the print head 33. The decoders 28,88 and encoder 30 are buffered to the hal ft oner/compositor 29. The tag encoder 30 establishes an infrared tag or tags lo a page according to protocols dependent on what uses might be made of the page and the actual content of a tag is not the subject of the present invenfion. lite print engine works in a double buffered way. One page is loaded into DRAM 34 via DRAM interface 89 and data bus 90 from the high speed serial interface 27 while the previously loaded page is read from DRAM 34 and passed through the print engine pipeline. Once the page has finished printing, then the page just loaded becomes the page being printed, and a new page is loaded via the high-speed serial interface 27. At the first Stage the pipeline expands any JPEG-comptessed contone (CMYK) la^er, and expands any of two Group 4 Fax.-compressed bi-level data streams. The two streams are the black layer (although the PEC is actually color agnostic and this bi-level layer can be directed to any of the output inks), and a matte for selecting between dither matrices for contone dithering (see below). At the second stage, in parallel with the first, is encoded any tags for later rendering in either IR or black ink. Finally the third stage dithers the contone layer, and composites position tags and the bi-level spatl layer over the resuUing bi-level dithered layer. The data stream is ideally adjusted to create smooth transifions across overlapping segments in the print head and ideally it is adjusted to compensate for dead nozzles in the print head. Up to 6 channels of bi-level data are produced from this stage. Note thai not all 6 channels ma>' be present on the print head. For example, the print head may be CMY only, with K pushed into the CMY channels and IR ignored. Alternatively, the position tags may be printed in K if IR ink is not available (or for testing purposes). The resultant bi-level CMYK-IR dot-data is bufl'ered and formatted for printing on the print head 33 via a set of line buffers (see below). The majority of these line buffers might be ideally stored on the of!-ehipDRAM 34. The final stage prints the 6 channels of bi-level dot data via the print head interface 32. Compression is used in a printing system that employs the PKC. This is to reduce bandwidth requirements between a host and PEC, as well as to reduce memory requirements for page storage. At 267 ppi, a Letter page of contone CMYK data has a size of 25MB, Using lossy contone compression algorithms such as JPEG (see below), con lone images compress with a ratio up to 10:1 without noticeable loss of quality, giving a compressed page size of 2.5MB. At 800 dpi, a Letter page of bi-level data has a size of 7MB. Coherent data such as text compresses very well. Using lossless bi-level compression algorithms such as Group 4 Facsimile (sec below), ten-point text compresses with a ratio of about 10:1, giving a compressed page size of 0.8MB. Once dithered, a page of CMYK contone image data eonsistsof 114MB of bi-level data. The two-layer compressed page image format described below exploits the relative sirengthsof lossy JPEG contone image compression and lossless bi-level text compression. The format is compact enough to be storage-efficient, and simple enough to allow straightforward real-time expansion during printing. Since text and images normally don't overlap, the normal worst-case page image size is 2,5MB (i,e, image only), while the nofitial best-case page image size is 0,8MB (i.e. text only). The absolute worst-case page image si^e is 3.3MB (i.e. text over image), Assuming a quarter of an average page contains images, the average page image size is 1.2MB. A Group 3 Facsimile compression algorithm (see ANSI/EIA 538-1988, Facsimile Coding Schemes and Coding Coniro! hmctions for Grmp 4 Facsimils Equipmem, August 1988) fin be used lo losslessly comprisses bi-level data for transmission over slow and noisy telephone lines. The bi-leve! data represents scanned black text and graphics on awhile background, and the algorithm is tuned for this class of images (it is explicitly not luned, for example, for halfioned bi-k\cl images). The yD Group 3 algorithm runlength-cncodes each scanlineand then Huffman-encodes the resulting runlengths- Runlengths in the range 0 to 63 are coded with lerminaiing codes. Runlengths in the range 64 to 2623 are coded with m«fc-wp codes, each representing a muhiple of 64, followed by a terminating code. Runlengths exceeding 2623 are coded with multiple make-up codes followed by a terminating code. The Huffman tables are fixed, but are separately tuned for black and white runs (except for make-up codes above 1728, which arc common). When possible, the 2D Group 3 algorithm encodes a scanline as a set of short edge deltas (0, ± I, ±2, ±3) with reference to the previous scanline. The delta symbols are entropy-en coded (so that the zero delta symbol is only one bit long etc.) Edges within a 2D-encoded line that can't be delta-encoded are runlength-encoded, and are identified by a prefix. ID- and 2D-encoded lines are marked differently. ID-encoded lines are generated at regular intervals, whether actually required or not, to ensure that the decoder can recover from line noise with minimal image degradation. 3D Group 3 achieves compression ratios of up lo6:l (see Urban, S J., "Review' of standards for electronic imaging for facsimile systems", Journal of Electronic Imaging. Vol,l(l), Januao' 1992. pp,5-2l). A Group i Facsimile algorithm (see ANSI/EIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) losslessly compresses bi-level data for transmission over error-free communications lines (i.e. the lines are truly error-free, or error-correction is done at a lower protocol level). The Group 4 algorithm is based on the 2D Group 3 algotithsti, with the essential modificatioti that since transmission is assumed to be error-free. ID-eneoded lines are no longer generated at regular intervals as an aid to error-recovery. Group 4 achieves compression ratios ranging from 20:1 to 60:1 for the CCITT set of test images. The design goals and performance of the Group 4 compression algorithm qualify it as a compression algorithm for the bi-leve! layers. However, its Huffman tables are tuned to a lower scanning resolution (100-400 dpi], and it encodes runlengths exceeding 2623 awkwardly. At 800 dpi, our maximum runlength is currently 6400. Although a Group 4 decoder core would be available for use in PEC, it might not handle runlengths exceeding those normally encountered in 400 dpi facsimile applications, and so would require modification. The (typically 1600 dpi) black layer is losslessly compressed using G4Fax at a typical compression ratio exceeding 10:1. A (typically 320dpi) dither matrix select layer, which matches the conlone color layer, is losslessly compressed using G4Fax at a typical compression ratio exceeding 50:1. The Group 4 Fax (G4 Fax) decoder is responsible for decompressing bi-level data. Bi-level data is limited to a single spot color (typically black for text and line graphics), and a dilhcr matrix select bit-map for use in subsequent dithering of the contone data (decompressed by the JPKO decoder). The input to the G4 Fax decoder is 2 planes of bi-level data, read from the external DRAM. The output of the G4 Fax decoder is 2 planes of decompressed bi-level data. The decompressed bi-level data is seail to the Halfionei/CompositoT Unit (HCU) for the next stage in the printing pipeline. Two bi-level buffers provides the means for transferring the bi-level data between the 04 Fax decoder and the HCU, Each decompressed bi-level layer is output to two line buffers. Each buffer is capable of holding a full 12 inch line of dots at the expected maximum lesolulion. Having two line butYcrs allows one line to be read by the HCU while the other line is being written to by the G4 Fax decoder. This is important because a single bi-level line is typically less than 1600 dpi. and must therefore be expanded in both the dot and line dimensions. If the buffering were less than a full line, the G4 Fax decoder would have to decode the same line multiple times, - once for each output 60Qdpi dotline. Spot color I is designed to allow high resolution dot data for a single color plane of the output image. While the contone layers provide adequate resolution for images, spot color I is targeted at applications such as text and line graphics (topically black). When used as text and line graphics, the typical compression ratio exceeds 10:1, Spot color I allows variable resolution up to 1600dpi for maximum print quality. Each of the two line buffers is therefore total 2400 bytes (12 inches X 1600 dpi = 19.200 bits). The resolution of the dither matrix select map should ideally match the contone resolution. Consequently each of the two line buffers is therefore 480 bytes (3840 bits), capable of storing 12 inches at 320 dpi. When the map matches the contone resolution, the typical compression ratio exceeds 50:1. [n order to provide support for: • 800 dpi spot color I layer (typically black) • 320 dpi dither matrix select layer the decompression bandwidth requirements are 9,05 MB/sec for 1 page per second performance (regardless of whether the page width is 12 inches or 8,5 inches), and 20 MB/sec and 14,2 MB/sec for 12 inch and 8,5 inch page widths respectively during maximum printer speed performance (30,000 lines per second). Given that the decompressed data is output to a line bufier, the G4 Fax decoder can readily decompress a line from each of the outputs one at a time. The G4 Fax decoder is fed directly from the main memon,' via the DRAM interface. The amount of compression determines the bandwidth requirements to the external DRAM, Since G4 Fax is lossless, the complexity of the image impacts on the amount of data and hence the bandwidth, typically an 800 dpi black text/graphics layer exceeds 10:1 compression, so the bandwidth required to print I page per second is 0,78 MB/sec. Similarly, a typical 320 dpi dither select matrix compresses at more than 50:1, resulting in a 0.025 MB/sec bandwidth. The fastest printing speed configuration of 320 dpi for dither select matrix and 800 dpi for spot color 1 requires bandwidth of 1,72 MB/sec and 0.056 MB/sec respectively, A total bandwidth of 2 MB/sec should therefore be more than enough for the DRAM bandwidth. The G4 Fax decoding functionality is implemented by means of a G4 Fax Decoder core, A wide variety of G4Fax Decoder eorcs are suitable: it can be any core with sufficient processing power to perform the required calculations and control functions fast enough. Il must be capable of handling runlengths exceeding those normally encountered in 400 dpi facsimile applicavions. and so may tetjuire modification. A JPEG compression algorithm (see ISO/IEC 19018-1:1994, Information technology - Digital compression and coding of continuous-lone still images: Requtremenis and guidelines, 1994) lossily compresses a contone image at a specified quality level. It introduces imperceptible image degradation at compression ratios below 5:1, and negligible image degradation at compression ratios below 10 1 (see Wallace, G.K.. "The JPEG Still Picture Compression Standard", Communications ofthe ACM. Vol,34, No.4, April 1991, pp.30-44). JPEG typically first transforms the image into a color space that separates luminance and chrominance into separate color channels. This allows the chrominance channels lo be subsampled without appreciable loss because of the human visual system's relatively greater sensitivity to luminance than chrominance. Alter this first step, each color channel is compressed separately. The image is divided into 8>i8 pixel blocks. Each block is then transformed into the frequency domain via a discrete cosine transform (DCf). This transformation has the effect of concentrating image energy in relatively lower-frequency coefficients, which allows higher-frequency coefticients to be more crudely quantized. This quantization is the principal source of compression in JPEG, further compression is achieved by ordering coefficients by frequency to maximize the likelihood of adjacent zero coefficients, and then run length-encoding runs of zeroes. Kinally, the runlengths and non-zero frequency coefficients are entropy coded. Decompression is the inverse process of compression. The CMYK (or CMY) contone layer is compressed to a planar color JPEG bytestream. If luniinance/chromi nance separation is deemed necessary, either for the purposes of table sharing or for chrominance subsampling, then CMYK is converted to YCrCb and Cr and Cb are duly subsampled. The JPEG bytestream is compleie and self-contained. It contains all data required for decompression, including quantization and Huffman tables. The JPEG decoder is responsible for performing the on-the-lly decompression of the contone data layer. The input to the JPEG decoder is up to 4 planes of contone data. This will typically be 3 planes, representing a CMY contone image, or 4 planes representing a CMYK contone image. Each color plane can be in a different resolution, although typically all color planes will be the same resolution. The contone layers are read from the external DRAM. The output ofthe JPEG decoder is the decompressed contone data, separated into planes. The decompressed contone image is sent to the halftoner/compositor unit (HCU\| 29 for the next stage in the printing pipeline. The 4-plane contone buffer provides the means for transferring the conlone data between the iPEG decoder and the HCU 29. Each color plane ofthe decompressed contone data is output to a set of two line buffers (see below), Kach line buffer is 3840 bytes, and is therefore capable of holding 12 inches of a single color plane's pixels at 320 ppi. The line buffering allows one line buffer to be read by the HCU while the other line buffer is being written lo by the JPEG decoder. This is important because a single contone line is typically less than 1600 ppi, and must therefore be expanded in both the dot and line dimensions. If the buffering were less than a full line, the JPEG decoder would have to decode the same line multiple limes - once for each output 600dpi dotline. Although a variety of resolutions is supported, there is a tradeoff between the resolution and available bandwidth. As resolution and number of colors increase, bandwidth requirements also increase. In addition, the numberof segments being targeted by the PEC chip also affects the bandwidth and possible resolutions, Note that since the contone image is pyocessed in a planar format, each color plane can be stored at a different resolution (for example CMY may be a higher resolution than the K plane). The highest supported contone resolution is 1600ppi (matching the printer's full dot resolution). However there is only enough output line buffer memory to hold enough contone pixels for a 320ppi line of length 12 inches. If the full 12 inchesof output was required at higher conlone resolution, multiple PEC chips would be required, although it should be noted that the final output on the primer will still only be bi-level. With support for 4 colors ai 320ppi. the decompression output bandwidth requirements are 40 MB/sec for I page per second performance (regardless of whether tlie page width is 12 inches or 8-5 inches), and 88 MB/sec and 64 MB/SEC for U inch anJ 8.5 inch page widths respectively during maximum printer speed performance (30,000 lines per second). The JPEG decoder is fed directly from the main memory via the DRAM interface. The amount of compression determines Ihe bandwidth requirements to the eyernal DRAM, As the level of compression increases, the bandwidth decreases, but the quality of the final output image can also decrease. The DRAM bandwidth for a single color plane can be readily calculated by applying Ihe compression factor to Ihe output bandwidth. For example, a single color plane at 320 ppi with a compression factor of 10:1 requires 1 MB/sec access to DRAM to produce a single page per second. The JPEG functionality is implemented by means of a JPEG core. A wide variety of JPEG cores are suitable: it can be any JPEG core with sufficient processing power to perform the required calculations and control functions fast enough. For example, the BTG X-Malch core has decompression speeds up to UO MBytes/sec. which allows decompression of 4 color planes at conlone resolutions up to 400ppi for the maximum printer speed (30,000 lines ai 1600dpi per second), and SOOppi for I page/sec printer speed. Note that the core needs to only support decompression. reducing Ihe requirements thai are imposed by more generalized JPEG compression/decompression cores. The size of the core is expected to be no more than 100,000 gates. Given that the decompressed data is output to a line buffer, the JPEG decoder can readily decompress an entire line for each of the color planes one at a lime, thus saving on context switching during a line and simplifying the control of the JPEG decoder, 4 contexts must be kepi (I context for each color plane), and includes current address in the exiernal DRAM as well as appropriate JPEG decoding parameters In EiG. 4 Ihe halftoner/compositor unit (HCU) 29 combines the functions of halftoning the contone (typically CMYK) layer to a bi-level version of the same, and compositing ihe spoil bi-level layer over the appropriate halftoned conlone layer(s). If there is no K ink in Ihe primer, ihe HCU 29 is able to map K to CMY dots as appropriate, ll also selects between two dither matrices on a pixel by pixel basis, based on the corresponding value in the dither matrix selecl map. The input to the HCU 29 is an expanded conlone layer (from the JPEG decoder unit) through buffer 37, an expanded bi-level spotl layer through buffer 38, an expanded dithcr-malrix-selcci bitmap at typically the same resolution as the conlone layer through buffer 39, and tag data at full dot resolution through buffer 40, The HCU 29 uses up lo iwo dither matrices, read from the external DRAM 34. The output from the HCU 29 to the line loader/format unit (LLFU) at 41 is a se\ of pointer re^olmion bi-level image lines in up to 6 color planes. Typically, the contoue layer is CMYK or CMY. and the bi-level spotl layer is K. In FIG. 5 is seen the HCU in greater detail Once started, the HCU proceeds until it detects an end-of-page condition, or until it is explicitly slopped via its control register. The first task of the HCU is lo scale, in the respective scale units such as the scale unit 43, all data, received in the buffer planes such as 42, to printer resolution both horizoniatly and vertically. The scale unit provides a means of scaling contone or bi-level data to printer resolution boih horizontally and vertically. Scaling is achieved by replicating a data value an integer number of limes in both dimensions. Processes by which to scale data will be familiar to those skilled in the art. Two control bits are provided to the scale unit 43 by the margin unit 57: advance dot and advance line. The advance doi bit allows the stale machine to generate multiple instances of the same dot data (useful for page margins and creating dot data for overlapping segments in the print head). Ihe advance line bit allows the slate machine lo control when a particular line of dots has been finished, thereby allovving truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-line logic, fhe input to ihe scale unil is a full line buffer. The line is used scale faclor times to effect vertical up-scaling via line replication, and within each line, each value is used scale factor times lo effecl horizontal up-scaling via pixel replication. Once the input line has been used scale factor times (the advance line bit has been set scale faclor limes), the input buffer select bit of the address is toggled (double buffering). The logic for the scale unit is the same for the 8-bit and I -bit case, since the scale unit only generates addresses. Since each of the conlone layers can be a different resolution, they are scaled independently, The bi-level spotl layer at buffer 45 and the dither matrix select layer at buffer 46 also need lo be scaled. The bi-level lag data at buffer 47 is established at the correct resolution and does aot need to he scaled. The scakd-up dither matrix select bit is used by the dither matrix access unit 48 to select a single 8-bil value from the two dither matrices. The 8-bil value is output to the 4 comparators 44, and 49 to 51, which simply compare it to the specific 8-bit coiitone -value. The generation of an actual dither matrix is dependent on the structure of the print head and the general processes by which to generate one will be familiar to those skilled in the art. If the contone value is greater than or equal to the 8-bit dither matrix value a 1 is output. If not, then a 0 is output. These bits are then all ANDed at 52 lo 56 with an inPage bit from the margin unil 57 (whether or not the particular dot is inside the printable area of the page). The final stage in the HCU is the composiling stage. For each of the 6 output layers there is a single dot merger unil, such as unit 58, each wilh 6 inputs. The single outpul bit from each dot merger unit is a combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing purposes), black to be merged into cyan, magenta and yellow (if no black ink is present in the print head), and tag dot data to be placed in a visible plane. A fixalive color plane can also be readily generated. The dot reorg unit (DRU) 59 is responsible for taking the generated dot stream for a given color plane and organizing it into 32-bil quantities so that the outpul is in segment order, and in dot order within segments. Minimal reordering, is required due to the fact that dots for overlapping segments are not generated in segment order. Two control hits are provided to the scale units by the margin unil 57: advance dot and advance line. The advance dot bit ■allo\\s the itate machine to generate multiple instances of the satne dot data (useful for page margins and creating dot data for overlapping segments in the print head) The advance line bit allows the stale machine to conirol when a particular line of dots has been finished, thereby allowing truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-line logic. The comparator unil contains a simple 8-bit "greater-than-or-equal" comparator. It is used to determine whether the 8-bit contone value is greater than or equal to the 8-bit dither matrix value. As such, the comparator unil lakes two 8-bil inputs and produces a single I -bit output. In FIG. 6 is seen more detail of the dot merger unii. It provides a means of mapping the bi-level dithered data, the spoil color, and Ihe lag data to output inks in the actual print head. Each dot merger unil takes 6 I-bit inputs and produces a single bit output that represents the output dot for that color plane. The output bit at 60 is a combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing ptivposes), black to be merged ii^to cyan, magenta and yellow (in the case of no black ink in the print head), and tag dot data to be placed in a visible plane. An output for fixative can readily be generated by simply combining all of the inpul bits. 'Ihe dot merger unit contains a fi-bit CoiorMnsk register 61 that is used as a mask against the 6 inptit bits. Each of the input bits is ANDed with the corresponding ColorMask register bit. and the resultant 6 bits are then ORed together to form the final output bit. The ColorMask registers for each output are set depending on the meaning of the inpul layers and the available inks in the print head. Assuming conlone layer I is cyan, contone layer 2 is magenta, contone layer 3 is yellow, and contone layer 4 is black, bi-level spoil is black, bi-level tag is infra-red: • If the print head does not contain black ink, the ColorMask registers for Cyan, Magenta and Yellow would be: 011001, 011010, and 011100 respectively, thus placing the black ink into each of cyan, magenta, and yellow, • !f all inks require fixative, the CoiorMask for ftxaiive would be; 111111. if infrared does not require fixative, the CoIorMask register for fixative would be 011111. • If black ink is present in the print head, and for testing purposes we want to view the tags, simply set bit5ofltie black color channel's CoIorMask register, Bit5 of the infrared channel's CoIorMask register can be set or cleared as desired during this testing mode. The Spot I color can be set to any base color simply by setting the appropriate bit of the CoIorMask register. For example: * If spoil color is cyan, the cyan CoIorMask register would be 010001 ♦ If spoil color is yellow, the yellow CoIorMask register would be 010100 " If spoil eolor is green, the cyan and yellow CoIorMask registers would be OIOOOl and OIOIOO respectively, to enable spoil onto both cyan and yellow inks * If spot I color is some special ink, such as gold, ii can be enabled into an ink channel simply by setting the CoIorMask register of that channel to 010000. Tags, spotl and potentially contone planes should be appropriately directed. For example, there are only 5 dot merger units but 6 inputs consequently one input is either ignored or merged. For example, if spoil is gold and contone contains a black layer, then black contone should be pushed into C. M and Y by setting the CoIorMask registers for Cyan, Magenta and Yellow to 011001, 011010, and 011100 respectively. A fixative plane can readily be generated by selecting the bits that represent inks requiring the presence of fixative. For example: • If all inks require fixative, the CoIorMask register for fixative would be 111111. * If only black requires fixative, and spoil and contone 4 represent black, the CoIorMask register for fixative would be 011000. " If none of the cyan, magenta, yellow or black inks require fixative, but the infra-red ink requires fixative, the CoIorMask register for fixative would be 100000. In FIG. 7 is seen the doi reorg unit \|DRU) which is responsible for taking the generated dot stream for a given color plane and organizing it into 32-bit quantities so that the output is in segment order, and in dot order within segments. Minimal reordering is required due to the fact that dots for overlapping segments are not generated in segment order. The DRU contains a 32-bil shift register, a regular 32-bit register, and a regular 16-bit register. A 5-bil counter keeps track of the number of bits processed so far. The dot advance signal from the dither matrix access unit (DMAU) is used to inslnicl the DRU as to which bits should be output. In FIG. 7 registerlA) 62 is clocked every cycle. It contains the 32 most recent dots produced by the dot merger unit(DMU). The full 32-bit value is copied to register(B) 63 every 32 cycles by means of a WriteEnable signal produced by the DRU state machine 64 via a simple 5-bil counter Ihe 16 odd bits (bits 1,3, 5, 7 etc.) from register(B) 63 are copied to regisier(C) 65 with ihe same WriteEnable pulse. A 32-bil multiplexor 66 then selects between the following 3 outputs based upon 2 bits from the stale machine: • the full 32 bits from register B • A 32-bil value made up from the 16 even bits of register A (bits 0, 2,4. 6 etc) and ihe 16 even bits of register B. The 16 even bits from register A form bits 0 to 15, while the 16 even bits from register B form bits 16-31. • A 32-bit value made up from the 16 odd bits of register B (bits 1, 3, 5. 7 etc) and the 16 bits of register C. The bits of registerC form bits 0 to 15, while the odd bits from registers form bits 16-31. The stale machine for the DRIJ can be seen in Table 1 It starts in state 0. li changes stale every 32 cycles. During the 32 cycies a single noOvertap bit collects the AND of all the dot ach-ance bits for those 32 cycles (noOverlap ■-dol advance for cycle 0, and noOverlap = noOverlap AND dol advance for cycles I to 31). Table I. State machine for DRU state NoOverlap Output output Valid Comment next slate ) X B J Slanup stale i 1 1 B 1 Regular non-overlap 1 1 3 B 1 A contains first overlap 2 2 X Even A, even B ! A contains second overlap S contains first overlap 3 3 X C. odd B 1 C contains first overlap B contains second overlap 1 The margin unii (MU) 57. iti t-TG. 5. is respotisihle for turning ot^vance t/of and advance/i>ie signals from the dither matrix access unit (DMAU) 48 inio general control signals based on the page margins of the current page. It is also responsible for generating the end of page condition. The MU keeps a counter of dot and line across the page. Both are set to 0 at the beginning of the page. The dot counter is advanced by I each lime the MU receives a dol advance signal from the DMAU. When the MU receives a bne advance signal from the DMAU, Ihe line counser is ii\cTemented and the dot counter is reset to 0. f;ach cycle, the current line and dot values are compared to the margins of the page, and appropriate output ^or Advance, line advance hwAwiihin margin s\gi:\z\s?negi\cn based on these margins. The DMAU contains the only substantial memory requirements for the HCU. In riG. 8 is seen the line loader / format unit (LLFU). It receives dol information from the HCU, loads the dots lor a given print line into appropriate buffer storage (some on chip, and some in external DRAM 34) and formats them into the order required for the print head. A high level block diagram oflhel-LFU in terms of its external interface is shown in FIG. 9. The input 67 to the LLFU is a set of 6 32-bil v^ords and a DataValid bit. all generated by the HCU. 'fhe output 68 is a set of 90 bits representing a maximum of 15 print head segments of 6 colors. Not all the output bits may be valid, depending on Viow many colors are actually ubed in the print head. The physical placement of firing nozzles on the print head referenced above, nozzles in two offset rows, means that odd and even dots of (he same color are for two different lines. The even dots are for line L. and the odd dots are for line L-2. In addition, there is a number of lines between the dots of one color and the dots of another. Since the 6 color planes for the same dot position are calculated at one time by the HCU, there is a need to delay tVie dol data for each of the color planes until the same dot is positioned under the appropriate color nozzle The size of each bufTer line depends on the width of the prim head. Since a single PEC generates dots for up to 15 print head segments, a single odd or even buffer line is therefore 15 sets of 640 dots, for a total of 9600 bits (1200 bytes). For example, the buffers required for color 6 odd dots totals almost 45 KBytes, 'Vhc entire set of requisite buflers might be provided on the PEC chip when manufacturing techniques arc capable. Otherwise, the buffers for colors 2 onward may be stored in external DRAM. This enables the PEC to be valid even though the distance between color planes may change in the future. It is trivial lo keep the even dots for color 1 on PKC, since everything is printed relative to that particular dot line (no additional line buffers are needed). In addition, the 2 hair-lines required for buffering color I odd dots saves substantial DRAM bandwidth. The various line buffers (on chip and in DRAM) need to be pre-loaded with all Os belbre the page is printed so that it has clean edges. The end of the page is generated automatically by the HCU so it will have a clean edge. In FIG \0 is seen a block diagram for Color N OESplit (see Oesplit 70 of FIG. 9), and Ihe block diagram for eachofthetwobuffersEandF,7i,72inFIG. 9 can be found in FlGs. lOaiidll. Buffer EF is a double buffered mechanism for transferrmg data to the prim head ititerfai;s (PHI) 11 iti FIG. 3. Buftets 1-: and F Cheiefore have iden\ical structures. During the processing oCa line of dots, one of the two buffers is written to while Ihe other is being read from. The two buffers are logically swapped upon receipt of the line-sync signal from the PHI, Both buffers E and F are composed of 6 sub-buffers, I sub-buffer per color, as shown in FIG. II, the color I sub-bufl'ernumbered 73. The size of each sub-buffer is 2400 byles. enough to hold 15 segments at 1280 dots per segment. The memory is accessed 32-bits at a time, so there are 600 addresses for each sub-buffer (requiring 10 bits of address). All the even dots are placed before the odd dots in each color's sub-buffer. If there is any unused space (for printing to fewer than 15 segments) it is located at the end ofeach color's sub-buffer. The amount of memory (ic;ua//>i w.serf from each sub-buffer is directly related to the number of segments actually addressed by the PEC, For a 15 segment print head there are 1200 bytes of even dots followed by 1200 bytes of odd dots, with no unused space. The number of sub-bulTers gainfully used is directly related to the number of colors used in the prim head. Themajcimum number of colors supported is 6. The addressing decoding circuitry for each of b\if(i;rs E and F is such thai in a given tycle, a single 32-bit access can be made to all 6 sub-buffers ■ either a read from all 6 or a write lo one of the 6. Only one bit of the 32-bits read from each color buffer is selected, for a total of 6 output bits. The process is shown in FIG. II. 15 bits of address allow the reading ofa particular bit by means of 10-bits of address being used to select 32 bits, and 5-bits of address choose I-bit from those 32, Since all color sub-buffers share this logic, a single 15-bit address gives a total of 6 bits out, one bit per color. Each sub-butTer 73 to 78 has its own WriieEnable line, to allow a single 32-bit value to be written to a particular color buffer in a given cycle. The individual WrileEnables arc generated by ANDing the single WriieEnable input with the decoded form of ColorSelect. The 32-bits of Datain on line 79 are shared, since only one buffer will actually clock the data in. Address generation for reading from buffers E and F is straightforward. Each cycle generates a bit address that is used to fetch 6 bits representing 1 -bit per color for a particular segment. By adding 640 to the current bit address, we advance lo the next segment's equivalent dot, Wi add &40 (tvot 1280) since the odd and even dwls are separated in the buffer. We do this SutnSegments times to retrieve the data representing the even dots, and transfer those bits to the PHI. Whea :\'! In addition, we generate the TiVriieEnable control signal for writing to the 90-bit Transfer register 90 in FIG, 9, Since ihe LLFU starts before ihe PHI, we must transfer the first value before the Advance pulse from the PHI, We must also generaie the next value in readiness for the first Advance pulse. The solution is to transfer the first value lo the Transfer register after NumSegments cycles, and then to stall NumSegmenis cycles later, waiting for the Advance pulse lo start Ihe next NumSegmenis cycle group. Once the first Advance pulse arrives, the LLFU is synchronized lo the PHI, The read process for a single dotline is shown in the following pseudocode: buffer EF. Upon receipt of the second OutputValid signal of the group of two, we write the 32-bits of odd dalaio the same location in buffer AB that we read from previously, and we write the 32-bits of even data to color 1 within buffer EF, The HCU provides 32 bits of data per color plane whenever the OutputValid control flag is set. This occurs every 32 c>cles excepi during cenain startup times. The 32 bits define a contiguous set of 32 dots for a single dot line - 16 even dots (bits 0, 2, 4 etc.), and 16 odd dots (bits 1.3. 5 etc.). While buffer 0E\| (83 in FIG, 10) is used to store a single 32>bii value for color 1, buffers OEj to OE^ are used to store a single 32-bit value for colors 2 to 6 respectively. Just as the data for color 1 is split into 32-bits representing color 1 odd dots and 32-biis representing color I even dots every 64 cycles (once every two OutputValid flags), the remaining color planes are also split into even and odd dots. However, instead of being written directly to buffer EF, the dot data is delayed by a number of lines, and is written out to DRAM via buffer CD (84 in FIG. 9), While the dots for a given tine are written to DRAM, the dots foe a previous line are read from DRAM and written to buffer EF (71,72). This process must be done interleaved with the process writing color 1 to buffer VJr. Every time an OutputValid flag is received from the HCU on lineKS in ¥K. 10, the 32-bits of color N data are written to buffer OEM (83). Every second OutputValid flag, the combined 64-bit value is written to color buffer N (86). This happens in parallel for all color planes 2-6, Color Buffer N (86) contains 40 s^ts of 64-bits (320 bytes} to enable the dots for two complete segments to be stored. This allows a complete segment generation time (20 x 64 = 1280 cycles) for the previous segment's data (both odd and even dots) to be written out to DRAM. Address generation for writing is straightforward. The ColorNWriteEnable signal on line 87 is given every second OutputValid Hag, The address starts at 0, and increments every second OutputValid flag until 39. Instead of advancing to 40, the address is reset to 0, thus providing the double-buffering scheme. This works so long as the reading does not occur during the OutputValid flag, and that the previous segment's data can be written \o DRAM in ibe time il takes to generate a single segment's data. The process is shown in the I'ollowing pseudocode: EndWhile Address generation for reading is trickier, since it is tied to the timing tor DRAM access (both reading and writing), buffer EF access, and therefore color I generation. It is more fully explained below. Address generation for buffers C, P, E, F, and i;olorN are all tied to the timing of DRAM access, and must not itiiccfere with color I processing with regards to buffers Band F The basic principle is that the data for a single segment of color N (either odd or even dots) is transferred from the DRAM lo buffer EF via buffer CD, Once the data has been read from DRAM those dots are replaced based on the values in CokirBufferN. This is done for each of the colors in odd and even dots. After a complete segment's worth of dots has accumulated (20 sets of 64 cycles), then the process begins again. Once the data for all segments in a given prinlline has been transferred from and lo DRAM, the current address for thai color's DRAM buffer is advanced so that it will be the appropriate number of lines until the particular data for the color's line is read back from DRAM, In this respect then, the DRAM acts as a form of FIFO. Consequently color N (either odd or even) is read from DR;\M into buffer D while copying color N (same odd/even sense) to buffer C, The copying of data to buffer C takes 20 or 21 cycles depending on whether the OulputVaiid flag occurs during the 20 transfers. Once both tasks have finished (typically the DRAM access will be the slower task), the second part of the process begins. The data in buffer C is written to DRAM (the same locations as were just read) and the data in buffer D is copied lo buffer EF (again, no color N data is transferred to buffer EF while the OulputVaiid flag is set since color I data is being transferred). When both tasks have finished the same process occurs for the other sense of color N (either odd or even), and then for each of the remaining colors. The entire double process happens 10 times. The addresses for each of the current lines in DRAM are then updated for the next line's processing to begin. In terms of bandwidth, the DRAM access for dot data butlers consumes the great majority of all DRAM access from PEC, For each print line we read an entire dot line for colors 2-6, and write an entire dot line for colors 2-6. For the maximum of 15 segments this equates to 2 v 5 x 15 x 1280 bits = 192,000 bits (24,000 bytes) per print line. For the fastest printing system (30,000 lines per second) this equates to 687 MB/sec. For 1 page per second printing the bandwidth required is 312 MB/sec. Since the bandwidth is so high, the addresses of the various half-lines for each color in DRAM should be Optimized for the memory type being used. In an RDRAM memory system for example, the very first half-line buffer is aligned for each color to a I KByte boundary to maximize page-hits on DRAM access. As the various segments are processed it is necessary to ensure that if the start of the next segment was going to be aligned at byte 960 within the I KByte page, then the 640-bit access would span 2 pages. Therefore the variable DiUMMiMFa/is used lo check for this case, and if it occurs, the address is rounded up for the next half-line buffer to be page-aligned. Consequently the only waste is 64 bytes per 13 segments, but have the advantage of the 64()-bil access completely within a single page. The address generation process can he considered as NumSagmenls worth of 10 sets of: 20 x 32-bil reads followed by 20 x 32-bit writes, and it can be seen in the following pseudocode: EFStartAdr = 0 Do NumScgments times: For CurrColor = 0 to MaxHalfColors DRAMSlartAddress - ColorCurrAdr[CurrColor] While reading 640 bits from DRAMSlartAddress into D{>= 20 cycles) ColorNAdr = 0 While (ColorNAdr 1=20) If (NOT HCl) OulputVaiid) (colors 2-6 in odd and even), and so MaxHaifColors should be set to 9. The LLFU rtquiies 2.\'umSeginen!s cycks io prepare ihe first 180 bits ofdala for the PHI. Consequently the print head should be started and the first LineSync pulse must occur ihis period of lime after the LLFU has started. This allows the initial Transfer value to be valid and the next 90-bil value lo be ready lo be loaded into the Transfer register. The prim head interlace (PHI) is the means by which ihe processor loads the print head with the dots lobe printed, and comrols llie acWa! dot pvinling process, ll takes input from the LLFU and outputs data to the print head itself. The PHI will becapableof dealing with a variety of print head lengths and formats. Theinlemal struelure of the PHI should allow for a maximum of 6 colors, 8 segments per transfer, and a maximum of 2 segment groups. This should be siiRleieni for a 15 segment (8.5 inch] printer capable of priming A4/Letter at full bleed. Throughout the specification the aim has been to describe the preferred embodiments of the invention without limiting the invention lo any one embodiment or specific collection of features. Persons skilled in the art may realize variations from the specific embodiments that will nonetheless fall within the scope of the invemifm WE CLAIM: 1. A print controller to drive an ink drop print head comprising: an interface at which to receive compressed page data; decoders to decode respective types of image planes in the received compressed page data; and a half-toning and composing unit to composite image plane data; the half-toning and composing unit comprising: a dot merger unit taking bits from the respective planes as mputs; and a color mask register holding masking bits in number equal to the number of image planes; respective input bits to the dot merger unit being ANDed with respective color mask register bits and the resultant bits ORed together to form an output bit in a channel for which there is an ink at the print head. 2. The prmt controller as claimed in claim 1 wherein the respective planes to the dot merger unit comprises three contone color planes and a high resolution plane and the color mask register is loaded with bits that are selected to place the high resolution plane into anyone of the respective color channels. 3. The print controller as claimed in claim 2 wherein a fixative channel is generated from anyone or more of the respective planes and selected by what bits are loaded to the color mask register. 4. The print controller as claimed in claim 1 wherein the color mask register is loaded with bits that are selected to split a K plane into C, M, and Y channels for output to a print head without K. 5. The print controller as claimed in claim 1 wherein the half-toning and composing unit comprises a tag encoder generating an infrared tag data plane and the color mask register maps its dots into an infrared channel at the print head. 6. The print controller to drive an ink drop print head comprising: a contone image decoder to decode any compressed continuous tone image planes in the received compressed page data; a high resolution image decoder to decode any compressed high resolution image plane; and a half-toning and composing unit comprising a dot merger unit controlled by a color mask to map image planes into channels corresponding to what inks are supplied in the print head that is interfaced by the print controller. 7. The print controller as claimed in claim 6, wherein the half-toning and composing unit comprises: a margin unit to apply margin data to the respective image planes during the composite process. 8. The print controller chip to interface with an ink drop print head comprising: an interface at which to receive compressed page data; a contone image decoder to decode any continuous tone image planes in the received compressed page data; a high resolution decoder to decode any high resolution image plane in the received compressed page data; a half-toning and composing unit comprising to dither any continuous tone image planes and composite any high resolution image plane data with any output plane includmg a dot merger unit controlled by a color mask to map image planes into channels corresponding to what inks are supplied in the print head that is interfaced by the print controller; and a print head driver to output the composite to a print head. 9. An ink drop printer driven by a print controller comprising: an interface at which to receive compressed page data; a contone image decoder to decode any continuous tone image planes m the received compressed page data; a high resolution image decoder to decode any high resolution image planes in the received compressed page data; a half-toning and composmg unit to dither any contmuous tone image planes and composite high resolution image plane data with any output plane comprising a dot merger unit controlled by a color mask to map image planes into channels corresponding to what inks are supplied in the print head that is interfaced by the print controller; a print head driver to output the composite to a print head; and a print head. 10. A method of operating an ink drop printer comprising: receiving compressed page data decoding any continuous tone image planes in the received compressed page data to generate output planes; decoding any high resolution image plane in the received compressed page data to generate an output plane; dithering any continuous tone image planes, compositing any high resolution image plane data with any output plane; and forwarding composited data to a print head with image planes mapped to what inks are available at the print head.

Full Text

PRINT ENGINE/CONTROLLER WITH COLOR MASK
FIELD OF THE INVENTION
The invenlLon relates to a print engine/coniroller (PEC) able to receive print data and generate and output in a formal suited to what inks are available at the print head.
BACKGROUND OF THE INVENTION
Arangeofprinleriypes have evolved wherein an image is constructed from ink selectively applied to a page in dot formal. !n US patent number 6045710 titled "Self-aligned construction and manufacturing process for monolithic print heads' lo the inventor Kia Silverbrook there is sei out an assessment of the prior art to drop on demand printers along with its panicular manufacturing process.

A mieroelectomechanical drop on demand prim head hereafter referred to as a Memjet print head has been . described in co-pending United States Paient Applications filed simultaneously to the present application and hereby incorporated by cross reference:

A distribution system of the above kind will output page data in a particular format, providing image data in a range of image planes. These image planes may be received at printers with print heads not fitted with a corresponding number of ink channels. Some clients to the system might desire to move image planes from one ink channel lo another. A print engine/controller ideally addresses these issues.
More speed and flexibility in selection of output channels at the print head depends on development of both print head and its engine/controller. The print engine/controller architecture ideally needs to be designed to push data in volume to selected ink chanriels in the print head at high speed.
SUMMARY OF THE INVENTION
In one form ihe invention resides in a print engine/controller to drive an ink drop print head comprising:
an interface at ivhich lo receive compressed page dala;
decoders lo decode respective types of image planes in Ihe received compressed page data; and a half-loner/compositor to composite image plane data; the half-toner/compositor including;
a dot merger unit taking bits from the respective planes as inputs; and a color mask register holding masking bits in number equal to the number of image planes;
tespective input bits, to the dot merger unit being ANDed with respective color mask register bits and the resullant bils Ored together to form an output bit in a channel for which there is an ink at the print head.
The dot merger unit provides a means by which to map data bits to the respective inks at a print head. A color mask register within the dot merger unit holds a pattern of bits that effect the mapping of image bils input to ihe dot merger unit. Image data might be delivered to a client with image planes in all of CMY and K together with data lo go into tags on an output page in infrared ink. Speed might be such that a fixative needs to be used. The ideal print head then works with six ink channels. Some printers may not provide for all of CMY and K and K may need to be expressed through use of the CMY channels. It might be desired in some circumstances to put a high-resolution plane otherwise destined for the K channel into one of the color channels. These outcomes are met through what bits are loaded into the color mask register.
BRIEF DESCRIPTION OF THE DRAWINGS
FiG. 1 is a diagram illuslraiing data How and .the functions performed by the print engine controller.
FIG. 2 shows the print engine controller in the context of the overall printer system architecture.
FiG. 3 illustrates the print engine controller architecture.
FIG. 4 illustrates the external interfaces to the halfloner/compositor unit (HCU) of FIG. 3.
FIG. 5 is a diagram showing internal circuitry to the HCU of FIG. 4.
FIG. 6 shows a block diagram illustrating the process within the dot merger unit of FIG. 5.
FIG. 7 shows a diagram illuslraiing the process within the dot reorganization unit of FIG. 5.
FIG. 8 shows adiagramillusiratinglheprocess within the line loader/format unit (LLFU) of FIG. 5.
FIG. 9 is a diagram showing internal circuitrj'to generate color data in the LLFU of FIG. 8.
FIGs. !0 and 11 illustrate components of the LLFU seen in FIG. 9,
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
A typically 12 mch print head width is controlled by one or more I'BCs. as described below, to allow full-bleed printing of both A4 and Letter pages. Six channels of colored ink are the expected maximum in the present printing environment, these being;

• CMY. for regular color printing.
• K. for black text and other black printing.
• IR (infrared), for tag-enabled applications,
• F (fixative), to enable printing at high speed.
Because the printer is to be capable of fast printing, a fixative may be required to enable the ink to dry before the next page has completed printing at higher speeds. Otherwise the pages might bleed on each other. In lower speed printing environments the fixative will not be required.
A PEC might be built in a single chip ii> interface with a print head It will contain four basic levels of functionality: receiving compressed pages via a serial interface such as lEEF. 1394
• a prim engine for producing a page from a compressed form. The print engine functionality includes expanding the page image, dithering the contone layer, compositing the black layer over the contone layer, optionally adding infrared tags, and sending the resultant image to the prim head.
• a print controller for controlling the print head and stepper motors.
• iwo standard low-speed serial ports far communication with QA chips. Note that there ought to be two ports and not a single port to ensure strong security during the authentication procedure.
In Figure 1 is seen the flow of data to send a document from computer syswm to printed page. A document is received at 11 and loaded to memory buffer 12 wherein page layouts may be effected and any required objects might be added. Pages from memory 12 are rasierized at 13 and compressed at 14 prior to transmission to the print engine controller 10, Pages are received as compressed page images within the prim engine controller 10 into a memory buffer 15, from which they are fed to a page expander 16 wherein page images are retrieved. Any requisite dither might be applied to any contone layer at 17, Any black bi-level layer might be composited over the conlone layer at 18 together with any infrared tags at \9. The composited page data is printed at 20 to produce page 21,
The print engine/controller takes the compressed page image and starts the page expansion and printing in pipeline fashion. Page expansion and printing is preferably pipelined because it is impractical to store a sizable bi-level CMYK+IR page image in memory.
The first stage of the pipeline expands a JPEG-compressed conlone CMYK layer (see below), expands a Group 4 Fax-compressed bi-level dither matrix selection map (see below), and expands a Group 4 Fax-compressed high resolution black layer (sec below), all in parallel. In parallel with this, the tag encoder encodes bi-lcvel IR tags with data from the compressed page image. The second stage dithers the contone CMYK layer using a ililher matrix selected by the dither matrix select map, composites the bi-level black layer over the resulting bi-lcvel K layer and adds the IR layer to the page, A fixative layer is also generated at each dot position wherever there is a need in any of C, M, Y, K, or IR channels. The last stage prints the bi-level CMYK+IR data through the print head via a print head interface (see below).
In FIG. 2 is seen how the print engine/controller 10 fits within the overall printer system architecture. The various components of the printer system might include
■ a Prinl Engine'ConiroUer (PEC) A PEC chip 10. or chips, is responsible for receiving the compressed page images for storage in a memory buffer 24, performing the page expansion, black layer compositing and sending the dot data to the print head 23. It may also communicate with QA chips 25,26 and provides a means of retrieving print head characteristics to ensure optimum printing The PEC is the subject of this specification.
■ a memory buffer. The memory buffer 24 is for storing the compressed page image and for scratch use during the printing of a given page. The construction and working of memory buffers is known to those skilled in (he art and a rangeof standard chips and techniques for their use might be utilized in use of the PEC of the invention.

a masier QA chip. The master chip 25 is ideally matched to replaceable ink cartridge QA chips 26. The construction and working of QA units is known to those skilled in the art and a range of known QA processes might be utilized in use of the PEC of the invention. For example, a QA chip is described in co-pending United Slates Patent Applications;

USSN Our Docket IN umber Our Title
TBA AUTHOl Validation Protocol and System
09/112,763 AUTH02 Circuit for Protecting Chips Against IDD Fluctuation Attacks
09/112,737 AUTH04 Method for Protecting On-Chip Memory (Flash and RAM)
09/112,761 AUTH05 Method for Making a Chip Tamper-Resistant
09/113,223 AUrH06 A system for authenticating physical objects
TBA AUTH07 Validation Protocol and System
TBA AUTH08 Validation Protocol and System
09/505,003 AUTI109 Consumable Authentication Protocol and System
09/517,608 AUTHIO Consumable Authentication Protocol and System
09/505,147 AUTHll Consumable Authentication Protocol and System
09/505,952 AUTH12 Unauthorized Modification of Values Stored in Flash Memory
TBA AUTH13 A System for the Manipulation of Secure Data
09/516.874 AUTH14 An Authentication Chip with Protection from Power Supply Attacks
TBA AUTHI5 Shielding Manipulations of Secret Data
QA chip communication may be best included within the overall functionality of the PEC chip since it has a role in the expansion of the image as vvell as running the physical print head. By locating QA chip communication there it can be ensured ihal there is enough ink to print the page. Preferably the QA embedded in the print head assembly is implemented using an authentication chip. Since it is a master QA chip, it only contains authentication keys, and does not contain user-data. Howevet, it must match the itik catltidge's QA chip, The QAchip in the ink cartridge contains information required for maintaining the best possible print quality', and is implemented using an authentication chip.
Preferably a 64 MBit (8 MByte) memory buffer is used to store the compressed page image. While one page is being written to the buffer another is being read (double buflering). In addition, the PEC uses the memory to buffer the calculated dot information during the printing of a page. During the printing of page N, the buffer is used for:
• Reading compressed page N
• Reading and writing the bi-level dot information for page ;V
• Writing compressed page ,V+ /
Preferably a PEC chip will incorporate a simple micro-controller CPU core 35 to perform the following functions:
perform QAchip authentication protocols via serial interface 36 between print pages
run Ihe stepper motor via a parallel interface 91 during a print (the stepper motor requires a 5 KHz process)
synchronize Ihe various portions of the PEC chip during a print
provide a means of interfacing with external data requests (programming registers etc.)
provide a means of interfacing with print head segment low-speed data requests (such as reading the characterization
vectors and writing pulse profiles)

■ provideameansof writing the portrait and landscape tag structures to external DRAM
Since all of the image processing is performed by dedicated hardware, the CPU does not have to process pixels. As a result, the CPU can be extremely simple. A wide variety ofknown CPU cores are suitable: it can be any processor core with sufficient processing power to perform the required calculations and control funcfions fast enough. An example ofa suitable core is a Philips 8051 micro-controller running at about 1 MHz, Associated with the CPU core 35 may be a program ROM and a small program scratch RAM. The CPU communicates with the other units within the PEC chip via memory-mapped I/O. Particular address ranges may map to particular units, and within each range, to particular registers within that particular unit. This includes the serial 36 and parallel 91 interfaces, A small program flash ROM may be incorporated into the PLC chip. Its size depends on the CPU chosen, but should not be more than 8KB. Likewise, a small scratch RAM area can be incorporated into the PEC chip. Since the program code does not have to manipulate images, there is no need for a large scratch area. The R.AM size depends on the CPU chosen (e.g. stack mechanisms, subroutine calling convenfions. register sizes etc), but should not be more than about 2 KB,
A PEC chip using the above referenced segment based page wide print head can reproduce black at a full dot resolution (typically 1600 dpi), but reproduces contone color at a somewhat lower resolution using halftoning. The page description is therefore divided into a black bi-level layer and a contone layer. The black bi-level layer is defined to composite over the contone layer. The black bi-level layer consists ofa bitmap containing a 1-bit opacity for each pixel, fhis black layer malle has a resolution that is an integer factor of the printer's dot resolution. The highest supported resolufion is 1600 dpi, i.e. the printer's full dot resolution. The contone layer consists ofa bitmap containing a 32-bit CMYK color for each pixel, where K is optional. This contone image has a resolution thai is an integer factor of the primer's dot resolution. The highest supported resolution is320ppi over 12 inches for a single PEC, i,e. one-fifth the printer's dot resolution. For higher contone resolutions multiple PECs are tequived, with each PEC producing an strip of the output page. The contone resolution is also typically an integer factor of the black bi-level resolufion, to simplify calculations in the RlPs, This is not a requirement, however. The black bi-level layer and the contone layer are both in compressed form for efficient storage in the printer's internal memory.
In FIG, 3 is seen the print engine architecture. The print engine's page expansion and printing pipeline consists ofa high speed serial interface 27 (such as a standard IEEE 1394 interface), a standard JPEG decoder 28, a standard Group 4 Fax decoder. a custom halttoncr/compositor unit 29, a custom tag encoder 30, a line loader/fotTnatter unit 31, and a custom interface 32 to the print head 33. The decoders 28,88 and encoder 30 are buffered to the hal ft oner/compositor 29. The tag encoder 30 establishes an infrared tag or tags lo a page according to protocols dependent on what uses might be made of the page and the actual content of a tag is not the subject of the present invenfion.
lite print engine works in a double buffered way. One page is loaded into DRAM 34 via DRAM interface 89 and data bus 90 from the high speed serial interface 27 while the previously loaded page is read from DRAM 34 and passed through the print engine pipeline. Once the page has finished printing, then the page just loaded becomes the page being printed, and a new page is loaded via the high-speed serial interface 27. At the first Stage the pipeline expands any JPEG-comptessed contone (CMYK) la^er, and expands any of two Group 4 Fax.-compressed bi-level data streams. The two streams are the black layer (although the PEC is actually color agnostic and this bi-level layer can be directed to any of the output inks), and a matte for selecting between dither matrices for contone dithering (see below). At the second stage, in parallel with the first, is encoded any tags for later rendering in either IR or black ink. Finally the third stage dithers the contone layer, and composites position tags and the bi-level spatl layer over the resuUing bi-level dithered layer. The data stream is ideally adjusted to create smooth transifions across overlapping segments in the print head and ideally it is adjusted to compensate for dead nozzles in the print head. Up to 6 channels of bi-level data are produced from

this stage. Note thai not all 6 channels ma>' be present on the print head. For example, the print head may be CMY only, with K pushed into the CMY channels and IR ignored. Alternatively, the position tags may be printed in K if IR ink is not available (or for testing purposes). The resultant bi-level CMYK-IR dot-data is bufl'ered and formatted for printing on the print head 33 via a set of line buffers (see below). The majority of these line buffers might be ideally stored on the of!-ehipDRAM 34. The final stage prints the 6 channels of bi-level dot data via the print head interface 32.
Compression is used in a printing system that employs the PKC. This is to reduce bandwidth requirements between a host and PEC, as well as to reduce memory requirements for page storage. At 267 ppi, a Letter page of contone CMYK data has a size of 25MB, Using lossy contone compression algorithms such as JPEG (see below), con lone images compress with a ratio up to 10:1 without noticeable loss of quality, giving a compressed page size of 2.5MB. At 800 dpi, a Letter page of bi-level data has a size of 7MB. Coherent data such as text compresses very well. Using lossless bi-level compression algorithms such as Group 4 Facsimile (sec below), ten-point text compresses with a ratio of about 10:1, giving a compressed page size of 0.8MB. Once dithered, a page of CMYK contone image data eonsistsof 114MB of bi-level data. The two-layer compressed page image format described below exploits the relative sirengthsof lossy JPEG contone image compression and lossless bi-level text compression. The format is compact enough to be storage-efficient, and simple enough to allow straightforward real-time expansion during printing. Since text and images normally don't overlap, the normal worst-case page image size is 2,5MB (i,e, image only), while the nofitial best-case page image size is 0,8MB (i.e. text only). The absolute worst-case page image si^e is 3.3MB (i.e. text over image), Assuming a quarter of an average page contains images, the average page image size is 1.2MB.
A Group 3 Facsimile compression algorithm (see ANSI/EIA 538-1988, Facsimile Coding Schemes and Coding Coniro! hmctions for Grmp 4 Facsimils Equipmem, August 1988) fin be used lo losslessly comprisses bi-level data for transmission over slow and noisy telephone lines. The bi-leve! data represents scanned black text and graphics on awhile background, and the algorithm is tuned for this class of images (it is explicitly not luned, for example, for halfioned bi-k\cl images). The yD Group 3 algorithm runlength-cncodes each scanlineand then Huffman-encodes the resulting runlengths- Runlengths in the range 0 to 63 are coded with lerminaiing codes. Runlengths in the range 64 to 2623 are coded with m«fc-wp codes, each representing a muhiple of 64, followed by a terminating code. Runlengths exceeding 2623 are coded with multiple make-up codes followed by a terminating code. The Huffman tables are fixed, but are separately tuned for black and white runs (except for make-up codes above 1728, which arc common). When possible, the 2D Group 3 algorithm encodes a scanline as a set of short edge deltas (0, ± I, ±2, ±3) with reference to the previous scanline. The delta symbols are entropy-en coded (so that the zero delta symbol is only one bit long etc.) Edges within a 2D-encoded line that can't be delta-encoded are runlength-encoded, and are identified by a prefix. ID- and 2D-encoded lines are marked differently. ID-encoded lines are generated at regular intervals, whether actually required or not, to ensure that the decoder can recover from line noise with minimal image degradation. 3D Group 3 achieves compression ratios of up lo6:l (see Urban, S J., "Review' of standards for electronic imaging for facsimile systems", Journal of Electronic Imaging. Vol,l(l), Januao' 1992. pp,5-2l).
A Group i Facsimile algorithm (see ANSI/EIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) losslessly compresses bi-level data for transmission over error-free communications lines (i.e. the lines are truly error-free, or error-correction is done at a lower protocol level). The Group 4 algorithm is based on the 2D Group 3 algotithsti, with the essential modificatioti that since transmission is assumed to be error-free. ID-eneoded lines are no longer generated at regular intervals as an aid to error-recovery. Group 4 achieves compression ratios ranging from 20:1 to 60:1 for the CCITT set of test images. The design goals and

performance of the Group 4 compression algorithm qualify it as a compression algorithm for the bi-leve! layers. However, its Huffman tables are tuned to a lower scanning resolution (100-400 dpi], and it encodes runlengths exceeding 2623 awkwardly. At 800 dpi, our maximum runlength is currently 6400. Although a Group 4 decoder core would be available for use in PEC, it might not handle runlengths exceeding those normally encountered in 400 dpi facsimile applications, and so would require modification. The (typically 1600 dpi) black layer is losslessly compressed using G4Fax at a typical compression ratio exceeding 10:1. A (typically 320dpi) dither matrix select layer, which matches the conlone color layer, is losslessly compressed using G4Fax at a typical compression ratio exceeding 50:1.
The Group 4 Fax (G4 Fax) decoder is responsible for decompressing bi-level data. Bi-level data is limited to a single spot color (typically black for text and line graphics), and a dilhcr matrix select bit-map for use in subsequent dithering of the contone data (decompressed by the JPKO decoder). The input to the G4 Fax decoder is 2 planes of bi-level data, read from the external DRAM. The output of the G4 Fax decoder is 2 planes of decompressed bi-level data. The decompressed bi-level data is seail to the Halfionei/CompositoT Unit (HCU) for the next stage in the printing pipeline. Two bi-level buffers provides the means for transferring the bi-level data between the 04 Fax decoder and the HCU, Each decompressed bi-level layer is output to two line buffers. Each buffer is capable of holding a full 12 inch line of dots at the expected maximum lesolulion. Having two line butYcrs allows one line to be read by the HCU while the other line is being written to by the G4 Fax decoder. This is important because a single bi-level line is typically less than 1600 dpi. and must therefore be expanded in both the dot and line dimensions. If the buffering were less than a full line, the G4 Fax decoder would have to decode the same line multiple times, - once for each output 60Qdpi dotline.
Spot color I is designed to allow high resolution dot data for a single color plane of the output image. While the contone layers provide adequate resolution for images, spot color I is targeted at applications such as text and line graphics (topically black). When used as text and line graphics, the typical compression ratio exceeds 10:1, Spot color I allows variable resolution up to 1600dpi for maximum print quality. Each of the two line buffers is therefore total 2400 bytes (12 inches X 1600 dpi = 19.200 bits).
The resolution of the dither matrix select map should ideally match the contone resolution. Consequently each of the two line buffers is therefore 480 bytes (3840 bits), capable of storing 12 inches at 320 dpi. When the map matches the contone resolution, the typical compression ratio exceeds 50:1.
[n order to provide support for:
• 800 dpi spot color I layer (typically black)
• 320 dpi dither matrix select layer
the decompression bandwidth requirements are 9,05 MB/sec for 1 page per second performance (regardless of whether the page width is 12 inches or 8,5 inches), and 20 MB/sec and 14,2 MB/sec for 12 inch and 8,5 inch page widths respectively during maximum printer speed performance (30,000 lines per second). Given that the decompressed data is output to a line bufier, the G4 Fax decoder can readily decompress a line from each of the outputs one at a time. The G4 Fax decoder is fed directly from the main memon,' via the DRAM interface. The amount of compression determines the bandwidth requirements to the external DRAM, Since G4 Fax is lossless, the complexity of the image impacts on the amount of data and hence the bandwidth, typically an 800 dpi black text/graphics layer exceeds 10:1 compression, so the bandwidth required to print I page per second is 0,78 MB/sec. Similarly, a typical 320 dpi dither select matrix compresses at more than 50:1, resulting in a 0.025 MB/sec bandwidth. The fastest printing speed configuration of 320 dpi for dither select matrix and 800 dpi for spot color 1 requires bandwidth of 1,72 MB/sec and 0.056 MB/sec respectively, A total bandwidth of 2 MB/sec should therefore be more than enough for the DRAM bandwidth. The G4 Fax decoding functionality is implemented by means of a G4 Fax Decoder core, A wide variety of

G4Fax Decoder eorcs are suitable: it can be any core with sufficient processing power to perform the required calculations and control functions fast enough. Il must be capable of handling runlengths exceeding those normally encountered in 400 dpi facsimile applicavions. and so may tetjuire modification.
A JPEG compression algorithm (see ISO/IEC 19018-1:1994, Information technology - Digital compression and coding of continuous-lone still images: Requtremenis and guidelines, 1994) lossily compresses a contone image at a specified quality level. It introduces imperceptible image degradation at compression ratios below 5:1, and negligible image degradation at compression ratios below 10 1 (see Wallace, G.K.. "The JPEG Still Picture Compression Standard", Communications ofthe ACM. Vol,34, No.4, April 1991, pp.30-44). JPEG typically first transforms the image into a color space that separates luminance and chrominance into separate color channels. This allows the chrominance channels lo be subsampled without appreciable loss because of the human visual system's relatively greater sensitivity to luminance than chrominance. Alter this first step, each color channel is compressed separately. The image is divided into 8>i8 pixel blocks. Each block is then transformed into the frequency domain via a discrete cosine transform (DCf). This transformation has the effect of concentrating image energy in relatively lower-frequency coefficients, which allows higher-frequency coefticients to be more crudely quantized. This quantization is the principal source of compression in JPEG, further compression is achieved by ordering coefficients by frequency to maximize the likelihood of adjacent zero coefficients, and then run length-encoding runs of zeroes. Kinally, the runlengths and non-zero frequency coefficients are entropy coded. Decompression is the inverse process of compression.
The CMYK (or CMY) contone layer is compressed to a planar color JPEG bytestream. If luniinance/chromi nance separation is deemed necessary, either for the purposes of table sharing or for chrominance subsampling, then CMYK is converted to YCrCb and Cr and Cb are duly subsampled. The JPEG bytestream is compleie and self-contained. It contains all data required for decompression, including quantization and Huffman tables. The JPEG decoder is responsible for performing the on-the-lly decompression of the contone data layer. The input to the JPEG decoder is up to 4 planes of contone data. This will typically be 3 planes, representing a CMY contone image, or 4 planes representing a CMYK contone image. Each color plane can be in a different resolution, although typically all color planes will be the same resolution. The contone layers are read from the external DRAM. The output ofthe JPEG decoder is the decompressed contone data, separated into planes. The decompressed contone image is sent to the halftoner/compositor unit (HCU| 29 for the next stage in the printing pipeline. The 4-plane contone buffer provides the means for transferring the conlone data between the iPEG decoder and the HCU 29.
Each color plane ofthe decompressed contone data is output to a set of two line buffers (see below), Kach line buffer is 3840 bytes, and is therefore capable of holding 12 inches of a single color plane's pixels at 320 ppi. The line buffering allows one line buffer to be read by the HCU while the other line buffer is being written lo by the JPEG decoder. This is important because a single contone line is typically less than 1600 ppi, and must therefore be expanded in both the dot and line dimensions. If the buffering were less than a full line, the JPEG decoder would have to decode the same line multiple limes - once for each output 600dpi dotline. Although a variety of resolutions is supported, there is a tradeoff between the resolution and available bandwidth. As resolution and number of colors increase, bandwidth requirements also increase. In addition, the numberof segments being targeted by the PEC chip also affects the bandwidth and possible resolutions, Note that since the contone image is pyocessed in a planar format, each color plane can be stored at a different resolution (for example CMY may be a higher resolution than the K plane). The highest supported contone resolution is 1600ppi (matching the printer's full dot resolution). However there is only enough output line buffer memory to hold enough contone pixels for a 320ppi line of length 12 inches. If the full 12 inchesof output was required at higher conlone resolution, multiple PEC chips would be required, although it should be noted that the final output on

the primer will still only be bi-level. With support for 4 colors ai 320ppi. the decompression output bandwidth requirements are 40 MB/sec for I page per second performance (regardless of whether tlie page width is 12 inches or 8-5 inches), and 88 MB/sec and 64 MB/SEC for U inch anJ 8.5 inch page widths respectively during maximum printer speed performance (30,000 lines per second).
The JPEG decoder is fed directly from the main memory via the DRAM interface. The amount of compression determines Ihe bandwidth requirements to the eyernal DRAM, As the level of compression increases, the bandwidth decreases, but the quality of the final output image can also decrease. The DRAM bandwidth for a single color plane can be readily calculated by applying Ihe compression factor to Ihe output bandwidth. For example, a single color plane at 320 ppi with a compression factor of 10:1 requires 1 MB/sec access to DRAM to produce a single page per second.
The JPEG functionality is implemented by means of a JPEG core. A wide variety of JPEG cores are suitable: it can be any JPEG core with sufficient processing power to perform the required calculations and control functions fast enough. For example, the BTG X-Malch core has decompression speeds up to UO MBytes/sec. which allows decompression of 4 color planes at conlone resolutions up to 400ppi for the maximum printer speed (30,000 lines ai 1600dpi per second), and SOOppi for I page/sec printer speed. Note that the core needs to only support decompression. reducing Ihe requirements thai are imposed by more generalized JPEG compression/decompression cores. The size of the core is expected to be no more than 100,000 gates. Given that the decompressed data is output to a line buffer, the JPEG decoder can readily decompress an entire line for each of the color planes one at a lime, thus saving on context switching during a line and simplifying the control of the JPEG decoder, 4 contexts must be kepi (I context for each color plane), and includes current address in the exiernal DRAM as well as appropriate JPEG decoding parameters
In EiG. 4 Ihe halftoner/compositor unit (HCU) 29 combines the functions of halftoning the contone (typically CMYK) layer to a bi-level version of the same, and compositing ihe spoil bi-level layer over the appropriate halftoned conlone layer(s). If there is no K ink in Ihe primer, ihe HCU 29 is able to map K to CMY dots as appropriate, ll also selects between two dither matrices on a pixel by pixel basis, based on the corresponding value in the dither matrix selecl map. The input to the HCU 29 is an expanded conlone layer (from the JPEG decoder unit) through buffer 37, an expanded bi-level spotl layer through buffer 38, an expanded dithcr-malrix-selcci bitmap at typically the same resolution as the conlone layer through buffer 39, and tag data at full dot resolution through buffer 40, The HCU 29 uses up lo iwo dither matrices, read from the external DRAM 34. The output from the HCU 29 to the line loader/format unit (LLFU) at 41 is a se\ of pointer re^olmion bi-level image lines in up to 6 color planes. Typically, the contoue layer is CMYK or CMY. and the bi-level spotl layer is K.
In FIG. 5 is seen the HCU in greater detail Once started, the HCU proceeds until it detects an end-of-page condition, or until it is explicitly slopped via its control register. The first task of the HCU is lo scale, in the respective scale units such as the scale unit 43, all data, received in the buffer planes such as 42, to printer resolution both horizoniatly and vertically.
The scale unit provides a means of scaling contone or bi-level data to printer resolution boih horizontally and vertically. Scaling is achieved by replicating a data value an integer number of limes in both dimensions. Processes by which to scale data will be familiar to those skilled in the art.
Two control bits are provided to the scale unit 43 by the margin unit 57: advance dot and advance line. The advance doi bit allows the stale machine to generate multiple instances of the same dot data (useful for page margins and creating dot data for overlapping segments in the print head). Ihe advance line bit allows the slate machine lo control when a particular line of dots has been finished, thereby allovving truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-line logic, fhe input to ihe scale unil is a full line buffer. The line is

used scale faclor times to effect vertical up-scaling via line replication, and within each line, each value is used scale factor times lo effecl horizontal up-scaling via pixel replication. Once the input line has been used scale factor times (the advance line bit has been set scale faclor limes), the input buffer select bit of the address is toggled (double buffering). The logic for the scale unit is the same for the 8-bit and I -bit case, since the scale unit only generates addresses.
Since each of the conlone layers can be a different resolution, they are scaled independently, The bi-level spotl layer at buffer 45 and the dither matrix select layer at buffer 46 also need lo be scaled. The bi-level lag data at buffer 47 is established at the correct resolution and does aot need to he scaled. The scakd-up dither matrix select bit is used by the dither matrix access unit 48 to select a single 8-bil value from the two dither matrices. The 8-bil value is output to the 4 comparators 44, and 49 to 51, which simply compare it to the specific 8-bit coiitone -value. The generation of an actual dither matrix is dependent on the structure of the print head and the general processes by which to generate one will be familiar to those skilled in the art. If the contone value is greater than or equal to the 8-bit dither matrix value a 1 is output. If not, then a 0 is output. These bits are then all ANDed at 52 lo 56 with an inPage bit from the margin unil 57 (whether or not the particular dot is inside the printable area of the page). The final stage in the HCU is the composiling stage. For each of the 6 output layers there is a single dot merger unil, such as unit 58, each wilh 6 inputs. The single outpul bit from each dot merger unit is a combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing purposes), black to be merged into cyan, magenta and yellow (if no black ink is present in the print head), and tag dot data to be placed in a visible plane. A fixalive color plane can also be readily generated. The dot reorg unit (DRU) 59 is responsible for taking the generated dot stream for a given color plane and organizing it into 32-bil quantities so that the outpul is in segment order, and in dot order within segments. Minimal reordering, is required due to the fact that dots for overlapping segments are not generated in segment order.
Two control hits are provided to the scale units by the margin unil 57: advance dot and advance line. The advance dot bit ■allo\\s the itate machine to generate multiple instances of the satne dot data (useful for page margins and creating dot data for overlapping segments in the print head) The advance line bit allows the stale machine to conirol when a particular line of dots has been finished, thereby allowing truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-line logic.
The comparator unil contains a simple 8-bit "greater-than-or-equal" comparator. It is used to determine whether the 8-bit contone value is greater than or equal to the 8-bit dither matrix value. As such, the comparator unil lakes two 8-bil inputs and produces a single I -bit output.
In FIG. 6 is seen more detail of the dot merger unii. It provides a means of mapping the bi-level dithered data, the spoil color, and Ihe lag data to output inks in the actual print head. Each dot merger unil takes 6 I-bit inputs and produces a single bit output that represents the output dot for that color plane. The output bit at 60 is a combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing ptivposes), black to be merged ii^to cyan, magenta and yellow (in the case of no black ink in the print head), and tag dot data to be placed in a visible plane. An output for fixative can readily be generated by simply combining all of the inpul bits. 'Ihe dot merger unit contains a fi-bit CoiorMnsk register 61 that is used as a mask against the 6 inptit bits. Each of the input bits is ANDed with the corresponding ColorMask register bit. and the resultant 6 bits are then ORed together to form the final output bit.
The ColorMask registers for each output are set depending on the meaning of the inpul layers and the available inks in the print head.
Assuming conlone layer I is cyan, contone layer 2 is magenta, contone layer 3 is yellow, and contone layer 4 is black, bi-level spoil is black, bi-level tag is infra-red:

• If the print head does not contain black ink, the ColorMask registers for Cyan, Magenta and Yellow would be: 011001, 011010, and 011100 respectively, thus placing the black ink into each of cyan, magenta, and yellow,
• !f all inks require fixative, the CoiorMask for ftxaiive would be; 111111. if infrared does not require fixative, the CoIorMask register for fixative would be 011111.
• If black ink is present in the print head, and for testing purposes we want to view the tags, simply set bit5ofltie black color channel's CoIorMask register, Bit5 of the infrared channel's CoIorMask register can be set or cleared as desired during this testing mode.
The Spot I color can be set to any base color simply by setting the appropriate bit of the CoIorMask register. For example:
* If spoil color is cyan, the cyan CoIorMask register would be 010001
♦ If spoil color is yellow, the yellow CoIorMask register would be 010100
" If spoil eolor is green, the cyan and yellow CoIorMask registers would be OIOOOl and OIOIOO respectively, to
enable spoil onto both cyan and yellow inks
* If spot I color is some special ink, such as gold, ii can be enabled into an ink channel simply by setting the
CoIorMask register of that channel to 010000. Tags, spotl and potentially contone planes should be
appropriately directed. For example, there are only 5 dot merger units but 6 inputs consequently one input is
either ignored or merged. For example, if spoil is gold and contone contains a black layer, then black contone
should be pushed into C. M and Y by setting the CoIorMask registers for Cyan, Magenta and Yellow to 011001,
011010, and 011100 respectively.
A fixative plane can readily be generated by selecting the bits that represent inks requiring the presence of fixative. For example:
• If all inks require fixative, the CoIorMask register for fixative would be 111111.
* If only black requires fixative, and spoil and contone 4 represent black, the CoIorMask register for fixative
would be 011000.
" If none of the cyan, magenta, yellow or black inks require fixative, but the infra-red ink requires fixative, the
CoIorMask register for fixative would be 100000.
In FIG. 7 is seen the doi reorg unit |DRU) which is responsible for taking the generated dot stream for a given color plane and organizing it into 32-bit quantities so that the output is in segment order, and in dot order within segments. Minimal reordering is required due to the fact that dots for overlapping segments are not generated in segment order. The DRU contains a 32-bil shift register, a regular 32-bit register, and a regular 16-bit register. A 5-bil counter keeps track of the number of bits processed so far. The dot advance signal from the dither matrix access unit (DMAU) is used to inslnicl the DRU as to which bits should be output.
In FIG. 7 registerlA) 62 is clocked every cycle. It contains the 32 most recent dots produced by the dot merger unit(DMU). The full 32-bit value is copied to register(B) 63 every 32 cycles by means of a WriteEnable signal produced by the DRU state machine 64 via a simple 5-bil counter Ihe 16 odd bits (bits 1,3, 5, 7 etc.) from register(B) 63 are copied to regisier(C) 65 with ihe same WriteEnable pulse. A 32-bil multiplexor 66 then selects between the following 3 outputs based upon 2 bits from the stale machine:
• the full 32 bits from register B
• A 32-bil value made up from the 16 even bits of register A (bits 0, 2,4. 6 etc) and ihe 16 even bits of register B. The 16 even bits from register A form bits 0 to 15, while the 16 even bits from register B form bits 16-31.
• A 32-bit value made up from the 16 odd bits of register B (bits 1, 3, 5. 7 etc) and the 16 bits of register C. The bits of

registerC form bits 0 to 15, while the odd bits from registers form bits 16-31.
The stale machine for the DRIJ can be seen in Table 1 It starts in state 0. li changes stale every 32 cycles. During the 32 cycies a single noOvertap bit collects the AND of all the dot ach-ance bits for those 32 cycles (noOverlap ■-dol advance for cycle 0, and noOverlap = noOverlap AND dol advance for cycles I to 31). Table I. State machine for DRU

state NoOverlap Output output Valid Comment next slate
) X B J Slanup stale i
1 1 B 1 Regular non-overlap 1
1 3 B 1 A contains first overlap 2
2 X Even A, even B ! A contains second
overlap
S contains first overlap 3
3 X C. odd B 1 C contains first overlap B contains second overlap 1
The margin unii (MU) 57. iti t-TG. 5. is respotisihle for turning ot^vance t/of and advance/i>ie signals from the dither matrix access unit (DMAU) 48 inio general control signals based on the page margins of the current page. It is also responsible for generating the end of page condition. The MU keeps a counter of dot and line across the page. Both are set to 0 at the beginning of the page. The dot counter is advanced by I each lime the MU receives a dol advance signal from the DMAU. When the MU receives a bne advance signal from the DMAU, Ihe line counser is ii\cTemented and the dot counter is reset to 0. f;ach cycle, the current line and dot values are compared to the margins of the page, and appropriate output ^or Advance, line advance hwAwiihin margin s\gi:\z\s?negi\cn based on these margins. The DMAU contains the only substantial memory requirements for the HCU.
In riG. 8 is seen the line loader / format unit (LLFU). It receives dol information from the HCU, loads the dots lor a given print line into appropriate buffer storage (some on chip, and some in external DRAM 34) and formats them into the order required for the print head. A high level block diagram oflhel-LFU in terms of its external interface is shown in FIG. 9. The input 67 to the LLFU is a set of 6 32-bil v^ords and a DataValid bit. all generated by the HCU. 'fhe output 68 is a set of 90 bits representing a maximum of 15 print head segments of 6 colors. Not all the output bits may be valid, depending on Viow many colors are actually ubed in the print head.
The physical placement of firing nozzles on the print head referenced above, nozzles in two offset rows, means that odd and even dots of (he same color are for two different lines. The even dots are for line L. and the odd dots are for line L-2. In addition, there is a number of lines between the dots of one color and the dots of another. Since the 6 color planes for the same dot position are calculated at one time by the HCU, there is a need to delay tVie dol data for each of the color planes until the same dot is positioned under the appropriate color nozzle
The size of each bufTer line depends on the width of the prim head. Since a single PEC generates dots for up to 15 print head segments, a single odd or even buffer line is therefore 15 sets of 640 dots, for a total of 9600 bits (1200 bytes). For example, the buffers required for color 6 odd dots totals almost 45 KBytes,
'Vhc entire set of requisite buflers might be provided on the PEC chip when manufacturing techniques arc capable. Otherwise, the buffers for colors 2 onward may be stored in external DRAM. This enables the PEC to be valid even though the distance between color planes may change in the future. It is trivial lo keep the even dots for color 1 on

PKC, since everything is printed relative to that particular dot line (no additional line buffers are needed). In addition, the 2 hair-lines required for buffering color I odd dots saves substantial DRAM bandwidth. The various line buffers (on chip and in DRAM) need to be pre-loaded with all Os belbre the page is printed so that it has clean edges. The end of the page is generated automatically by the HCU so it will have a clean edge.
In FIG \0 is seen a block diagram for Color N OESplit (see Oesplit 70 of FIG. 9), and Ihe block diagram for eachofthetwobuffersEandF,7i,72inFIG. 9 can be found in FlGs. lOaiidll. Buffer EF is a double buffered mechanism for transferrmg data to the prim head ititerfai;s (PHI) 11 iti FIG. 3. Buftets 1-: and F Cheiefore have iden\ical structures. During the processing oCa line of dots, one of the two buffers is written to while Ihe other is being read from. The two buffers are logically swapped upon receipt of the line-sync signal from the PHI, Both buffers E and F are composed of 6 sub-buffers, I sub-buffer per color, as shown in FIG. II, the color I sub-bufl'ernumbered 73. The size of each sub-buffer is 2400 byles. enough to hold 15 segments at 1280 dots per segment. The memory is accessed 32-bits at a time, so there are 600 addresses for each sub-buffer (requiring 10 bits of address). All the even dots are placed before the odd dots in each color's sub-buffer. If there is any unused space (for printing to fewer than 15 segments) it is located at the end ofeach color's sub-buffer. The amount of memory (ic;ua//>i w.serf from each sub-buffer is directly related to the number of segments actually addressed by the PEC, For a 15 segment print head there are 1200 bytes of even dots followed by 1200 bytes of odd dots, with no unused space. The number of sub-bulTers gainfully used is directly related to the number of colors used in the prim head. Themajcimum number of colors supported is 6.
The addressing decoding circuitry for each of b\if(i;rs E and F is such thai in a given tycle, a single 32-bit access can be made to all 6 sub-buffers ■ either a read from all 6 or a write lo one of the 6. Only one bit of the 32-bits read from each color buffer is selected, for a total of 6 output bits. The process is shown in FIG. II. 15 bits of address allow the reading ofa particular bit by means of 10-bits of address being used to select 32 bits, and 5-bits of address choose I-bit from those 32, Since all color sub-buffers share this logic, a single 15-bit address gives a total of 6 bits out, one bit per color. Each sub-butTer 73 to 78 has its own WriieEnable line, to allow a single 32-bit value to be written to a particular color buffer in a given cycle. The individual WrileEnables arc generated by ANDing the single WriieEnable input with the decoded form of ColorSelect. The 32-bits of Datain on line 79 are shared, since only one buffer will actually clock the data in.
Address generation for reading from buffers E and F is straightforward. Each cycle generates a bit address that is used to fetch 6 bits representing 1 -bit per color for a particular segment. By adding 640 to the current bit address, we advance lo the next segment's equivalent dot, Wi add &40 (tvot 1280) since the odd and even dwls are separated in the buffer. We do this SutnSegments times to retrieve the data representing the even dots, and transfer those bits to the PHI. Whea :\'! In addition, we generate the TiVriieEnable control signal for writing to the 90-bit Transfer register 90 in FIG, 9, Since ihe LLFU starts before ihe PHI, we must transfer the first value before the Advance pulse from the PHI, We must also generaie the next value in readiness for the first Advance pulse. The solution is to transfer the first value lo the Transfer register after NumSegments cycles, and then to stall NumSegmenis cycles later, waiting for the Advance pulse lo start Ihe next NumSegmenis cycle group. Once the first Advance pulse arrives, the LLFU is synchronized lo the PHI, The read process for a single dotline is shown in the following pseudocode:

buffer EF. Upon receipt of the second OutputValid signal of the group of two, we write the 32-bits of odd dalaio the same location in buffer AB that we read from previously, and we write the 32-bits of even data to color 1 within buffer EF,
The HCU provides 32 bits of data per color plane whenever the OutputValid control flag is set. This occurs every 32 c>cles excepi during cenain startup times. The 32 bits define a contiguous set of 32 dots for a single dot line - 16 even dots (bits 0, 2, 4 etc.), and 16 odd dots (bits 1.3. 5 etc.).
While buffer 0E| (83 in FIG, 10) is used to store a single 32>bii value for color 1, buffers OEj to OE^ are used to store a single 32-bit value for colors 2 to 6 respectively. Just as the data for color 1 is split into 32-bits representing color 1 odd dots and 32-biis representing color I even dots every 64 cycles (once every two OutputValid flags), the remaining color planes are also split into even and odd dots.
However, instead of being written directly to buffer EF, the dot data is delayed by a number of lines, and is written out to DRAM via buffer CD (84 in FIG. 9), While the dots for a given tine are written to DRAM, the dots foe a previous line are read from DRAM and written to buffer EF (71,72). This process must be done interleaved with the process writing color 1 to buffer VJr.
Every time an OutputValid flag is received from the HCU on lineKS in ¥K. 10, the 32-bits of color N data are written to buffer OEM (83). Every second OutputValid flag, the combined 64-bit value is written to color buffer N (86). This happens in parallel for all color planes 2-6, Color Buffer N (86) contains 40 s^ts of 64-bits (320 bytes} to enable the dots for two complete segments to be stored. This allows a complete segment generation time (20 x 64 = 1280 cycles) for the previous segment's data (both odd and even dots) to be written out to DRAM. Address generation for writing is straightforward. The ColorNWriteEnable signal on line 87 is given every second OutputValid Hag, The address starts at 0, and increments every second OutputValid flag until 39. Instead of advancing to 40, the address is reset to 0, thus providing the double-buffering scheme. This works so long as the reading does not occur during the OutputValid flag, and that the previous segment's data can be written \o DRAM in ibe time il takes to generate a single segment's data. The process is shown in the I'ollowing pseudocode:

EndWhile Address generation for reading is trickier, since it is tied to the timing tor DRAM access (both reading and writing), buffer EF access, and therefore color I generation. It is more fully explained below.
Address generation for buffers C, P, E, F, and i;olorN are all tied to the timing of DRAM access, and must not itiiccfere with color I processing with regards to buffers Band F The basic principle is that the data for a single segment of color N (either odd or even dots) is transferred from the DRAM lo buffer EF via buffer CD, Once the data has been read from DRAM those dots are replaced based on the values in CokirBufferN. This is done for each of the colors in odd and even dots. After a complete segment's worth of dots has accumulated (20 sets of 64 cycles), then the process begins again. Once the data for all segments in a given prinlline has been transferred from and lo DRAM, the current address for thai color's DRAM buffer is advanced so that it will be the appropriate number of lines until the particular data for the color's line is read back from DRAM, In this respect then, the DRAM acts as a form of FIFO. Consequently color N (either odd or even) is read from DR;\M into buffer D while copying color N (same odd/even sense) to buffer C, The copying of data to buffer C takes 20 or 21 cycles depending on whether the OulputVaiid flag occurs during the 20 transfers. Once both tasks have finished (typically the DRAM access will be the slower task), the second part of the process begins. The data in buffer C is written to DRAM (the same locations as were just read) and the data in buffer D is copied lo buffer EF (again, no color N data is transferred to buffer EF while the OulputVaiid flag is set since color I data is being transferred). When both tasks have finished the same process occurs for the other sense of color N (either odd or even), and then for each of the remaining colors. The entire double process happens 10 times. The addresses for each of the current lines in DRAM are then updated for the next line's processing to begin.
In terms of bandwidth, the DRAM access for dot data butlers consumes the great majority of all DRAM access from PEC, For each print line we read an entire dot line for colors 2-6, and write an entire dot line for colors 2-6. For the maximum of 15 segments this equates to 2 v 5 x 15 x 1280 bits = 192,000 bits (24,000 bytes) per print line. For the fastest printing system (30,000 lines per second) this equates to 687 MB/sec. For 1 page per second printing the bandwidth required is 312 MB/sec. Since the bandwidth is so high, the addresses of the various half-lines for each color in DRAM should be Optimized for the memory type being used. In an RDRAM memory system for example, the very first half-line buffer is aligned for each color to a I KByte boundary to maximize page-hits on DRAM access. As the various segments are processed it is necessary to ensure that if the start of the next segment was going to be aligned at byte 960 within the I KByte page, then the 640-bit access would span 2 pages. Therefore the variable DiUMMiMFa/is used lo check for this case, and if it occurs, the address is rounded up for the next half-line buffer to be page-aligned. Consequently the only waste is 64 bytes per 13 segments, but have the advantage of the 64()-bil access completely within a single page.
The address generation process can he considered as NumSagmenls worth of 10 sets of: 20 x 32-bil reads followed by 20 x 32-bit writes, and it can be seen in the following pseudocode:
EFStartAdr = 0
Do NumScgments times:
For CurrColor = 0 to MaxHalfColors
DRAMSlartAddress - ColorCurrAdr[CurrColor]
While reading 640 bits from DRAMSlartAddress into D{>= 20 cycles) ColorNAdr = 0 While (ColorNAdr 1=20)
If (NOT HCl) OulputVaiid)

(colors 2-6 in odd and even), and so MaxHaifColors should be set to 9.
The LLFU rtquiies 2.\'umSeginen!s cycks io prepare ihe first 180 bits ofdala for the PHI. Consequently the print head
should be started and the first LineSync pulse must occur ihis period of lime after the LLFU has started. This allows the
initial Transfer value to be valid and the next 90-bil value lo be ready lo be loaded into the Transfer register.
The prim head interlace (PHI) is the means by which ihe processor loads the print head with the dots lobe printed, and
comrols llie acWa! dot pvinling process, ll takes input from the LLFU and outputs data to the print head itself. The PHI
will becapableof dealing with a variety of print head lengths and formats. Theinlemal struelure of the PHI should allow
for a maximum of 6 colors, 8 segments per transfer, and a maximum of 2 segment groups. This should be siiRleieni for a
15 segment (8.5 inch] printer capable of priming A4/Letter at full bleed.
Throughout the specification the aim has been to describe the preferred embodiments of the invention without limiting the invention lo any one embodiment or specific collection of features. Persons skilled in the art may realize variations from the specific embodiments that will nonetheless fall within the scope of the invemifm

WE CLAIM:
1. A print controller to drive an ink drop print head comprising:
an interface at which to receive compressed page data;
decoders to decode respective types of image planes in the received compressed page data; and
a half-toning and composing unit to composite image plane data;
the half-toning and composing unit comprising:
a dot merger unit taking bits from the respective planes as mputs; and
a color mask register holding masking bits in number equal to the number of image planes;
respective input bits to the dot merger unit being ANDed with respective color mask register bits and
the resultant bits ORed together to form an output bit in a channel for which there is an ink at the print head.
2. The prmt controller as claimed in claim 1 wherein the respective planes to the dot merger unit comprises three contone color planes and a high resolution plane and the color mask register is loaded with bits that are selected to place the high resolution plane into anyone of the respective color channels.
3. The print controller as claimed in claim 2 wherein a fixative channel is generated from anyone or more of the respective planes and selected by what bits are loaded to the color mask register.

4. The print controller as claimed in claim 1 wherein the color mask register is loaded with bits that are selected to split a K plane into C, M, and Y channels for output to a print head without K.
5. The print controller as claimed in claim 1 wherein the half-toning and composing unit comprises a tag encoder generating an infrared tag data plane and the color mask register maps its dots into an infrared channel at the print head.
6. The print controller to drive an ink drop print head comprising:
a contone image decoder to decode any compressed continuous tone image planes in the received compressed page data;
a high resolution image decoder to decode any compressed high resolution image plane; and
a half-toning and composing unit comprising a dot merger unit controlled by a color mask to map image planes into channels corresponding to what inks are supplied in the print head that is interfaced by the print controller.
7. The print controller as claimed in claim 6, wherein the half-toning and composing
unit comprises:
a margin unit to apply margin data to the respective image planes during the composite process.
8. The print controller chip to interface with an ink drop print head comprising:
an interface at which to receive compressed page data;

a contone image decoder to decode any continuous tone image planes in the received compressed page data;
a high resolution decoder to decode any high resolution image plane in the received compressed page data;
a half-toning and composing unit comprising to dither any continuous tone image planes and composite any high resolution image plane data with any output plane includmg a dot merger unit controlled by a color mask to map image planes into channels corresponding to what inks are supplied in the print head that is interfaced by the print controller; and
a print head driver to output the composite to a print head.
9. An ink drop printer driven by a print controller comprising:
an interface at which to receive compressed page data;
a contone image decoder to decode any continuous tone image planes m the received compressed page data;
a high resolution image decoder to decode any high resolution image planes in the received compressed page data;
a half-toning and composmg unit to dither any contmuous tone image planes and composite high resolution image plane data with any output plane comprising a dot merger unit controlled by a color mask to map image planes into channels corresponding to what inks are supplied in the print head that is interfaced by the print controller;
a print head driver to output the composite to a print head; and
a print head.

10. A method of operating an ink drop printer comprising:
receiving compressed page data
decoding any continuous tone image planes in the received compressed page data to generate output planes;
decoding any high resolution image plane in the received compressed page data to generate an output plane;
dithering any continuous tone image planes,
compositing any high resolution image plane data with any output plane; and
forwarding composited data to a print head with image planes mapped to what inks are available at the print head.

Documents:

in-pct-2002-1905-che abstract-duplicate.pdf

in-pct-2002-1905-che abstract.pdf

in-pct-2002-1905-che claims-duplicate.pdf

in-pct-2002-1905-che claims.pdf

in-pct-2002-1905-che correspondence-others.pdf

in-pct-2002-1905-che correspondence-po.pdf

in-pct-2002-1905-che description (complete)-duplicate.pdf

in-pct-2002-1905-che description (complete).pdf

in-pct-2002-1905-che drawings-duplicate.pdf

in-pct-2002-1905-che drawings.pdf

in-pct-2002-1905-che form-1.pdf

in-pct-2002-1905-che form-19.pdf

in-pct-2002-1905-che form-26.pdf

in-pct-2002-1905-che form-3.pdf

in-pct-2002-1905-che form-4.pdf

in-pct-2002-1905-che form-5.pdf

in-pct-2002-1905-che pct.pdf

in-pct-2002-1905-che petition.pdf

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Patent Number

201803

Indian Patent Application Number

IN/PCT/2002/1905/CHE

PG Journal Number

08/2007

Publication Date

23-Feb-2007

Grant Date

17-Aug-2006

Date of Filing

22-Nov-2002

Name of Patentee

SILVERBROOK RESEARCH PTY LTD

Applicant Address

393 Darling Street Balmain, NSW 2041

Inventors:

#	Inventor's Name	Inventor's Address
1	WALMSLEY, Simon, Robert	Unit 3, 9 Pembroke Street Epping, NSW 2121

PCT International Classification Number

B41J2/205

PCT International Application Number

PCT/AU00/00511

PCT International Filing date

2000-05-24

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA