Title of Invention

Multiple frequency band sythesizer using a single voltage controlled oscillator

Abstract A multiple frequency band synthesizer comprising: a reference signal generation circuit for generating a frequency reference signal of which frequency is controlled in accordance with a reference frequency control signal; a phase comparator for phase-comparing a frequency-divided signal with said frequency reference signal to output a phase difference signal; a low-pass filter for low-pass-filtering said phase difference signal with one of a plurality of cut-off frequencies selected in response to a filter control signal; a voltage controlled oscillator for generating and outputting an oscillation signal in one of a plurality of frequency bands in accordance with a predetermined combination of said reference frequency control signal and said filter control signal and an output of said low pass filter; a frequency dividing circuit for frequency dividing said oscillation signal and supplying said frequency divided signal to said phase comparator; and a control circuit for generating said reference frequency control signal and said filter control signal in accordance with a frequency command signal.
Full Text BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a multiband PLL frequency synthesizer for generating a frequency signal over a plurality of bands.
2. Description of the Prior Art
A multiband PLL frequency synthesizer for generating a frequency signal over a plurality of bands is known.
Fig. 7 is a block diagram of a prior art multiband PLL (phase-locked loop) frequency synthesizer. This prior art multiband PLL frequency synthesizer includes three PLL frequency synthesizing circuits 313, 314, and 315. The PLL frequency synthesizing circuits 313, 314, and 315 generate frequency signals at different bands respectively. Fig. 8 is an illustration of the prior art showing an example of using the prior art multiband PLL frequency synthesizer shown in Fig. 7. In Fig. 8. the PLL frequency synthesizing circuits 313, 314, and 315 generate frequency signals at bands fl to f2, f3 to f4, and f5 to f6 respectively. A switch 316 outputs one of the frequency signals from the PLL frequency synthesizing circuits 313, 314, and 315.
In this circuit, there are many parts used because
three similar circuits are used.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a superior multiband PLL frequency synthesizer.
According to the present invention there is provided a first PLL frequency synthesizer which includes: a reference signal generation circuit for generating a reference signal of which frequency is controlled in accordance with a reference frequency control signal; a phase comparing circuit for phase-comparing a frequency-divided signal with the frequency reference signal to output a phase difference signal; a low-pass filter circuit for low-pass-filtering the phase difference signal with one of a plurality of cut-off frequencies selected in response to the filter control signal; a voltage controlled oscillation circuit for generating and outputting an oscillation signal in accordance with an output of the low-pass filter circuit; a frequency dividing circuit for frequency-dividing the oscillation signal and supplying the frequency-divided signal to the phase comparing circuit; and a control circuit for generating the reference frequency control signal and the filter control signal in accordance with a frequency command signal.
In the first PLL frequency synthesizer, the frequency divining circuit frequency-divides the
oscillation signal in first and second modes in accordance with a frequency dividing control signal, the frequency dividing circuit frequency-dividing the oscillation signal by an integer in the first mode and frequency-dividing the oscillation signal in the second mode such that the oscillation signal is divided by a fraction using control data, the control circuit further generating the frequency dividing control signal, the integer, and control data in accordance with the frequency command signal. In this case, the frequency dividing circuit includes a frequency divider supplied with the integer and a dividing control circuit for controlling the frequency divider in the second mode such that the integer is periodically varied in accordance with the frequency dividing control signal.
In the first PLL frequency synthesizer, the low-pass filter circuit comprises a loop filter for charging and discharging a constant current for a phase difference interval represented by the phase difference signal and a switch controlled in response the filter control signal, one terminal of the switch being supplied with the phase difference signal, and a filter circuit including a first capacitor of which one terminal is connected the other terminal of the switch, the other terminal of the first capacitor being connected to the ground, and a series circuit including a resistor and a second capacitor, one
end of the series circuit being connected to the other terminal of the switch and the other end of the series circuit being connected to the ground.
In the first PLL frequency synthesizer, the voltage controlled oscillation circuit includes a plurality of oscillation circuits, the oscillation signal is outputted by one of a plurality of the oscillation circuits in accordance with an oscillation control signal, the control circuit further generating the oscillation control signal in accordance with the frequency command signal.
According to the present invention there is provided a second PLL frequency synthesizer which includes: a reference signal generation circuit for generating a reference signal of which frequency is controlled in accordance with a reference frequency control signal; a phase comparing circuit for phase-comparing a frequency-divided signal with the frequency reference signal to output a phase difference signal; a low-pass filter circuit for low-pass-filtering the phase difference signal; a voltage controlled oscillation circuit for generating and outputting an oscillation signal in accordance with an output of the low-pass filter circuit: a frequency dividing circuit for frequency-dividing the oscillation signal in first and second modes in accordance with a frequency dividing control signal, the frequency
dividing circuit frequency-dividing the oscillation signal by an integer in the first mode and frequency-dividing the oscillation signal in the second mode such that the oscillation signal is divided by a fraction, and supplying the frequency-divided signal to the phase comparing circuit; and a control circuit for generating the reference frequency control signal and the frequency dividing control signal in accordance with a frequency command signal.
In the second PLL frequency synthesizer, the frequency dividing circuit includes a frequency divider supplied with the integer and a dividing control circuit for controlling the frequency divider in the second mode such that the integer is periodically varied in accordance with the frequency dividing control signal.
In the second PLL frequency synthesizer, the low-pass-filtering circuit low-pass-filters the phase difference signal with one of a plurality of cut-off frequencies selected in response to a filter control signal and the control circuit further generates the filter control signal in accordance with the frequency command signal. In this case, the low-pass filter circuit includes a loop filter for charging and discharging a constant current for a phase difference interval represented by the phase difference signal and a switch controlled in response the filter control signal, one terminal of the switch being
supplied with the phase difference signal, and a filter circuit including a first capacitor of which one terminal is connected the other terminal of the switch, the other terminal of the first capacitor being connected to the ground, and a series circuit including a resistor and a second capacitor, one end of the series circuit being connected to the other terminal of the switch and the other-end of the series circuit being connected to the ground.
In the second PLL frequency synthesizer, the voltage controlled oscillation circuit includes a plurality of oscillation circuits, the oscillation signal is outputted by one of a plurality of the oscillation circuits selected in accordance with an oscillation control signal, the control circuit further generating the oscillation control signal in accordance with the frequency command signal.
Accordingly the present invention relates to a multiple frequency band synthesizer comprising:
a reference signal generation circuit for generating a frequency reference signal of which frequency is controlled in accordance with a reference frequency control signal;
a phase comparator for phase-comparing a frequency-divided signal with said frequency reference signal to output a phase difference signal;
a low-pass filter for low-pass-filtering said phase difference signal with one of a plurality of cut-off frequencies selected in response to a filter control signal;
a voltage controlled oscillator for generating and outputting an oscillation signal in one of a plurality of frequency bands in accordance with a predetermined combination of said reference frequency control signal and said filter control signal and an output of said low pass filter;
a frequency dividing circuit for frequency dividing said oscillation signal and supplying said frequency divided signal to said phase comparator; and
a control circuit for generating said reference frequency control signal and said filter control signal in accordance with a frequency command signal.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The object and features of the present invention will become more readily apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Fig. 1 is a block diagram of a multiband PLL frequency synthesizer of a first embodiment;
Fig. 2 is a block diagram of a frequency dividing circuit shown in Fig. 1;
Fig. 3 is a time chart of the first embodiment
showing an operation of the frequency dividing circuit shown in Fig. 1;
Fig. 4 is a block diagram of a multiband PLL frequency synthesizer of a second embodiment;
Fig. 5 is a block diagram of a voltage controlled oscillation circuit shown in Fig. 4;
Fig. 6 is an illustration of the second embodiment showing an example of using the multiband PLL frequency synthesizer of the second embodiment;
Fig. 7 is a block diagram of a prior art multiband PLL frequency synthesizer; and
Fig. 8 is an illustration of the prior art showing an example of using the prior art multiband PLL frequency synthesizer shown in Fig. 7.
The same or corresponding elements or parts are designated with like references throughout the drawings. DETAILED DESCRIPTION OF THE INVENTION
Hereinbelow will be described a first embodiment of this invention.
Fig. 1 is a block diagram of a multiband PLL frequency synthesizer of a first embodiment.
The multiband PLL frequency synthesizer of the first embodiment includes a frequency reference signal generation circuit 1 for generating a frequency reference signal (clock signal) lc of which frequency is controlled in
accordance with a reference frequency control signal 13a, a phase comparator 2 for phase-comparing a frequency-divided signal 10a with the frequency reference signal 1c to output a phase difference signal 2a, a low-pass filter 3 for low-pass-filtering the phase difference signal 2a with one of a plurality of cut-off frequencies selected in response to a filter control signal 13b, a voltage controlled oscillator 4 for generating and outputting an oscillation signal in accordance with an output of the low-pass filter 3, a frequency dividing circuit 10 for frequency-dividing the oscillation signal and supplying the frequency-divided signal 10a to the phase comparator 2, and a control circuit 13 for generating the reference frequency control signal 13a and the filter control signal 13b in accordance with a frequency command signal 16.
The frequency divining Circuit 10 frequency-divides the oscillation signal in first and second modes in accordance with a frequency dividing control signal 13c. The frequency dividing circuit 10 frequency-divides the oscillation signal by an integer M in the first mode and frequency-divides the oscillation signal in the second mode such that the oscillation signal is divided by a fraction. That is, in the first mode, an integer frequency dividing operation is effected and in the second mode, a fraction frequency dividing operation is effected. The control
circuit 13 further generates and supplies the frequency dividing control signal 13c, the integer M, and a constant k for the fraction operation as control data in accordance with the frequency command signal 16. More specifically, the control circuit 13 generates the reference frequency control signal 13a, the filter control signal 13b, the frequency dividing control signal 13c including the integer M and the constant k in accordance with the frequency command signal 16 using a ROM table included therein.
The low-pass filter 3 includes a loop filter 12 for charging and discharging a constant current for a interval corresponding to a phase difference interval represented by the phase difference signal 2a and a switch 9 controlled in response the filter control signal 13b and a filter circuit 8. One terminal 9a of the switch 9 is supplied with the phase difference signal 2a. The filter circuit 8 includes a first capacitor 5 of which one terminal 5a is connected the other terminal 9b of the switch 9 and of which the other terminal 5a is connected to the ground, and a series circuit 8a including a resistor 7 and a second capacitor 6. One end of the series circuit 8a is connected to the other terminal 9b of the switch 9 and the other end of the series circuit 8a is connected to the ground.
Fig. 2 is a block diagram of a frequency dividing circuit 10 shown in Fig. 1.
The frequency dividing circuit 10 includes a frequency divider 15 supplied with the integer M and a dividing control circuit 11 for controlling the frequency divider 15 in the second mode such that the integer M is periodically varied in accordance with the constant k in the frequency dividing control signal 13c.
An operation of the first embodiment will be described.
The reference signal generation circuit 1 generates the frequency reference signal (clock signal) lc. The frequency of the frequency reference signal is controlled in accordance with the reference frequency control signal 13a.
The phase comparator 2 compares a phase of the frequency-divided signal 10a with a phase of the frequency reference signal 13a and supplies the phase difference signal 2a to the low-pass filter 3.
The low-pass filter 3 effects low-pass-filtering the phase difference signal 2a. The cut-off frequency is selected from a plurality of the cut-off frequencies in response to the filter control signal 13b. More specifically, the loop filter 12 of the low-pass filter 3 charges and discharges a constant current for the interval corresponding to the phase difference interval represented by the phase difference signal 2a, so that a cutoff
frequency, that is, a cutoff angular frequency  n1 is provided. When the switch 9 is made close in response the filter control signal 13b, the filter circuit 8 is added to the input of the loop filter 12, so that the filter circuit 8 acts as a part of the loop filter 12. It is assumed that the cutoff frequency of the filter circuit 8 is lower than that of the loop filter 12, that is, the passband of the filter circuit 8 is narrower than that of the loop filter 12. Then, when the switch 9 is made close, the cutoff angular frequency o) n of the PLL loop is lower than that when the switch is open, so that the passband of the filter circuit 3 can be varied in accordance with the filter control signal 13b.
The voltage controlled oscillator 4 generates and outputs the oscillation signal in accordance with an output of the low-pass filter 3 and outputs a local oscillation signal as the output of the multiband PLL frequency synthesizer of the first embodiment.
The frequency dividing circuit 10 effects frequency-dividing the oscillation signal and supplies the frequency-divided signal 10a to the phase comparator 2, so that the PLL feedback loop is provided.
In the frequency dividing circuit 10, in the first mode, it effects the integer frequency dividing operation and in the second mode, it effects the fraction frequency
dividing operation such that the oscillation signal is divided by a fraction.
More specifically, the frequency dividing circuit 10 includes the frequency divider 15 and a dividing control circuit 11. The dividing control circuit 11 includes an accumulator 103 having an adder 101 and a latch 102.
The dividing control circuit 11 controls a divisor I) for the frequency divider 15 to provide the fraction frequency dividing operation in the second mode such that: the divisor D is varied periodically to equivalently provide a fraction of the divisor.
Fig. 3 is a time chart of the first embodiment showing an operation of the frequency dividing circuit 10 shown in Fig. 1.
Assuming that a period 1/fr of the frequency reference signal lc is one clock CLK, the divisor D varies from the integer M to M + 1 every L clocks (interval T), so that an average of the divisor D for the interval T is given by M + 1/L. The fraction term 1/L can be treated as k/L and k is varied such that k= 0, 1, 2, ••• , so that the divisor D can be set every step of 1/L. Then, the average divisor Mave is given by:
Mave = M + k/L (0 ≤ k ≤ L, k is an integer) (1)
This operation is provided by the accumulator 103 having an adder 101 and a latch 102. In Fig. 2, a value in
the adder 101 increases by k every clock CLK which is the frequency reference signal 1c and when the adder overflows, the adder 101 supplies an overflow signal +1 to the frequency divider, the divisor D becomes M + 1. If the adder does not supplies the overflow signal +1, the divisor D maintains the integer M.
This fraction frequency dividing operation expands the cutoff angular frequency Moreover, a combination of variation in the low-pass filter 3 and the variation in the frequency dividing circuit 10, that is, the combination of narrow passband and wide passband in the low-pass filter 3 and the integer frequency dividing operation and the fraction frequency dividing operation can provide three cutoff angular frequencies w n of the loop as shown in TABLE 1.
TABLE 1

(Table Removed)
As shown in table 1, the loop condition can be controlled by controlling only the cutoff frequency and controlled by switching the frequency dividing operation and the combination is possible. Moreover, as shown in table 1, it is possible that the oscillation signal is outputted from the voltage controlled oscillator at a plurality of frequency bands which may be intermittently arranged in the frequency base or may be continued in the
frequency base.
As mentioned, the frequency of the local oscillation signal can be varied over a relatively wider range stable by adaptively varies the feedback loop condition, that is, the cutoff angular frequency and the frequency dividing-operation, i.e., the integer frequency dividing operation and the fraction frequency dividing operation.
A second embodiment will be described.
Fig. 4 is a block diagram of a multiband PLL frequency synthesizer of the second embodiment.
The multiband PLL frequency synthesizer of the second embodiment is substantially the same as that of the first embodiment. The difference is that a voltage controlled oscillation circuit 14 is used instead of the voltage controlled oscillator 4.
Fig. 5 is a block diagram of a voltage controlled oscillation circuit 14 shown in Fig. 4. Fig. 6 is an illustration of the second embodiment showing an example of using the multiband PLL frequency synthesizer of the second embodiment.
The voltage controlled oscillation circuit 14 includes a plurality of oscillation circuits 201 and 202 The local oscillation signal is outputted from one of a plurality of the oscillation circuits 201 and 202 in accordance with an oscillation control signal 13d from the control circuit 13. That is, the control circuit 13 further generates the oscillation control signal 13d in accordance with the frequency command signal 16.
The oscillation circuit 201 is used to oscillate at a range over two different frequency bands A and B. The oscillation circuit 202 is used to oscillate at further different frequency band C, wherein one of oscillation
circuits 201 and 202 is operated in response to supplying- a power Vcc via a switch 204. An amplifier 203 amplifies the output of either of the oscillation circuit 201 or 202 to output the local oscillation signal.
The oscillation circuit 201 is used to generate the local oscillation signal at either of frequency band A or B and the oscillation circuit 202 generates the local oscillation signal at a frequency band C. Therefore, the frequency of the local oscillation signal from the local oscillation circuit 14 is at either of the frequency band A, B, or C.
Table 2 shows designing data of the multiband PLL frequency synthesizer of the second embodiment.
TABLE 2

(Table Removed)
As shown in table 2, in the oscillation circuit 201, the oscillation frequency band is wide, so that VCO controlling sensitivity is different, that is, it is 120 at the frequency band A and it is 80 at the frequency band 3 because a linearity of a variable capacitance diode (not shown) used in the oscillation circuit 201 is not maintained between the frequency bands A and B.
Moreover, because the loop gains K at respective frequency bands are different each other, if the reference
frequency is constant and the cutoff frequency is not changed, it is difficult to provide the same characteristics at respective frequency bands A, B, and C.
More specifically, at frequency band C where the loop gain is lowest, the cutoff angular frequency co n is low and increases in the order of the frequency band B and frequency band A. Then, as similar to the first embodiment, the passband of the loop filter is varied and the frequency of frequency reference signal is varied (the frequency dividing mode is changed) every frequency bands to provide three cutoff angular frequencies a> n in only one PLL loop to optimum the PLL loop every frequency band,
Determination of respective constants in the multiband PLL synthesizer of the second embodiment will be described.
At first, in Fig. 4, the switch 9 is made open to make the low-pass filter a broad band and the integer frequency dividing operation, that is, the first mode, is set. In this condition, respective constants in the loop filter 12 are determined to obtain a desired characteristic at the frequency band B where the loop gain is secondly largest. Then, with the frequency dividing mode maintained, that is in the first mode, the switch 9 is made close to make the low-pass filter 3 in a narrow band mode and then, constants of the capacitors 5 and 6, and the resistor 7 in
the filter circuit 8 is determined to provide a desired characteristic at the frequency band A where the loop gain is largest. Finally, the switch 9 is made open, to provide the filter circuit 3 in a wide band condition, and then, the value of L supplied to the dividing control circuit 11 is determined at the frequency band C where the loop gain in smallest in the fraction frequency dividing operation mode, that is, the second mode.
As mentioned, at the frequency band where the loop gain is large, the reference frequency (frequency dividing mode) and the passbands of the low-pass filter 3 are determined to make the cutoff angular frequency



WE CLAIM:
1. A multiple frequency band synthesizer comprising:
a reference signal generation circuit for generating a frequency reference signal of which frequency is controlled in accordance with a reference frequency control signal;
a phase comparator for phase-comparing a frequency-divided signal with said frequency reference signal to output a phase difference signal;
a low-pass filter for low-pass-filtering said phase difference signal with one of a plurality of cut-off frequencies selected in response to a filter control signal;
a voltage controlled oscillator for generating and outputting an oscillation signal in one of a plurality of frequency bands in accordance with a predetermined combination of said reference frequency control signal and said filter control signal and an output of said low pass filter;
a frequency dividing circuit for frequency dividing said oscillation signal and supplying said frequency divided signal to said phase comparator; and
a control circuit for generating said reference frequency control signal and said filter control signal in accordance with a frequency command signal.
2. The multiple frequency band synthesizer as claimed in claim
1, wherein said frequency dividing circuit frequency divides said
oscillation signal in first and second modes in accordance with a
frequency dividing control signal, said frequency dividing circuit
frequency dividing said oscillation signal by an integer in said first
mode and frequency dividing said oscillation signal in said second
mode such that said oscillation signal is divided by a fraction using
control data, said control circuit further generating said frequency
dividing control signal, said integer and said control data in
accordance with said frequency command signal.
3. The multiple frequency band synthesizers as claimed in claim
2, wherein said frequency dividing circuit comprises:
a frequency divider supplied with said integer; and
a dividing control circuit for controlling said frequency divider in said second mode such that said integer is periodically varied in accordance with said frequency dividing control signal.
4. The multiple frequency band synthesizer as claimed in claim
1, wherein said low pass filter means comprises a loop filter for
charging and discharging a constant current for a phase difference
interval represented by said phase difference signal and a switch
controlled in response said filter control signal, one terminal of said switch being supplied with said phase difference signal, and a filter circuit including a first capacitor of which one terminal is connected to the other terminal of said switch, the other terminal of said first capacitor being connected to the ground, and a series circuit including a resistor and a second capacitor one end of said series circuit being connected to the other terminal of said switch and the other end of said series circuit being connected to the ground.
5 The multiple frequency band as claimed in claim 1
wherein said voltage controlled oscillator includes a plurality of oscillation circuits said oscillation signal is outputted by one of a plurality of said oscillation circuits in accordance with an oscillation control signal, said control means further generating said frequency command signal.
6. A multiple frequency band synthesizer comprising:
a reference signal generation circuit for generating a reference signal of which frequency is controlled in accordance with a reference frequency control signal;
a phase comparator for phase comparing a frequency divided signal with said frequency reference signal to output a phase difference
signal;
a low pase filter for low pase filtering said phase difference signal;
a voltage controlled oscillator for generating and outputting an oscillation signal in accordance with an output of said low pass filter.
a frequency dividing circuit for frequency dividing said oscillation signal in first and second modes in accordance with a frequency dividing control signal, said frequency dividing circuit frequency dividing said oscillation signal by an integer in said first mode and frequency dividing said oscillation signal in said second mode such that said oscillation signal is divided by a fraction, and supplying said frequency-divided signal to said phase comparator; and
a control circuit for generating said reference frequency control signal and said frequency dividing control signal in accordance with a frequency command signal, wherein said voltage controlled oscillator generates and outputs said oscillation signal at one of a plurality of frequency bands in cooperation with said frequency dividing circuit and said control circuit.
7, The multiple frequency band synthesizer as claimed in claim 6,, wherein said frequency dividing circuit comprises:
a frequency divider supplied with said integer; and
a dividing control circuit for controlling said frequency divider in said second mode such that said integer is periodically varied in accordance with said frequency dividing control signal.
8. The multiple frequency band synthesizer as claimed in claim 6, wherein said low pass filter said phase difference signal with one of a plurality of cut-off frequencies selected in response to a filter control signal, said control circuit further generating said filter control signal in accordance with said frequency command signal.
9. The multiple frequency band synthesizer as claimed in claim 8, wherein said low pass filter comprises a loop filter for charging and discharging a constant current for a phase difference interval represented by said phase difference signal and a switch controlled in response said filter control signal, one terminal of said switch being supplied with said phase difference signal, and a filter circuit including a first capacitor of which one terminal is connected ther other terminal of said first capacitor being connected to the ground, a series circuit including a resistor and a second capacitor, one end of said series circuit being connected to the other terminal of said switch and the other end of said series circuit being connected to the ground.
10. The multiple frequency band synthesizer as claimed in claim 6, wherein said voltage controlled oscillator includes a plurality of oscillation circuits, said oscillation signal is outputted by one of a plurality of said oscillation circuits in accordance with an oscillation control signal, said control circuit further generating
said oscillation control signal in accordance with said frequency command signal.


Documents:

1022-del-1998-abstract.pdf

1022-del-1998-claims.pdf

1022-del-1998-complete specification (granded).pdf

1022-del-1998-correspondence-others.pdf

1022-del-1998-correspondence-po.pdf

1022-del-1998-description (complete).pdf

1022-del-1998-drawings.pdf

1022-del-1998-form-1.pdf

1022-del-1998-form-13.pdf

1022-del-1998-form-19.pdf

1022-del-1998-form-2.pdf

1022-del-1998-form-3.pdf

1022-del-1998-form-4.pdf

1022-del-1998-form-6.pdf

1022-del-1998-pa.pdf

1022-del-1998-petition-137.pdf

1022-del-1998-petition-138.pdf


Patent Number 199598
Indian Patent Application Number 1022/DEL/1998
PG Journal Number 37/2008
Publication Date 12-Sep-2008
Grant Date 05-Jan-2007
Date of Filing 21-Apr-1998
Name of Patentee Matsushita Electric Industrial Co. Ltd.,
Applicant Address 1006, Oaza Kadoma, Kadoma-shi, Osaka 571-0050
Inventors:
# Inventor's Name Inventor's Address
1 Hisashi Adachi 6-7-36, Minoo, Minoo-shi, Osaka 562-0001
2 Hidenobu Kato 749-1, Saedo-cho, Tsuzuki-ku, Yokohama 224
3 Daisuke Tobise 2600-92-206, Kozukue-cho, Kohoku-ku, Yokohama 222
PCT International Classification Number H03L 7/08
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 9-121483 1997-04-25 Japan