Title of Invention

Apparatus of testing atm network and method thereof

Abstract The present invention discloses an apparatus of testing an ATM network and a method thereof for verifying the ATM network's capacity by verifying transmitted and received ATM cells. The ATM network test apparatus includes an input/output means for inputting and outputting predetermined information and verification information; a cell generation means for generating an ATM transmit cell and for outputting the ATM cell based on the predetermined information; at least one of matching means for matching the ATM transmit cell with an ATM receive cell, respectively; and a cell verification means for detecting the verification information from the ATM receive cell.
Full Text 1 FIeld of the Invention
I he present invention relates to an apparatus of testing an asynchronous transfer mode (ATM), and a method thereof. In particular, the present invention relates to an apparatus of testing an ATM network and a method thereof, which generates an ATM cell, transmits the cell, and verifies an error on the basis of the received ATM cell.
2.Description of the Related Art
In general, a radio network controller (RNC) in an IMT-2000 system is based on an asynchronous transfer mode (ATM) for connecting its components. Especially, an ATM cell is transmitted through an ATM switch inside of the radio network controller.
An ATM network is beneficial in many ways. For one thing, since the ATM network transmits and switches all information on every user in a packet form with a lixcd length, called a 'cell', it is capable of providing a variety of services ranging from a low speed to a high speed in a single network, and facilitates to provide a new service. Moreover, through a statistical multiplexing, the ATM network can readily manage burst traffic, in other words, an enormous amount of irafllc that changes to a great extent on a time basis. However, if the burst traffic flows in the ATM network simultaneously, it is always possible that the network might fall into a congestion state and not be able to meet the quality of service (QOS) standards.
Iherelore, the first thing to be done in order to prevent the congestion state of
the network and to utilize the network resources more efficiently is having a comprehensive or thorough understanding on the performance of the ATM system for operating a node function. That is to say, before actually installing an ATM network for the subscriber sevices, it is very important to calculate a total capacity of the ATM network that can provide services, by actually measuring and checking the capacity of the ATM exchange system.
To meet the requirement described above, an apparatus of testing an ATM system is required to develop a new ATM system and to test whether the ATM system is being property operated or not.
Unfortunately however, the traditional apparatus of testing the ATM system is too expensive in general, and a special and highly trained complicated technique is required to operate the apparatus, which consequently decreased the work efficiency to a great extent.
In addition, the previous ATM system has a different transfer speed for the ATM cell, depending on the mode, such as synchronous transfer mode (STM)-l mode, El mode and an optic mode. Thus it was not easy to match the previous apparatus of testing the ATM system with a variety of modes, and the test itself could not be carried out for the individual mode, respectively.
SUMMARY OF THE INVENTION
As an attempt to solve the problems, it is, therefore, an object of the present invention to provide an apparatus of testing an ATM network and a method thereof, for generating and transmitting an ATM cell, and for verifying the ATM's perfomance by verifying the ATM cell received.
Another object of the present invention is to provide an apparatus of testing an
ATM network and a method thereof, for conducting a test on external transfer modes with different transfer speeds with one another.
To achieve the above objects, a preferred embodiment of the present invention provides the apparatus of testing the ATM network, which includes: an input/output means for input/output predetermined information and verification information; a cell generation means for generating and outputting an ATM transmit cell on the basis of the predetermined information; at least one of matching means for matching the ATM transmit cell and an ATM receive cell, respectively; and a cell verification means for detecting the verification information from the ATM receive cell.
According to the ATM network test apparatus, the predetermined information can include matching information, cell data, transmission pattern, traffic amount, and transmission start/stop information.
Preferably, the ATM transmit cell can be inputted in one of the matching means in accordance with the matching information.
In addition, the transfer speed of the ATM cell is determined on the basis of the matching information, the transmission pattern and the traffic amount.
The verification information preferably includes the number of the ATM receive cells, the number of error cells received, information on the error cells received, and information on the physical layer enor.
According to the ATM network apparatus of testing the present invention, the cell verification means calls an inquired ATM cell from at least one of the matching means, and detects a header error from the inquired ATM cell, and detects a Start Of Call (SOC) error.
Further, the cell verification means of the ATM network test apparatus according to the present invention can detect an enor by comparing the ATM transmit
cell and the ATM receive cell.
Another aspect of the present invention provides a test apparatus an ATM network, which includes: a cell generation means for converting cell data into an ATM transmit cell; a plurality of a first storage means for temporarily storing predetermined information in order to generate the ATM transmit cell; a cell verification means for detecting verification information from an ATM receive cell; and a plurality of a second storage means for temporarily storing the verification information.
In accordance with the ATM network test apparatus described above, the format conversion can be conducted by inserting control information into the cell data.
Still another preferred embodiment of the present invention provides a method for testing an ATM network, which includes the steps of: inquiring cell data in accordance with transmission start/stop information; converting the inquired cell data into an ATM transmit cell format, and transmitting the converted ATM cell; detecting error information based on an inputted ATM receive cell; and storing the detected error information.
According to the ATM network test method described above, the step of converting the inquired cell data into the ATM transmit cell and of transmitting the ATM cell further includes the steps of deciding a transfer speed of the ATM transmit cell on the basis of matching information, transmission pattern, and traffic amount; and generating a control signal to transmit the ATM cell.
In addition, the step of detecting the error information of the test method preferably includes the steps of calling an receiving ATM cell by inquiring whether the receiving ATM cell exists in a physical layer; and testing a header based on the ATM receive cell.
Statement of the invention:
An apparatus of testing an ATM network, comprising: an input/output means *:,
inputting and outputting a predetermined information and a verification
information;
a cell generating means for generating an ATM transmit cell and for outputting
the ATM cell based on the predetermined information;
A plurality of a first storage means for temporarily storing predetermined
information in order to generate the ATM transmit cell;
at least one of matching means for matching the ATM transmit cell with an ATM
received cell, respectively; and,
a cell verification means for detecting the verification information form the ATM
received cell.
a plurality of a second storage means for temporarily storing verification
information.
Brief Description of the Drawings:
These and other features of the present invention will be more readily understand by reading the following detailed description taken in conjunction will be accompanying drawing, in which:
Fig. 1 is a block diagram illustrating an apparatus of testing an ATM network n accordance with a preferred embodiment of the present invention;
Fig. 2 is a block diagram illustrating a cell generation and verification unt of the device which particularly suitable for the embodiment of fig. 1;
Fig. 3 is a block diagram illustrating a cell format generation unit which is particularly suitable for the embodiment of fig. 2; and
Fig. 4 is a flow chart explaining a test method of an ATM network in accord ing with another preferred embodiment of the present invention.
BRIEF DESCRIPTION OF THE DRAW INGS
These and other features of the present invention will he more readily understood by reading the following detailed description taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a block diagram illustrating an apparatus of testing An ATM network in accordance with a preferred embodiment of the present iinention;
Fig. 2 is a block diagram illustrating a cell generation and verification unit of the device which particularly suitable for the embodiment of Fig. 1;
Fig. 3 is a block diagram illustrating a cell formal generation unit which is particularly suitable for the embodiment of Fig. 2; and
Fig. 4 is a flow chart explaining a test method of an ATM network in accordance with another preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Where possible , The same refrence nubers will be used thoughout the drawings to refer to the same or like parts.
Fig. 1 is a block diagram of an apparatus of testing an ATM network in accordance with the present iinention. With reference to Fig. 1. the apparatus of testing the ATM network includes a processor matching unit 100. a cell generation and verification unit 200, and a physical matching unit 300. The processor matching unit 100 stores information necessary for ATM cell generation (i.e., predetermined information) in the eel! generation and verification unit 200. Preferably.; the processor matching unit 100 includes a processor for leading verification information delected
from an receiving ATM cell that has been outputted from the cell generation and verification unit 200, and a peripheral unit. Here, the predetermined information includes matching data, cell data, information on a transmission pattern and traffic amount, transmission start/stop information and so forth. Also, the transmission start/stop information is used for determining whether the ATM cell is repeatedly transmitted or not.
Preferably, the verification information includes the number of ATM receive cells, the number of error cells received, information on the error cells received, and information on the physical layer error.
The processor matching unit 100 inputs the predetermined information, which is inputted by an operator, into the cell generation and verification unit 200 by connecting the cell generation and verification unit 200, and an external terminal including a PC,, and at the same time, it sends out the verification information to the external terminal device for the operator to see the information. In the light of that, the processor matching unit 100 is an input/output interface because it gives and takes the data by connecting the external terminal device and the cell generation and verification unit 200.
The physical matching unit 300 is served as a means for matching physically the cell generation and verification unit 200 with the outside, the unit transmitting the generated ATM cell from the cell generation and verification unit 200 and sending the ATM cell received from the outside to the cell generation and verification unit 200. The physical matching unit 300 includes a matching circuit for matching several different modes with a different transfer speed from one another, respectively, wherein the modes includes, for example, a synchronous transfer mode (STM) - 1 mode, an El mode and an optic mode. In addition, the three physical layer matching circuits are
matched in the physical matching unit 300 as a parallel data or bus. However, only one matching circuit designated in the processor matching unit 100 performs the actual operation of the matching unit. In this way, each matching circuit plays an important role for the ATM cell generated from the cell generation and verification unit 200 to be transmitted to the outside through each mode to be tested.
The cell generation and verification unit 200 is now explained in detail with reference to Fig. 2. Fig. 2 is a block diagram of the cell generation and verification unit which is particularly suitable for the embodiment in Fig. 1. Referring to Fig. 2, the cell generation and verification unit 200 includes a cell fonnat generation unit 280, a receiving cell verification unit 290, and a plurality of storage units for storing the predetermined information and the verification information.
Again, the storage unit for storing the predetermined information includes a cell data register 210, a physical matching register 220. and a transmitting cell control register 230. On the other hand, the storage unit for storing the verification information includes a receiving cell counter 240, a receiving cell error counter, a receiving cell error register 260. and a physical layer error register 270.
The cell data register is used for saving cell data to be tested, and the physical matching register 220 is used for selecting physical matching. In addition, the transmitting cell control register 230 is used for saving transmission start/stop information, traffic amount information and transmission pattern information. Usually, the operator who hosts the test inputs the information listed above into each register, i.e., the cell data register 210, the physical matching register 220. and the transmitting cell control register 230. The information inputted by the operator is then saved in each register via the processor matching unit 100.
Here, the receiving cell counter 240 is used for counting and saving the number

of the 53-byte ATM cells to be inputted in the receiving cell verification unit 290, while the receiving cell error counter 250 is used for counting and saving the number of the ATM cells with an error among the inputted 53-byte ATM cells. Moreover, the receiving cell error register 260 is used for saving error information detected from the ATM cell, and the physical layer error register 270 is used for saving error information detected from the physical layer. The error infonnation saved in the receiving cell error register 260 can include header error, SOC error and so forth.
The cell format generation unit 280, as shown Fig. 3, includes a cell data inquiry unit 281, a transmit cell control unit 282, a transmitting speed control unit 283, a cell data generation state machine 284, and a physically layer matching unit 285.
The cell data inquiry unit 281, under the start command of the transmission start/stop infonnation saved in the transmitting cell control register 230, inquires whether the cell data exists for generating the ATM cell, through the cell data register 210. In addition, if cell data is saved in the cell data register 210, the cell data inquiry unit 281 calls the cell data and sends it out to the cell data generation state machine 284. Under the transmission pattern command saved in the transmitting cell control register 230, the transmit cell control unit 282 modulates an ATM cell's transmission pattern that has been generated from the cell data generation state machine 284. Further, the transmit cell control unit 282, on the basis of the transmit start/stop information, controls transmission start/stop for the ATM cell.
The transmitting speed control unit 283 detennines a transfer speed of the ATM
cell based on the transmit start/stop infonnation, traffic amount infonnation and
transmission pattern infonnation. Therefore, the ATM cells generated from the cell
data generation state machine 284 are transmitted in a brief period of time at the transfer
speed set up by the transmitting speed control unit 283, which consequently causes
burst traffic. The ATM cells in the burst traffic situation are then used for testing the ATM network. The cell data generation state machine 284 can convert the inquired cell data from the cell data inquire unit 281 into the ATM cell. Here, the format conversion means converting the cell data into 53-byte cells by inserting control infonnation in the cell data. The cell data generation state machine 284, on the other hand, can output the converted ATM cell to the physical layer matching unit 285.
When the ATM cell is inputted into the cell data generation state machine 284, the physical layer matching unit 285 inquires the physical matching register 229 and outputs the ATM cell to a corresponding matching circuit to the selected matching mode. At this time, the physical layer matching unit 285 outputs a SOC signal, an Enable signal and a Clock signal, simultaneously.
Referring again to Fig. 2, the receiving cell verification unit 290 inquires whether a receiving ATM cell exists in the physical layer. If it turns out that the receiving ATM cell exists in the physical layer, the receiving cell verification unit 290 calls the receiving ATM cell in. When the receiving cell verification unit 290 calls in the ATM receive cell, a SOC error test can be carried out to find out or detect if the SOC occurred or not. Moreover, the receiving cell verification unit 290 tests the ATM cell if there exists a header error therein through a header error control (HEC), and saves the detected header error.
As already explained above, the verification information detected from the receiving cell verification unit 290 is saved in every counter and register, respectively.
Meanwhile, if the receiving cell verification unit 290 is set up in a loop test mode, it can also conduct error detection by comparing the received ATM cell with the ATM cell generated from the cell data state machine 284. At this time, the error detection can be also accomplished by using the control infonnation that is inserted in
the ATM cell generated from the cell data generation state machine 284.
Next, a verification method of an ATM cell using the ATM network apparatus of testing the present invention is explained with reference to Fig. 4.
Fig. 4 is a flow chart explaining a test method of an ATM network according to the present invention. Referring to Fig. 4, the operator inputs the predetermined information for generating ATM cells through the external terminal in advance. The inputted predetermined information is saved in each designated register by way of the processor matching unit 100 (S411). Here, the predetermined information preferably includes matching information, cell data, transmission pattern information, traffic amount information, and transmission start/stop information. Thus the matching information is saved in the physical matching register 220, and the cell data is saved in the cell data register 210. The other information, such as, the transmission pattern information, the traffic amount information and the transmission start/stop information are saved in the transmitting cell control register 230.
Under the command of the transmission start out of the transmission start/stop information, the cell data inquiry unit 281 inquires of the cell data register 210 whether the cell data exists, and sends out the inquired cell data to the cell data generation state machine 284 (S413).
The cell data generation state machine 284 then converts the inputted cell data into the ATM cell format, and outputs the converted ATM cell to the physical layer matching unit 285 (S415). At this point, the transmitting speed control unit 283, based on the transmission pattern information and the traffic information, determines an appropriate transfer speed for the ATM cell,
On the other hand, upon the receipt of an ATM cell from the cell data generation state machine 284, the physical layer matching unit 285 outputs the ATM

cell to a matching circuit of the physical matching unit 300 corresponding to the selection command of the matching information. The physical matching unit 300 matches the ATM cell with the corresponding matching mode, and outputs the cell (S417).
The receiving cell verification unit 290 confirms whether the receiving ATM cell exists by inquiring the physical layer, and if yes, calls the receiving ATM cell in (S419). At this time, the receiving ATM cell is read as 53-byte ATM cell, and is outputted to the receiving cell verification unit 290.
In addition, the receiving cell verification unit 290 tests the ATM receive cell, particularly the header of the ATM cell (S421) to detect any error therein (S423). The header test can be conducted through the header error control (HEC).
Just in case that the receiving ATM cell has the header error, the receiving cell verification unit 290 then saves the detected header error information into the cell error register 260 (S425).
Here, the receiving cell error counter 250 can add one more error, or increase the number of errors by 1, before it being saved. Moreover, when the receiving ATM cell is inputted into the receiving cell verification unit 290, it also increases the number of receive cells to be saved by 1.
In the meantime, when the receiving ATM cell is inputted, the receiving cell verification unit 290 can detect any error therein by conducting the SOC test.
As previously explained, the verification information saved in the counter or the register, it having been detected from the receiving cell verification unit 290, is provided to the operator, and used for verifying the capacity and function of the ATM network to be tested.
In conclusion, the apparatus of testing the ATM network of the present

invention is very effective in testing the ATM network's capacity, since it has a simple hardware logic configuration, and performs the ATM cell generation and verification process based on the predetermined information.
In addition, the ATM network apparatus of testing the present invention can be applied to the ATM network currently being used as well as the ATM network under development.
Finally, since the ATM network apparatus of testing the present invention is equipped with a variety of matching circuits, it is easily applied to totally different mating modes.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.




We Claim:

1. An apparatus of testing an ATM network, comprising:
an input/output means for inputting and outputting a predetermined information and a verification information;
a cell generating means for generating an ATM transmit cell and for outputting the ATM cell based on the predetermined information:
A plurality of a first storage means for temporarily storing predetermined information in order to generate the ATM transmit cell
at least one of matching means for matching the ATM transmit cell wr~h ATM received cell, respectively; and, a cell verification means for detecting the verification information form the ATM received cell.
a plurality of a second storage means for temporarily storing verification information.

2. The test apparatus as claimed in claim 1 wherein the predetermined information has a matching information traffic data information, a cell date transmission pattern, a traffic amount and a transmission start/stop information.

3. The test apparatus as claimed in claim 1. wherein the ATM transmit cell inputted in one of the matching means in accordance with the matching information.

4. The test apparatus as claimed in claim 1, wherein the transmission of th~ ATM cell is determined depending on the transmission start/stop information.

5. The test apparatus as claimed in claim 1, wherein a transfer speed oi the ATM cell is decided on the basis of the matching information, the transmission pattern and the traffic amount.

6. The test apparatus as claimed in I wherein the verification information here number of ATM receive cells, a number of error cells receive, information ~ error cells received, and information on a physical layer error.

7. The test apparatus as claimed in claim 1, wherein ~he cell verification means calls in an inquired ATM cell from one of the matching means, and detech; header error from the inquired ATM cell.

8. The test apparatus as claimed in claim 1, wherein the cell verification means detects a Soc error.

9. The test apparatus as claimed in claim 1, wherein the cell verification means detects an error by comparing the ATM transmit cell and the ATM received cell.


10. The test apparatus as claimed in claim 1, wherein the cell generation means determines a transfer speed of the ATM transmit cell, on the basis of anrd amount information, a transmission pattern information, and a matching information.

11 . The test apparatus as claimed in claim 1, wherein the format corwersion is accomplished through inserting a control information into the cell data

12.The test apparatus as claimed in claim 1, wherein the cell verificarion detects a header error and a SOC error from the ATM receive cell.

13. The test method for the test apparatus having the steps of:
Inquiring cell data in accordance with a transmission start/stop information;
Converting the inquired cell data into an ATM transmit cell format. are transmitting the converted ATM cell;
Detecting error information based on an inputted ATM received cell; and storing the detected error information.

14. The test method as claimed in claim 13, wherein the step of convertion the inquired cell data into the ATM transmit cell and of transmitting the ATM cell having the steps of deciding a transfer speed of the ATM transmit cell on the basis of matching information, transmission pattern, and traffic amount are generating a control signal to transmit the ATM cell.

15. The test method as claimed in claim 13, wherein the step of detecting the error information is having the steps of calling an receiving ATM cell by
inquiring weather the receiving ATM cell exists in a physical layer: and to a header based on the ATM receive cell.

16. The test method as claimed in claim 13, wherein in case that the receivirt. ATM cell is called in, a SOC error is detected in the ATM cell.

17.The test method as herein substantially described and illustrated in the accompanying drawings with reference to the figures 1 to 4.

Documents:

1256-del-2001-abstract.pdf

1256-del-2001-claims.pdf

1256-del-2001-complete specification (granted).pdf

1256-del-2001-correspondence-po.pdf

1256-del-2001-description (complete).pdf

1256-del-2001-drawings.pdf

1256-del-2001-form-1.pdf

1256-del-2001-form-19.pdf

1256-del-2001-form-2.pdf

1256-del-2001-form-26.pdf

1256-del-2001-form-3.pdf

1256-del-2001-form-5.pdf


Patent Number 199534
Indian Patent Application Number 1256/DEL/2001
PG Journal Number 38/2008
Publication Date 19-Sep-2008
Grant Date 12-Jan-2007
Date of Filing 19-Dec-2001
Name of Patentee L.G. Electronics, Inc.
Applicant Address 20, Yoido-dong, Youngdungpo-gu, Seoul
Inventors:
# Inventor's Name Inventor's Address
1 KIM, Boo Soo Hogye-dong 984-15, Dongan-gu, Anyang-si, Gyunggi-do
PCT International Classification Number H04L12/28
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 81721/2000 2000-12-26 Republic of Korea