Indian Patents
Title of Invention

"A MOSFET DEVICE"
Abstract The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; and a porous gate layer located on top of the plurality of atomic ridges.
Full Text A MOSFET DEVICE
CROSS-REFERENCE TO RELATED APPLICATIONS
This application makes reference to the following co-pending U.S. Patent Applications: U.S. Provisional Patent Application No. 60/153,088, filed September 9, 1999 and U.S. Patent Application No. 09/187,730, entitled "QUANTUM RIDGES AND TIPS'* filed November 9, 1998, the concurrently filed U.S. Patent Application entitled "STRONGLY TEXTURED ATOMIC RIDGE AND DOT FABRICATION", the concurrently filed U.S. Patent Application entitled "STRONGLY TEXTURED ATOMIC RIDGE AND MOSFETS, SENSORS, AND FILTERS", and the concurrently filed U.S. Patent Application entitled "STRONGLY TEXTURED ATOMIC RIDGES AND TIP ARRAYS", the entire disclosure and contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION Fietd of the invention
The present invention relates to MOSFET device, and generally to methods of formation of atomic ridges. The present invention also relates to MOSFET sensors, filters and nonostructures. The present invention also relates generally to movable multi-tip arrays.
Description of the Prior Art
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Metal-semiconductor growth systems that exhibit one-dimensional (1 -D) structures on the nanometer scale have lately been of interest, particularly those that form nanowires. Usually such structures have been grown by depositing metals on periodically stepped (or vicinal) surfaces. However, this step growth method has the disadvantage that the steps are not atomically straight, and that the deposited metal must preferentially nucleate at the step edges.
1-D structures also be grown using other types of surface morphologies other than steps. A number of high-index, "tilted" silicon surfaces possess unique morphologies not found on their low-index counterparts. For example, the recently discovered surface of Si(5 5 12) is oriented 30.5away from (001) towards (111) and forms a single-domain, planar reconstruction composed of row-like structures. It is known that group-Ill metals cause major faceting of this surface, see Baski et al, Surf. Sci. 423, L265-270 (1999). In contrast, the deposition and annealing of noble metals on Si(5 5 12) may lead to the formation of nanowire arrays.
A problem with many conventional nano-sized chemical sensors is that they do not have a high specificity for particular chemical species to be detected. For example, MOSFETs, or more precisely, ISFETs (Ion Sensitive Field Effect Transistors), may be provided with porous gates to allow the environmental gases to arrive at the gate/dielectric interface and modify the threshold voltage and current voltage character. In fact, these ISFETs are often quite sensitive to gaseous ambients of different types. However, the electrical behavior of the ISFET does not generally allow different gases to be distinguished from each other, especially when there are several gases present in the environment simultaneously.
Similar to the problems faced in producing high specificity nano-sized chemical sensors, there is also currently no good way to produce very high flow-through nano-sized reaction chambers or chemical filters having a high degree of chemical specificity. For example, people having an oxygen deficiency often carry around a bulky oxygen tank which must be refilled on a regular basis. A lightweight active filter that allowed
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the passage of oxygen and very little nitrogen and larger dust and pollen particles would be a significant adjunct to the quality of life for many people
The present methods of electron beam lithography being developed at great expense may reach an ultimate minimum dimension of about 35 nm, which is indeed a large improvement over the 180 nm now being produced in the IC business. One of the best developed methods in this family is called SCALPEL (Scattering with Angular Limitation Projection Electron-beam Lithography). This system requires magnetic lenses, very thin masks, difficult mask alignment tools, and is quite complex. It appears to have significant promise in high throughput lithography for minimum dimensions down to about 35 nm, but not for smaller dimensions. A simple contact mask for e-beam lithography producing dimensions in the range of 1 to 5 nm would be of major benefit for a wide range of applications.
Currently available movable multi-tip arrays include Ultrasharp calibration gratings having tip sizes of 10 nm and tip spacings of 1 to 10 urn. While such multi-tip arrays may be useful for purposes such as calibration gratings, if multi-tip arrays could be made having tips sizes and spacings 100 to 10,000 times smaller, such multi-tip arrays could be used for many more applications such as for use in lithography processes, chemical sensors, nano-circuits, DNA manipulation, and much more.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for forming regularly spaced atomic ridges on a silicon wafer with a variety of spacings (or pitch).
It is another object of the present invention to provide a method for forming regularly spaced Au and other metal nanowires, as well as either positive or negative lithographic etch masks, for forming a variety of useful structures on particular crystal surfaces of Si and other semiconductors.
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It is yet another object of the present invention to provide MOSFETs that may be used in producing sensors having a high degree of chemical specificity.
It is yet another object of the present invention to produce nano-sized reaction chambers having a high degree of chemical specificity.
It is yet another object of the present invention to produce nano-sized filters having a high degree of chemical specificity.
It is yet another object of the present invention to produce nano-sized openings in a contact lithographic mask and a shadow mask for charge and neutral particles.
According to first broad aspect of the present invention, there is provided a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges.
According to a second broad aspect of the present invention, there is provided a thin membrane comprising: a substrate; and a plurality of nanowindows in the substrate.
According to a third broad aspect of the present invention, there is provided a method for forming nanowindows in a substrate comprising the steps of: forming convex depressions having bottoms on a surface of a Si substrate; treating the bottoms of the convex depressions to form atomically flat regions; ion-implanting at least one element selected from the group of elements consisting of oxygen and nitrogen into the Si substrate to form a lower layer comprising Si, a middle layer comprising a Si-based insulating compound, and an upper layer comprising single crystalline Si; thinning the upper layer to a thickness of 5.0 to 50.0 nm; depositing nanowires comprised of a first metal on the atomically flat regions; and etching away portions of the substrate that are
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unprotected by the nanowires to form a plurality of nanowindows in the substrate, wherein the nanowindows have a pitch of 0.94 to 5.35 nm and window widths of about 0.2 to 5.0 nm.
According to fourth broad aspect of the present invention, there is provided a multi-tip array device comprising: a substrate; a multi-tip array of atomic tips on the substrate, the multi-tip array having a pitch of 0.94 to 5,4 nm between adjacent tips in at least one direction; and means for moving the substrate.
According to a fifth broad aspect of the present invention, there is provided an atomic claw comprising: a mounting block; a paddle having a multi-tip array thereon, the multi-tip array having a pitch of 0.94 to 5.35 nm between adjacent tips in at least one direction; and a cantilever connected to the paddle and the mounting block, wherein the cantilever allows the paddle to be moved in at least one arcuate direction.
Other objects and features of the present invention will be apparent from the following detailed description of the preferred embodiment.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described in conjunction with the accompanying figures, in which:
Figure 1 is a scanning tunneling microscopy (STM) image of the clean Si(5 5 12)-2xl reconstructed surface, in which a 2x1 unit cell is outlined and consists of one (7 7 17) subunit cell (wider) and one (337) subunit (narrower) and the main surface features include three pi-bonded chains per 2x 1 unit cell;
Figure 2 is an image of a Si(5 5 12) surface showing a disruption in the surface periodicity in which there is an extra (337) unit cell;
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Figure 3 illustrates a nanowire growth phase of Ag on Si(5 5 12) at low coverage ( -0.20 ML) and moderate annealing temperature (450 to 550°C), where the Ag rows are the bright, overlayer rows;
Figure 4 illustrates the Ag nanowire growth phase on Si(5 5 12), but in this case a disruption in the underlying Si periodicity results in a discontinuity in the overlayer Ag row;
Figure 5 illustrates a higher coverage, "sawtooth" phase of Ag growth on Si(5 5 12);
Figure 6 illustrates a higher-coverage, "stepped double row" phase of Ag growth onSi(5 5 12);
Figure 7 illustrates Au growth on Si(5 5 12) to form a (7 7 15) template for a nanowire array;
Figure 8 illustrates from left to right, an end-on view of Ag nanowires covered with a thin Au layer, a small cavity after dissolving the Ag in nitric acid through the porous Au, after dissolving the Si with an anisotropic wet etchant, and after a liftoff process and a deep dry etching step where a typical pitch between ridges and grooves is 5.35 run;
Figure 9 illustrates the final result of a negative etch mask process using the method of the present invention;
Figure 10 illustrates the final result of a positive etch resist process using the method of the present invention;
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Figure 11 illustrates a first embodiment of the MOSFET device in cross section of the present invention in simplified form;
Figure 12 illustrates a second embodiment of the MOSFET device of the present invention in simplified form;
Figure 13 illustrates an active membrane filter of the present invention in simplified form;
Figure 14 is a cross-sectional illustration of an c-bcam mask of the present invention
Figure 15 is a simplified cross-sectional illustration of a depression patterning step of one embodiment of the method of the present invention for forming a membrane;
Figure 16 is a simplified cross-sectional illustration of a crystal flattening step of one embodiment of the method of the present invention for forming a membrane;
Figure 17 is a simplified cross-sectional illustration of oxygen and nitrogen implantation step of one embodiment of the method of the present invention for forming a membrane;
Figure 18 is a simplified cross-sectional illustration of a layer thinning step of one embodiment of the method of the present invention for forming a membrane;
Figure 19 is a simplified cross-sectional illustration of a nanowire deposition step of one embodiment of the method of the present invention for forming a membrane;
Figure 20 is a simplified cross-sectional illustration of a nanowire thickening step of one embodiment of the method of the present invention for forming a membrane;
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Figure 21 is a simplified cross-sectional illustration of a copper covering layer step of one embodiment of the method of the present invention for forming a membrane;
Figure 22 is a simplified cross-sectional illustration of a nanowindow etching step of one embodiment of the method of the present invention for forming a membrane;
Figure 23 illustrates in simplified form a perspective drawing of a multi-tip array of the present invention;
Figure 24A is a simplified plan view in simplified form of a section of a multi-tip array of the present invention that includes artificial atoms and artificial diatomic molecules.
Figure 24B is a cross-sectional view of the section of the multi-tip array of Figure 24A;
Figure 25A is a simplified plan view in simplified form of a section of a multi-tip array of the present invention that includes inverse artificial atoms and artificial inverse diatomic molecules.
Figure 25B is a cross-sectional view of the section of the multi-tip array of Figure 25A; and
Figure 26 is a simplified perspective view of a MOSFET that includes a linear array of surface states at the oxide -Si interface of the present invention.
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
It is advantageous to define several terms before describing the invention. The following definitions are used throughout this application.
Definitions
Where the definition of terms departs from the commonly used meaning of the term, applicant intends to utilize the definitions provided below, unless specifically indicated.
For the purposes of the present invention, the term "artificial atom" refers to an atomic tip that differs in some significant way from the atomic tips surrounding it.
For the purposes of the present invention, the term "artificial molecule" refers to two or more artificial atoms that are close to each other and that are surrounded by normal atomic tips.
For the purpose of the present invention, the term "anti-tip" refers to a location in an array of atomic tips where a tip that would be part of a complete array of atomic tips is absent.
For the purposes of the present invention, the term "atomic ridge" refers to a ridge formed in the silicon wafer, primarily from an etching procedure following the growth of nanowires.
For the purposes of the present invention, the term "atomic tip" refers to a elevated region having widths of less than 5 nm in both lateral directions.
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For the purposes of the present invention, the term "complete array" refers to an array of atomic tips in which all of the atomic tips that form the regular pattern, such as a grid pattern, of the array are present.
For the purposes of the present invention, the term "elongated molecule" includes elongated molecules such as long chain molecules, carbon nanotubes, etc.
For the purposes of the present invention, the term "etch mask" refers to any material that resists or locally slows the wet or dry (plasma) etching process.
For the purposes of the present invention, the term "inverse artificial atom" refers to the region of a missing atomic tip in the midst of normal atomic tips.
For the purposes of the present invention, the term "inverse artificial molecule" refers to a regions where two or more closely spaced atomic tips are missing.
For the purposes of the present invention, the term "long chain molecule" refers to molecules having a length of at least 5 nm, but generally refers to much longer molecules or segments of very long molecules. The term long chain molecules includes DNA, RNA, polypeptides, etc.
For the purposes of the present invention, the term "Molecular Beam Epitaxy (MBE)" refers to the deposition of elements onto a substrate using evaporators in a UHV environment.
For the purposes of the present invention, the term "monolayer (ML)" refers to one atomic layer of metal on a surface of a given orientation.
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For the purposes of the present invention, the term "nanoborder" refers to one or more nanowires or nanoridges bordering a nanowindow.
For the purposes of the present invention, the term "nanogroovc" refers to the recessed region between two adjacent atomic ridges.
For the purposes of the present invention, the term "nanowindow" refers to a nanogrove that goes all the way through a membrane, and it may be an open window or may in some cases have a thin dielectric layer in the window.
For the purposes of the present invention, the term "nanowire" refers to an overlayer row resulting from the deposition of a metal on the silicon surface. Such a nanowire has a width of-1 to 4 nm, a length of 10 nm or longer, and a pitch of ~1 to 5 nm.
For the purposes of the present invention the term "pitch" refers to the separation between two adjacent nanowires, atomic ridges, atomic tips or grooves.
For the purposes of the present invention, the term "Reactive Ion Beam Etching (RIBE)" refers to one of the plasma or dry-etching methods that may be used to produce the grooves of this invention.
For the purposes of the present invention, the term "surfactant restructurant" refers to a single element or several elements that help restructure the surface of a substrate used in the formation of grooves, ridges, tips, oxide ridges, quantum wires, or other structures of the present invention.
For the purposes of the present invention, the term "Ultra High Vacuum (UHV)" refers to a pressure of less than l?10-9 Torr.
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Description
The recently discovered surface of Si(5 5 12) forms a single domain, planar reconstruction that is entirely composed of row-like structures, see A.A. Baski, S.C. Erwin, and L.J. Whitman, Science 269, 1556 (1995) and A.A. Baski, S.C. Erwin, and L.J. Whitman (1997). Surf. Set. 392, 69 (1997). These rows consist of structural units already known to exist on the low-index surfaces, such as pi-chains and tctramers, see R.M. Feenstra and J.A. Stroscio, Phys. Rev. Lett. 59, 2173 (1987). Unfortunately, group-Ill metals strongly interact with the Si(5 5 12) surface and induce large-scale faceting, see A.A. Baski and L.J. Whitman, J. Vac. Sci. Technol B 14, 992 (1996). However, recent scanning tunneling microscopy (STM) studies have shown that a noble metal such as Ag grows in an ordered manner on this surface, sec H.H. Song, K.M. Jones, and A.A. Baski,./. Vac. Sci. Technol. A 17, 1696 (1999).
The present invention provides a method for producing atomic ridges on a substrate comprising: depositing a first metal on a substrate; heating the substrate to form initial nanowires of the first metal on the substrate; depositing a second metal on the initial nanowires of the first metal to form thickened nanowires that are more resistant to etching than the initial nanowires; and etching the substrate to form atomic ridges separated by grooves having a pitch of 0.94 to 5.35 nm.
The present invention also provides a method for producing Au nanowires on a substrate comprising: depositing Au on a substrate; heating said substrate to form a plurality of Au nanowires on the substrate wherein at least two adjacent nanowires of the plurality of Au nanowires are at a pitch of 2.51 to 3.45 nm.
The process of the present invention preferably starts with a high temperature, on the order of 1100-1200°C, treatment of a special orientation wafer such as Si(5 5 12), Si(7 7 15), or Si(5 5 11) in an Ultra High Vacuum (UHV) system. The wafer is then cooled at a slow rate to near room temperature (RT), at which point a fraction of an atomic monolayer (ML) of an element such as Au, Ag, etc. is evaporated onto the
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wafer. The wafer is then heated to a specific temperature range, which depends on the element deposited, the thickness of the deposited element, and the substrate on which the element is deposited. As a result of the heat treatment, nanowires arc formed of the deposited element.
After the metal nanowires are formed on a Si wafer, additional treatments to the Si wafer are used to produce grooves in the unprotected Si between the metal nanowires, thereby producing atomic ridges. Depending on the application, the metal nanowires may be removed from the atomic ridges.
In one preferred embodiment, the additional treatment of the Si wafer includes thickening or protecting the thin metal nanowires to make the metal nanowires more etch-resistant during various conventional wet chemical or dry etching treatments. Once the metal nanowires have been thickened, the Si wafer is etched to produce grooves having a pitch of 0.94 to 5.35 nm.
A method of depositing Ag on a Si(5 5 12) surface suitable for use in the method of the present invention is described in Baski et al, J. Vac. and Tech. 17, 1696 (1999), the entire disclosure and contents of which is hereby incorporated by reference. The process of Baski et al starts with a clean single crystal wafer of Si(5 5 12). The wafer is then heated to 1150-1200°C in a UHV system to vaporize any native oxide and to allow the surface to restructure into the well-ordered structure characterized by a surface unit cell of 5.35 nm, see Figure 1. The wafer is then slowly cooled to room temperature, and very thin layer of only about 0.25 monolayers (ML) of Ag is evaporated from a tungsten filament onto the surface and the surface is annealed at a moderate temperature (450 to 550°C), see Fig. 3. The Ag atoms move around on the surface and form Ag nanowires of about 1.6 nm width on a pitch of 5.35 nm, namely with the spacing of the surface cell mentioned above. This process is similar to that for Au deposition on such a surface as described in U.S. Patent Application No. 09/187,730 filed November 9, 1998 and
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International Patent Application No. PCT/US98/23875 filed November 9, 1998, the entire contents and disclosure of which are hereby incorporated by reference.
Instead of Ag, Au may also be used to form other nanowire arrays with different pitches. The deposition of 0.04 to 0.12 ML Au on Si(5 5 12) and annealing to ~-800°C results in the formation of large (7 7 15) facet planes with interposed (113) steps, see Fig. 7. The (7 7 15) atomic ridges have a very regular spacing of 3.45 nm over large areas, unlike the situation with (5 5 12) atomic ridges which may have as many as 20% surface faults, one of which is shown in Figure 2. Therefore, Au deposited onto specially cut and precisely aligned (7 7 15) wafers will result in a very regular array of nanowires with a pitch of 3.45 nm. These regularly spaced nanogrooves may be used to create atomic ridges (or grooves) via possible subsequent oblique metal evaporation, and wet or dry etching of the Si substrate, as discussed in U.S. Patent Application No. 09/187,730, filed November 9, 1998, the entire disclosure and contents of which is hereby incorporated by reference.
In the method of the present invention, when Ag nanowires are deposited, preferably the Ag is deposited to a thickness of 0.15 to 2.5 ML on a Si substrate. In the method of the present invention, when Au nanowires are deposited, preferably the Au is deposited to a thickness of 0.04 to 1.0 ML on a Si substrate.
In these processes, a fraction of a monolayer of a surfactant element, such as Ga, Au, Ag, or other elements may also be added to the Si surface prior to metal deposition. The use of surfactants may enhance the surface diffusion of the deposited metal or the substrate atoms and modify the favored crystal planes and necessary temperature ranges.
On the Si(5 5 12) surface, there may be occasional surface faults that disrupt the regularity of the atomic ridges for -20% of the ridges, see Fig. 2. Occasionally, there are extra (3 3 7) segments of 1.6 nm width on the (5 5 12) surface, so the sequence may become: 5.4 nm, 5.4 nm, 5.4 nm, 7.0 nm, 5.4 nm, 5.4 nm, etc. Alternatively,
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occasionally there are missing (337) segments to produce a sequence: 5.4 nm, 5.4, 5.4 nm, 3.8 nm, 5.4 nm, 5.4 nm, etc. The sample mounting procedure may control this regularity, where purposeful mounting at tensile or compressive stress could control the density and type of defect. One method of controlling and even eliminating such stress involves using quartz wedges during the high temperature flashing process and/or at lower temperatures. At a particular low value of induced stress it should be possible to produce a wafer with a greatly reduced number of such surface faults.
In addition to occasional irregularities of the (5 5 12) pattern, there are sometimes small surface modulations of the crystal orientations on the Si wafer due to manufacturing issues. One method to minimize such modulations is to add concave or convex regions on the (5 5 12) or other (11X) wafers, as described in U.S. Patent Application No. 09/187,730, the entire disclosure and contents of which is hereby incorporated by reference.
One process to produce the locally concave dimples, and ultimately atomically flat regions, is to heat a spot on the wafer to a temperature of 800 to 975°C with a laser, other localized light or x-ray source, electron, or ion or neutral particle beam when the sample is in a UHV or in a clean low pressure active-gas chamber. The temperature is generally limited to -975 °C or lower in order to stay below the elastic limit of Si and to reduce the diffusion of the substrate atoms in neighboring regions. However, brief
pulse-heating at higher temperatures may also sometimes be used. If done in molecular
-8 oxygen at a pressure in the range of 10 Torr or in various active gas environments
such as Cl, Ar, Si2H6, or H, this process will result in local etching and the formation of large concave regions with atomically flat regions near their centers. For the important molecular O2 case with uniform wafer heating, see J. B. Harmon, et al, Phys. Rev. Lett. 81,4676(1998).
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A modification of the above procedure involves splitting the laser or other energy beams into multiple beams to form a regular submicrometer or larger spaced array. This splitting allows multiple atomically flat regions to be produced in precisely located regions on the wafer for subsequent device and integrated circuit processing. The various means for splitting the beam may include interferometric methods and physical obstructions (i.e., Si or other "screenwire shadow masks" interposed near the wafer in front of an intense large area beam).
The laser or other energy beams above may also be split into multiple beams in regularly spaced submicron or larger arrays by various means so that multiple atomically flat regions may be produced in precisely located regions of the wafer for subsequent device and integrated circuit processing. For example, for this invention, the atomic flatness in regions under all the gates of the MOSFETs should be under excellent control to give uniform behavior to the many individual MOSFETs of an integrated circuit. The various means to produce these regions would include well known interferometric methods. It would also include physical obstructions with Si or other "screenwire shadow masks" interposed near the wafer in front of an intense large area beam. It should be noted that the concave regions produced by such multiple beams gives a group of concave regions on a wafer with atomically flat bottoms quite similar to the dimples, produced by a different process, described in U.S. Patent Application No. 09/187,730, filed November 9, 1998, the entire disclosure and contents of which is hereby incorporated by reference.
Another method to minimize surface modulations is to cut the Si(llX) wafer off-axis in particular directions by ~0.1 to 5 degrees, thereby ensuring that the misalignment steps will be in the same general directions. In a MOSFET made on a (11X) wafer, the source-to-drain current may be arranged so that it flows parallel to the atomic ridges (i.e., [HO] direction), perpendicular to the atomic ridges, or in an arbitrarily chosen direction. The purposeful miscut angle should be greater than the largest misorientation angles of the original local modulations in crystal orientation so
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that all or most of the misalignment steps run in the same general direction. As Si wafer local flatness produced by standard chemical-mechanical polishing or other procedures improves, and as the precision of the original orientation angle improves, the need for off-axis cuts of the Si wafer diminishes.
When Ag is the metal deposited as nanowires, the resulting Ag nanowires may be used as etch masks for etching Si, either with wet chemistry or dry etching. Preferably, the Ag nanowires are thickened by depositing more Ag or Au, or other materials to make the nanowires a more robust etch mask. The resulting nanowire width should not exceed the pitch of the nanowire array. Fig. 8 illustrates Ag nanowires covered with a thin Au layer which allows the Ag nanowires to be taken out of the UHV system into normal room air without oxidation of the thin Ag. The thin Au (or also Cu) layer of about 5 to 20 nm thickness is porous enough to allow wet chemical etchants like nitric acid to penetrate to the underlying Ag nanowires and dissolve the Ag (and not the Au) and form a small cavity. If ultrasonic agitation is added during this process, the Au directly above the Ag layer may often be lifted off to provide openings in the thicker Au layer that may be used to etch the Si in subsequent wet or dry etching processes. This results in very narrow nanogrooves that are in the same position as the original Ag nanowires, thereby acting as a positive etch-resist process.
By contrast, Fig. 9 illustrates how to produce a negative etch mask using the method of the present invention. In this case, Au (or more Ag) is evaporated onto the Si wafer containing the single ML nanowires of Ag at a temperature of 200 to 350°C. In this range of temperature, the additional Au or Ag will not stick to the clean Si between the Ag stripes, but it will adhere to the original Ag nanowires and they become thicker and much more robust. Then when the Si is either wet or dry etched, the nanogrooves are formed in regions where there is no metal etch mask, thereby acting as a negative etch-resist process. Finally, Fig. 10, which is discussed above, illustrates a method for producing a positive etch mask using the method of the present invention. Thus, either a "positive" or a "negative" atomic lithography may result from using the methods of the present invention. A Cu or gold-coating deposited on top of the Ag nanowires allows
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UHV samples to be taken out into normal room ambient temperature for subsequent processing.
It will be appreciated that we have not specifically discussed nanodots in this application, but almost all of the ridge producing processes discussed here have analogues in the world of quantum dots. This will be apparent from a careful reading of the atomic "cookie cutter" technique for producing regularly spaced dot arrays from metal ridges and wires, as discussed in U.S. Patent Application No. 09/187,730, filed November 9, 1998, the entire disclosure and contents of which is hereby incorporated by reference.
Molecules of a particular size may move into and out of gap under a "suspended" metal gate shown in Figure 11. Different oxide modulation widths, depths, and perhaps surface treatments of these gaps, along with different metal gate porosities obtaining using different oblique angle evaporation, along with nanotubes and other long molecules or segments thereof, may give a very large amount of specificity to the MOSFET device character for gaseous and liquid detection. Good specificity is very important for chemical sensors, and the concept of gangs of different length MOSFETs having different width, depth and gap characteristics may be used to analyze complex mixtures of chemicals. A MOSFET of the present invention includes a porous metal gate with pores that have similar but not identical diameters. The pore size may be controlled over a wide range by varying the angle of obliquity of the evaporant, the temperature of the receiving substrate, the rate of evaporation, and the rate of rotation of the substrate during the deposition process. See K. Robbie, et al, J. Vac. Sci. Tech. B, 16(3), 1115-1122 (1998) for experimental data on the porosity of thin films evaporated under a wide range of conditions.
A gated single walled nanotube (SWNT) of carbon supported on an SiO2 substrate has been shown to be extremely sensitive to NH3 and NO2 gas molecules, see Kong et al. "Nanotube molecular nanowires as chemical sensors", in Science, 287, 622-625 (2000), the entire disclosure and contents of which is hereby incorporated by
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reference. Two and three magnitude changes in the current of a MOSFET-like structure were obtained when the nanotube was exposed to these gases while using different "gate voltages" obtained by biasing the substrate relative to the source and drain metal nanowircs on the covering oxide. The present invention provides a ridged or dot MOSFET having a suspended porous gate which may have the effective work function of the gate modified with gas molecules or with SWNTs stretched out by the millions in the undulations of the oxide.
The atomic ridges of the present invention may be formed by any appropriate process for forming atomic ridges described in the 1998 U.S. Patent Application No. 09/187,730 entitled "Quantum Ridges and Tips" and in the concurrently filed U.S. Patent Application entitled "Strongly Textured Atomic Ridge and Dot Fabrication". Both of these applications list Don L. Kendall as an inventor and the contents and disclosure of both these applications are hereby incorporated by reference.
In one preferred method for forming atomic ridges of the present invention, a simple oblique incidence evaporation of an etch resistant metal onto a pristine silicon surface under Ultra High Vacuum UHV conditions is conducted. The oblique incidence evaporation is then followed by a brief etching step (dry or wet). Other single crystal materials other than silicon may also be used for the substrate, for example, Ge, diamond, and the III-V compounds, as well as other compounds and even metal crystals.
For preparing atomic ridge products of the present invention, a substrate, preferably a semiconductor wafer, most preferably a circular Si (1 IX) wafer, is prepared by standard chem-mechanical polishing methods. When the substrate is a silicon wafer, the substrate is preferably heated in a UHV chamber at a pressure of about 10-10 Torr to a temperature of 1150° C for a brief period ("flashed") to remove any surface oxides and then cooled to below room temperature (around -20 to 25° C). The heating of the wafer may also be accomplished locally using a focused or beam-expanded laser passing through a quartz window in the molecular beam epitaxy (MBE)
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system. This heating process leaves the surface in a stable condition with slightly elevated parallel atomic ridges or misalignment steps having a pitch of 0.54 to 60 nm, most preferably 0.94 to 5.4 nm for surfaces of (1 1 2) to (5 5 12), respectively. The atomic ridges may have occasional atomic steps in them along their length due to the slight variations from perfect flatness of the wafer surface, but after each misalignment step, the ridges again establish themselves in the same direction. In addition, there may be occasional reconstruction faults in the surface, especially on the (5 5 12) surface. By contrast the (1 1 4), (7 7 15), and (5 5 11) surfaces are generally completely free of restructuring faults.
The substrate is then coated to form quantum wires on the ridges. A preferred technique for forming quantum wires is to use oblique evaporation at a small angle of 1
to 5 (or up to 30 degrees is effective in some cases) with an etch resistant (or in certain quantum wire applications "conductive") metal such as Au or Cr, or Al or Be so that the slightly higher (by about 3 A) ridges are coated preferentially with 5 to 30A of the metal relative to the intervening very shallow trough of the restructured clean surface. Preferably, the substrate is rotated during this process while maintaining the obliquity to improve the uniformity of coverage along the ridges. This rotation also helps to avoid bridging of the metal due to the "lateral needles" that form when evaporating at high obliquity. This rotation may be modified by blocking off the evaporating beam with a raised barrier on the sample holder or on the wafer itself along the direction of the atomic ridges so that the evaporation source never is in direct line with the atomic troughs.
An alternative method for forming atomic ridges for use in the present invention involves depositing nanowires of Ag or Au on a Si substrate. This process preferably starts with a high temperature, on the order of 1100-1200°C, treatment of a special orientation wafer such as Si(7 7 15), Si(5 5 11) or Si(5 5 12) in an Ultra High Vacuum (UHV) system. The wafer is then cooled at a slow rate to near room temperature (RT), at which point a fraction of an atomic monolayer, ML, of an element such as Au, Ag, Ga, etc. is evaporated onto the wafer. The wafer is then heated to a specific temperature
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range, depending on the element deposited, the thickness of the element to be deposited, and the substrate on which the element is deposited. As a result of the heat treatment, nanowires are formed of the deposited element.
After the metal nanowires are formed on an Si wafer, additional treatments to the Si wafer are used to produce grooves in the unprotected Si between the metal nanowires, thereby producing atomic ridges. Depending on the application, the metal nanowires may be removed from the atomic ridges.
In one preferred embodiment, the additional treatment of the Si wafer includes thickening or protecting the thin metal nanowires to make the metal nanowires more etch resistant during various conventional wet chemical or dry etching treatments. Once the metal nanowires have been thickened, the Si wafer is etched to produce grooves having a pitch of 0.94 to 5.35 nm.
A method of depositing Ag on a Si(5 5 12) surface suitable for use in the method of the present invention is described in Baski et al., J. Vac. and Tech. 17, 1696-1699 (1999), the entire disclosure and contents of which is hereby incorporated by reference. The process of Baski et al starts with a clean well-polished single crystal wafer of Si(5 5 12). The wafer is then heated to 1150-1200°C in a UHV system operating at a pressure of about 10-10 torr to vaporize or flash any native oxide and to allow the surface to restructure into the well-ordered structure characterized by a surface unit cell of 5.35 nm. The wafer is then slowly cooled to room temperature, and very thin layer of only about 0.25 monolayers (ML) of Ag is evaporated from a tungsten filament onto a wafer. The sample is then heated at a pressure of about 10'10 torr to about 450°C, at which temperature the Ag atoms move around on the surface and form Ag nanowires of about 1.6 nm width on a pitch of 5.35 nm, namely on the spacing of the surface cell mentioned above. This is similar to the process for the deposition of Au on such as surface described in U.S. Patent Application No. 09/187,730 filed November 9, 1999, the entire contents and disclosure of which is hereby incorporated by reference.
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In the method of the present invention, when Ag nanowires are deposited, preferably the Ag is deposited to a thickness of 0.15 to 2.5 ML on a Si substrate. In the method of the present invention, when Au induced restructuring is desired, preferably the Au is deposited to a thickness of 0.04 to 1.0 ML on a Si substrate.
When silver is the metal deposited as nanowires, the deposited silver nanowires may be used as etch masks for etching Si, either with wet chemistry or dry etching. Preferably, the Ag nanowires are thickened by depositing more Ag or Au, or other materials to make the nanowires more robust etch mask. When the Ag nanowires are thickened with Ag, the resulting thickened nanowires preferably have a thickness of about 3 to 5 ML. When the Ag nanowires are thickened with Au, the resulting thickened nanowires preferably also have a thickness of about 3 to 5 ML, although thicknesses up to at least 20 ML are possible for both Au and Ag thickening using oblique evaporation along with a rotating substrate. A Cu or Au-coating completely covering the Ag nanowires allows UHV samples to be taken out into normal room ambient temperature for subsequent processing.
Without pre-stressing of the substrate on which Ag is deposited, there may be occasional surface faults that disrupt the regularity of the atomic ridges for about 20% of the ridges. Occasionally there are extra (3 3 7) segments of 1.6 run width on the (5 5 12) structure, so the sequence may become something like: 5.4 nm, 5.4 nm, 5.4 nm, 5.4 nm, 5.4 nm, 7.0 nm, 5.4 nm, 5.4 nm, etc. Alternatively, occasionally there are missing 1.6 nm segment so that the sequence may become something like : 5.4 nm, 5.4 nm, 5.4 nm, 5.4 nm, 5.4 nm, 3.8 nm, 5.4 nm, 5.4 nm, etc. However, typically, a sample either has all extra 1.6 nm faults, or it has all missing 1.6 nm segments. This is highly suggestive that mounting samples under compressive stress, or alternatively, tensile stress, during the passage of heating current to raise the samples to 1100 to 1200°C may remove these faults or control the density of these faults.
Depending on the application, the faults in the Si wafer may be controlled or removed using compression or tension. For example, the surface faults may provide controlled disruption of the Bragg-Law reflections, which provides plateaus that may be
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desirable in the production of MOSFETs. For other applications, very light compression or tension may be applied to the Si wafer, to eliminate surface faults completely to get large regions of 5.4 run sequences. One method of controlling such tension or stress involves using quartz wedges during the high temperature flashing process and/or at lower temperatures. Another way to provide a stress-free Si(5 5 12) surface is to float an Si wafer on a molten tin cushion during an MBE/UHV treatment.
The problem of small modulations on the surface of the Si wafer may be addressed in one of at least two ways. One way of solving the problem of small surface modulations is to add concave or convex regions on the (5 5 12) or other (1 1 X) wafers, as described in U.S. Patent Application No. 09/187,730, the entire disclosure and contents of which is hereby incorporated by reference.
However, the step of forming concave or convex regions may be avoided for many applications by cutting and polishing the Si(l 1 X) wafer off-axis in particular directions by about 0.5 to 4 degrees. Preferably the angle chosen is larger than the largest local Si wafer undulation angles, thereby ensuring that the misalignment steps will be in the same general directions, though not very regularly spaced nor straight because of the undulations. As Si wafer local flatness improves and as the precision of the original orientation angle improves, the need for off-axis cuts of the Si wafer diminishes.
It should also be noted that purposeful misalignment by less than 0.5 degrees, down to about 0.1 degrees, may also be useful in some applications, since this will result in single monolayer steps. Single monolayer steps may provide greatly different kinetics, compared to the double steps of wafer misorientations greater than about 1.0 degrees, during various processing steps. Crystal cleavage on a perfect crystal plane may be used to eliminate these steps, but this does not occur except on the (111) or (1 1 0) planes, and doing so on large wafers may be difficult.
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An important additional process step may be taken after the original Si etch step of only a few nanometers depth, either using RIBE or wet etching. This additional process step involves an oblique evaporation on a rotating substrate in order to build up a thicker metal or dielectric etch mask of several monolayers. After the additional monolayers are deposited, a second RIBE or other dry etching step may be performed in order to produce significantly deeper grooves of 2.0 to 20.0 nm depth, or even much deeper when the evaporated film is much thicker. This oblique evaporation may also be done on the original Ag deposited surface or even on the surface of a Si(l 1 X) before it has been through the Ag deposition process. However, the original surface topology of 0.2 to 0.3 nm, without the Ag, is quite shallow, and a preferred method is to increase the topology somewhat before the oblique evaporation step. These thicker grooves allow a much wider range of applications.
A fraction of a monolayer (ML) of an element like Ga, a surfactant-restructurant may be applied to the surface of the Si wafer prior to deposition of metal atomic strips to encourage elements such as Au or Ag deposited on the Si wafer to rapidly move to the desired atomic ridge positions.
Depositing a little less than one monolayer of Ga on a (1 1 2) Si wafer may force the Si wafer to favor the (1 1 2) facet formation after a 500°C treatment rather than a mixture of (3 3 7) and (1 1 1) sawtooth facets that are typically observed on a clean (1 1 2) surface. A (1 12) structure generally provides the smallest pitch in the (1 1 X) family in which the nanogroove walls are physically robust. Such reconstructions are described in Baski et al., "The structure of Si(l 1 2)-Ga(Nxl) reconstructions", Surf. Sci. 423, L265-270 (1999), the entire contents and disclosure of which is hereby incorporated by reference.
Using 0.04 to 0.12 ML of Au on slightly irregular (5 5 12) shows that Si (5 5 12) surface restructures to many (7 7 15) facets with interposed (1 1 3) steps after heating the wafer at about 800°C. The (7 7 15) atomic ridges have a very regular spacing of 3.45 nm when the Au is present. The situation with (7 7 15) atomic ridges is unlike the situation with (5 5 12) atomic ridges which may as have as many as 20% surface faults.
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Therefore, precisely aligned (7 7 15) wafers may be produced by Si manufacturing processes and then an 8000C Au treatment may be applied to obtain large areas of well structured material with very regular spacing of 3.45 nm. To utilize this regular spacing to produce regularly spaced nanogrooves of 3.45 nm pitch may be accomplished by using subsequent oblique evaporation, an electrochemical process, etc. of a metal or other etch mask and a dry or wet etch process to produce the grooves. The above-described restructuring process involves only a single impurity.
Small amounts of either Ga, or even Hg or Sn, used in conjunction with Ag, Au, or Al may also be useful as surfactants. The use of these small quantities of surfactants may lower or broaden the useful heat treatment range, and may help heal irregularities.
An additional aspect of using surfactants like Au at 800°C or Ga at 500°C, or perhaps Hg at a much lower temperature is to clean or restructure a surface prior to an MHR process at a similar or higher temperature. H2, O2 and cracked H2 may be used for removing nanowires of Ag, Au, Ga etc. from the atomic ridges so they may be used to form MOSFETS.
Nanowires of Ag, Au, Ga, etc. may also be removed form the atomic ridges by wet chemical cleaning using standard processes.
To form a MOSFET of the present invention, an upper dielectric or oxidized layer is formed in a substrate including atomic ridges by heating the wafer in an oxidizing or nitriding atmosphere.
After the dielectric layer is formed on the surface of the substrate, long chain molecules are deposited in nanogrooves between the atomic ridges by any of several methods. For example, the molecules may be suspended in a solvent and allowed to settle into the nanogrooves, perhaps in an electric field to stretch out the molecules in the general direction of the nanogrooves.
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To form a MOSFET, after the long chain molecules are placed in the nanogrooves, a porous gate layer comprising an obliquely evaporated metal like Al, Au, Cu, or W is deposited on the wafer. This metal gate layer rides across the top of the atomic ridges to form enclosed regions that contain the long chain molecules. Pores in the porous gate layer allow molecules to enter the MOSFET and be adsorbed or chemically reacted with the long chain molecules in the enclosed regions.
Fig. 11 illustrates a section of one embodiment of a MOSFET device 1102 of the present invention. MOSFET device 1102 includes a substrate 104 including an Si layer 1106, and SiO2 dielectric layer 1108, a long chain molecule 1110, a porous gate layer 1112 and an enclosed region 1114. Large pores 1116 allow large molecules 1118, typically 0.7 to 0.9 nm in average diameter to enter enclosed region 114 and be detected by their effect on the conductance of the long chain molecules 1110.
Fig. 12 illustrates a section of second embodiment of a MOSFET device 1202 of the present invention. MOSFET device 1202 includes a substrate 1204 including an Si layer 1206, and SiO2 dielectric layer 1208, a long chain molecule 1210, a porous gate layer 1212 and an enclosed region 1214. Small pores 1216 allow small molecules 1218, typically 0.3 to 0.6 nm in average diameter to enter enclosed region 1212 and be detected by their effect on the long chain molecules 1210.
A MOSFET of the type shown in either Fig. 11 or Fig. 12 is an excellent structure for sensing gases, as well as ions in liquids.
The spacing between atomic ridges may be 1.63 nm for (1 1 4) surfaces of Si, or it may be 5.4 nm for (5 5 12), as well as many other spacings for other (1 1 X) surfaces. The (5 5 12) surfaces provide larger groove widths, 1.6 to 3.2 nm depending on the depth of the undulations and the oxidation or deposition conditions, that are easily capable of containing the 1.6 to 1.8 nm diameter nanotubes. The oxide thickness may be adjusted to detect different size and shaped molecules.
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It is important to note that the MOSFET device of the present invention is similar to a standard MOSFET, except for the STAR ridges, the porous gate, and the deposition in the oxide grooves of nanotubes or other long chain molecules. The current may flow laterally from left to right across the inversion layers of Fig. 11, or it may be arranged to flow into the plane of Fig. 11 by changing the positions of the sources and drains.
The present invention also provides nano-sized reaction chambers for carrying out chemical reactions, such as the reactions that may take place in an active filter. For example, a thin segment of a (5 5 12) or other (1 1 X) Si wafer may be used to form water from even very dry air using the small mole fraction of about 5 x 10-6 of H2 gas in the atmosphere. This H2 gas is allowed to pass through a narrow nanowindow in the filter and O2 is allowed to pass, and perhaps dissociate due to a Pt catalyst on the walls of the filter, through a wider neighboring gap. Then the H2 and the excited oxygen atoms recombine on the downside of the filter to form water, as shown in Fig. 13. Nanowindows of different widths may be formed on Si(5 5 12) by near grazing incidence evaporation onto the tops of the pi-chain ridges that make up the (5 5 12) unit cell. These atomic ridges have spacings of 1.6, 1.6, and 2.2 nm within the 5.4 nm unit cells of the (5 5 12). These spacings provide two different spacings of the nanoridges of 1.6 and 2.2 nm. The grooves between these ridges are typically 0.6 smaller than the spacings of the nanoridges, so neighboring nanowindows are about 1.0 and 1.6 nm wide after the dry etching process, as shown in Figure 13. However, if narrower nanowindows are desired to encourage particular chemical reactions, the ridges may be oxidized and the resulting window widths will be about 0.4 and 1.0 nm wide. Many other options exist using these general principles.
The active filter shown in Fig. 13 may be used for oxygen enrichment of normal air. For example, if the O2 dissociates in a small groove perhaps due to the presence of a catalyst such as Pt on the walls of the grooves, as shown in Fig. 13 and the N2 in the air sample does not dissociate, then the O2 will effectively move much more efficiently through the filter since it is much smaller while it is passing through the structure, but it almost instantly recombines on the downside of the active filter. Such an active filter
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may be used in a mask for placing on an individual's face. Alternatively, the filter may be used in some other oxygen delivery system to replace the large oxygen tank typically used by individuals with oxygen deficits.
To prevent H2O vapor from plugging the active filter of the present invention, the formation of SiO2 may be inhibited by using an H-passivation process on the Si filter. One method of H-passivation is to soak the filter in a dilute solution of HF, preferably stabilized with F-compounds and/or by Pt or other catalyst(s).
The active filter may also be used to form H2 by passing normal water vapor form the atmosphere through the grooves and forming H2 and perhaps singlet excited oxygen on the down side using a suitable catalyst on the walls of the filter, as shown in Fig. 14. The H2 so formed may be used in a fuel cell without the need for any bulky H2 storage process. A preferred catalyst is Pt.
H2 may also be formed by the diffusion of singlet H+ ions from a dense plasma through the active filter of Figure 13 by the reaction H+ + H + + 2e -> H2. This reaction proceeds extremely rapidly, with an estimated turnover rate of about 2 x 105 molecules/sec inside a filter containing single channel wall thicknesses of about 0.3 nm (rather than the double channel wall thicknesses of 0.6 nm of the oxygen enriching filter.) This turnover rate is faster than most inorganic catalytic process by a factor of 1000 or so, and is within a factor of 5 of perhaps the fastest rates known, namely the hydgrogenase reactions for converting H+ ions into molecular H2 in the human body. This very fast turnover rate is due to the extremely thin vertical membranes on the (1 1 2) or other (1 1 X) surfaces in conjunction with the rapid diffusion of H in Si. A Pt or other catalyst on the surface of the vertical membranes may be used to ensure rapid recombination of H ions (protons) to form molecular hydrogen. Because two electrons must be extracted from the Si for every molecule of H2 that is formed, a very large current density of about 56 A/cm2 results from this process. This large current flow may in principle be drained off the membrane to ground as the plasma moves through the membrane.
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The present invention also provides a nanometer size electron beam litho-mask. Lithographic processes currently being developed, such as SCALPEL (scattering with angular limitation projection electron-beam lithography), may have an ultimate minimum dimension of 35 nm. In contrast, the litho-mask of the present invention may have a resolution of a small as 2 nm with a pitch at least as small as 5 nm. Fig. 14 illustrates a litho mask that may be used as a contact mask for e-beam lithography.
The litho masks or membranes of the present invention may be made in a series of steps. First, depression patterning is performed on the substrate, which preferably comprises Si. Light assisted chemical etch (LACE) process, an E-beam process, or Focused Ion Beam/Gas Assisted Etching (FIB/GAE), may be performed to produce convex regions at desired locations in the depression patterning process. Depression patterning may also be done using a chemical etching process along the lines described in U.S. Patent Application No. 09/187,730, the entire contents and disclosure of which is hereby incorporated by reference. Any of these localized etching process may be followed by a brief Chem-Mechanical Polish (CMP) touch up process, if desired. Fig. 15 illustrates a depression patterning step of one embodiment of the present invention.
The convex regions of the treated substrate may then be conditioned to be atomically flat (1 1 X) over tens of microns using Ar ion bombardment at 800 to 975°C for 1 to 5 minutes, or by allowing molecular oxygen to impinge on the surface at a pressure of about 4X10'8 torr at 800 to 975C for 1 to 5 minutes; see J. B. Harmon, et al, Phys. Rev. Lett. 81,4676-4681 (1998). Another way to condition the convex regions to make them atomically flat is to heat the substrate in ultrahigh vacuum (UHV) at about 1150 tol200°C for several hours; see s. Tanaka, et al, Appl. Phys. Lett. 69, 1235-1237 (1996). However, using a process having an operating temperature less than 975°C is preferred in most cases to avoid plastic deformation of Si. Fig. 16 illustrates such a conditioning (atomic flattening) step of one embodiment of the present invention.
In order to make a very thin e-beam mask or membrane, a low energy implantation of oxygen, nitrogen, or a mixture of oxygen and nitrogen is conducted on the substrate. This SIMNOX or SIMOX treatment is preferably conducted at an
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elevated temperature at a dose of about 10-l8/cm2. The substrate is then heated to a still higher temperature, such as 1050 to 1200°C to form the oxide, nitride, or oxy-nitride under the surface of the (1 1 X) Si, while leaving the top thin layer single crystalline, thereby forming a multi-layer wafer. One advantage of the "Separation by Implantation with Nitrogen and Oxygen" (SIMNOX) using silicon nitride or silicon oxynitride is that the underlying layer will be in tension to cause the ultimate ultra-thin mask to be stretched flat rather than be severely wrinkled as it would be with a silicon oxide (SIMOX) film. Fig. 17 illustrates the results of an N and O implantation step of one embodiment of the present invention. An early description of the so-called SIMOX or SIMNOX process for producing either an oxide or an oxynitride layer, respectively, under a single crystal Si layer is U. S. Patent No. 3,807,274 to Kendall et ai, the entire contents and disclosure of which is hereby incorporated by reference.
It should be noted that the SIMNOX or SIMOX treatment described above may be performed before depression patterning with similar results. In fact, the top of the dielectric film produced may be somewhat smoother if the implantation is done before depression patterning.
The single crystal layer produced by the implantation process described above will preferably have a thickness of about 0.1 to 0.5 um. To produce particularly thin grooves from this single crystal layer, the upper layer of Si must be thinned down to about 5.0 to 50.0 run. This thinning may be accomplished by oxidation in O2 at a temperature of 800 to 900°C followed by dipping of the multi-layer wafer in dilute HF or Buffered Oxide Etch (BOE). The thinning of the upper Si layer may also be accomplished by either wet or dry etching. However, oxidation and anodization processes are preferred to provide more uniform layer removal: Fig. 18- illustrates the results of a thinning step of one embodiment of the present invention.
The process of thinning the substrate may be performed prior to depression patterning if implantation of oxygen, nitrogen or a mixture thereof is conducted prior to depression patterning.
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Ag nanowires is then deposited under UHV on the (5 5 12) multi-layer wafer with 5.4 nm pitch in 1.6 nm wide parallel nanowires. The process of deposition preferably includes depositing Ag nanowires having a thickness of 0.25 ML to 2.5 ML at a temperature of 20°C up to 150°C. After deposition, a heat treatment step is performed in which the multi-layer wafer with the very thin layer of deposited Ag is heated at a temperature up to 450°C. Fig. 19 illustrates the results of a nanowire deposition step of one embodiment of the present invention, where the vertical scale has been increased slightly for clarity.
If a thicker more robust membrane or etch mask is required, a Au deposition of 0.20 to 5 ML or more may be applied at a temperature of 200 to 350°C. The Au will have a strong tendency to collect only at the position of the Ag strips due to Au's high surface diffusion coefficient on the Si surface, and, possibly due to the less-than-unity sticking coefficient for Au at 200 to 350°C. Fig. 20 illustrates this Au thickening step of one embodiment of the present invention.
If the multi-layer wafer of the present invention with deposited Ag nanowires or thickened Au/Ag nanowires is to be removed from the vacuum, a 5.0 to 50.0 nm thick layer of Cu may be evaporated, preferably at near normal incidence, on top of either the Ag nanowires or the thickened Au/Ag nanowires, respectively, without breaking the vacuum of the UHV system. Coating the nanowires with Cu allows for the samples to be removed form the UHV system and stored at room temperature for long periods of time without oxidation. Such a Cu coating also makes the nanowires resistant to airborne and liquid particle attachment. The Cu may be readily removed using dilute HC1 or other known solvents for Cu that will not attack the Au or Ag layers. Fig. 21 illustrates a Cu covering layer step of one embodiment of the present invention.
The resulting nanowire multi-layer wafers may then be dry etched, wet etched, chemically etched, or electrochemically etched to provide nanowindows in a thin membrane as shown in Fig. 22. In the embodiment shown in Fig. 22, the nanowindows are surrounded by Au-Ag-Si nanoborders. However, if the Ag nanowires are not coated with Au during processing, the nanoborders would be Ag-Si nanoborders.
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An alternative way to produce a thicker membrane for use as an etch-mask is to evaporate a metal or dielectric film at near-grazing incidence, which will provide an oblique evaporation thickening. If this is done on a rotating substrate that has an existing ridged surface morphology similar to that produced in the methods for forming a mask described above, a distinct columnar structure will be produced.
Vertical columns or ridges at least 10 times as high as the thickness of the Si wafer upon which the columns are deposited by oblique evaporation thickening may be obtained, as shown by Harmon, et al mentioned earlier. So, for example, a 3.4 nm high ridge on a Si (5 5 12) wafer will support a ridge or column of a deposited material at least 34.0 nm high. To remove irregularities, after the oblique evaporation thickening, the Si wafer with thickened ridges or columns may be dipped in a basic solution such as KOH:water or an organic base to straighten out any irregularities in the bombarded walls caused by warped etch masks in the bombarded walls.
Due to the thinness on the etch mask produced by the process of the present invention and the nanowindows therein, the etch mask and nanowindows of the present invention are preferably provided with etched honeycomb supports, such as those described in U.S. Patent No. 3,936,329 to Kendall et al., the entire disclosure and contents of which is hereby incorporated by reference.
The etch mask of the present invention may be used for a near-contact e-beam mask with very small patterns. The etch mask of the present invention may also be used for shadow masks for different angle evaporation or different types of energetic particles. In addition, the etch mask of the present invention may used for making MOSFETs with nanometer size features or for making SCALPEL masks more robust and/or more tolerant of angular deviations in an e-beam. The etch mask of the present invention may also be used to make a slightly diverging or converging e-beam into one or more parallel beams.
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A surprising and potentially useful feature of the thin membranes of the present invention is that they may be produced by this technology is that the membranes may be heated and cooled in incredibly short times. An estimate of the ultimate cooling time (and heating time) is given by the equation: = Cp d2 / K , where Cp is the specific
heat, d is the thickness, and K is the thermal conductivity of the membrane material. Using the known values of these parameters for Si, and assuming a thickness of 1.0 for simplicity, the ultimate cooling rate is calculated as 70 ns. For the more relevant thinnest membrane above used in this invention of 5 nm, the ultimate cooling rate is about 2X10" s, which is much faster than any switching time of a device in a typical IC. This means that a thin membrane is very sensitive to current and voltage variations while operating as an environmental or flow sensor.
The atomic dots and tips of the present invention may be formed by any appropriate process for forming atomic ridges described in U.S. Patent Application No. 09/187,730 entitled "Quantum Ridges and Tips", filed November 9, 1998, and in the concurrently filed U.S. Patent Application entitled "Strongly Textured Atomic Ridge and Dot Fabrication" and "Strongly Textured Atomic Ridge (STAR) and Dot (STARDOT) MOSFETs, Sensors, and Filters." All of these applications list Don L. Kendall as an inventor and the contents and disclosure of all of these applications are hereby incorporated by reference.
One preferred method of forming atomic tips of the present invention involves first forming atomic ridges. An appropriately oriented sample Of. Si, a (5 5 12) wafer, is prepared by standard chem-mechanical polishing methods. The wafer is placed in a
UHV chamber which is pumped to a vacuum of about 10-10 torr. The Si is then heated to 1150° C for a brief period ("flashed") to remove any surface oxides and then cooled to below room temperature (around -20°C). The heating of the wafer may also be accomplished locally using a focused or beam-expanded laser passing through a quartz window in the MBE machine. This leaves the surface in a stable condition with slightly elevated ridges separated in A by 16, 22, 16; 16, 22, 16, with this sequence of 54A width persisting over significant distances in regions where the heating occurs, and
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with the ridges also reaching across the whole length of the wafer. The ridges have occasional steps in them along their length due to the slight variations from perfect flatness of the wafer surface, but after each step, the ridges again establish themselves in the same direction. In addition, there are occasional surface faults in the (5 5 12) sequence that disrupt the regularity of the 16, 22, 16, or 54A unit cell, repetitions. These faults have a missing 16A section, with the fault then effectively having only a 38A section instead of a 54A sequence. By contrast, the other good ridge forming plane, the (1 1 4), has very regular 16.3A spacing with no surface faults.
Some low melting point metals must be deposited on the crystalline substrates at much lower temperatures (at least as low as 64°K. for Rb) to ensure that surface diffusion does not cause the metal to agglomerate and compromise the atomic ridge deposition of the Self Aligned Atomic Shadowing (SALAS) process. Still, other metals have measurable surface diffusion on semiconductor and other crystal surfaces near room temperature and are not good candidates for SALAS process except at very low substrate temperatures. However, a modest heat treatment after room temperature deposition in the UHV/MBE system may sometimes result in well formed ridges on one or more sets of the different ridge-type bonding sites on (1 IX) surfaces. For example, Au will diffuse to such sites at a temperature as low as 250°C, even though the eutectic temperature is 363°C. Subsequent heating to 700°C or higher may result in Vapor Liquid Solid (VLS) growth of nanostuds and nanowires at positions where a few atoms of Au exists at the Si surface. This may also be done using gas assisted epitaxy using Si2Hfi in the MBE machine.
The wafer is coated by oblique evaporation at a small angle of 1 to 5° (or up to 30° in some cases) with an etch resistant (or in certain nanowire applications "conductive") metal such as Au or Cr, or Al or Be so that the slightly higher (by about 3A) ridges are coated preferentially with 6 to 100A of the metal relative to the intervening depressions . The wafers are rotated during this process while maintaining the obliquity to improve the uniformity of coverage along the ridges. This rotation also helps to avoid bridging of the metal due to the "lateral needles" that form when evaporating at high obliquity. This rotation may be modified by blocking off the
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evaporating beam near the sample with a raised barrier along the direction of the atomic ridges so that the evaporation source never is in direct line with the troughs.
The wafers are then removed from the vacuum system and chemically etched a small amount in a solution of ethylene diamine (EDA) and water (54 vol % EDA) (or in a 50 wt% solution of KOH:water), so that about 10A of Si is removed from the depressions and the metal serves as an etch mask for the ridges. Since the tilted walls of the grooves are near the {111}, the lateral etching will be markedly slower than the vertical etch. The final result is a Strongly Textured Atomic Ridge (STAR) surface that undulates with an average "wavelength" of the peaks of the ridges of about 18A (the average of the 16+22+16 Å sequence on the (5 5 12)). If done on the (1 1 4), the spacing will be 16.3A. The Au or Cr (or Be or A1 in our first experiments) may then be removed in multiple aqua regia or KCN or other chemical removal steps if desired, for example before passing it on to a MOSFET fabrication cycle. For the MOSFET application the sample is handled like a normal wafer from this point forward, except that the oxidation steps are designed to maintain the STAR surface until the gate dielectric is formed. In a production process, the ridge producing process might also be done only in the gate oxide regions after many of the thick oxide and source and drain implantation and diffusion processes are completed.
The brief etch is designed to leave the metal atomic width "wires" intact along their length, while giving the surface a bit of surface relief which is useful for the next step. In either case, whether the etching step is performed or not, the next step is to use a second single crystal wafer to "cut" the metal "nanowires". Thus, the second wafer would also have regularly spaced atomic ridges, either a pristine freshly "flashed" surface like the one discussed above (before depositing the metal), or one that has been through the whole STAR groove process above. In the preferred method, the metal (or other material) is removed from the second "atomic-cookie-cutter" wafer before using it to cut the nanowires on the first wafer. Finally, the first slightly grooved wafer with the nanowires intact is immersed in a clean HF solution, or dilute HF (1 to 5%), or a dilute HF:ethanol acid bath.
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The second wafer may then be aligned perpendicular (or at some other specified angle to the first substrate )and pressed carefully onto the surface of the first wafer. (This is the "crossed wafer" process mentioned earlier). The wafers are allowed to contact each other without any significant lateral shifting by first contacting the flat bottom edges of the otherwise circular wafers and then letting gravity and surface tension close them like closing a book. The Van der Waals forces between the two surfaces then finishes the bonding process so that there is absolutely no lateral shifting of the wafers. To ensure that the nanowires are completely cut, a weight is then placed on the wafer sandwich while still immersed in the solution.
The wafers are then separated while still in the liquid with a thin wedge inserted into the edge of the wafer stack, again being careful that there is no lateral shifting during the separation (debonding) step. The metal coated bottom wafer is then dipped into DI water for 5 minutes and air dried face up to avoid disturbing the atomic dots that result from this treatment. The metal (or other material) need not be completely removed from the regions cut with the second wafer, but the few monolayers MLs of thickness of the nanowires has been compressed into monolayer thickness regions and squeezed sideways out of the previously continuous nanowires. This squeezing process is adequate to disrupt the conductivity along the atomic wires and make them into "atomic dots", each of which has dimensions of about 4A X 14A X 20A, where the last number is the approximate thickness of the film and the first 2 numbers are the width and length of the elongated "dots". The most useful thickness range for the q-wire applications is probably between 10 and 30A, since below 10A the conductivity will be very poor, and above 30A the narrow (say 3 to 6A width) wires will tend to delaminate from the substrate ridges. On the other hand, as a temporary etch mask, the useful thickness of the deposited material may be as small as 3 A, which is of the order of one monolayer ML thickness.
The above steps may also be done in N2, Ar, He, or other inactive gas, as well as in Ultra High Vacuum (UHV), etc., although the procedure in HF or the dilute HF, or HF and ethanol leaves the surface in an H-passivated state, which is an advantage for
38

some applications. The dilute HF mixtures are preferred when the atomic ridge metal is either Be or Al.
Thus, each dot in the above case contains about 56 atoms. This number of atoms in a given "dot" is determined from the atomic density of silicon, which is 0.05 atoms/A3. However, useful dot sizes will span the range from a single channel wall width (3.14A) with a single atom thickness (about 4 atoms) to a dot size of about 50X50X40 or 100,000A3 (about 5000 atoms). The latter may seem too large to be called an "atomic dot", but it is still several magnitudes smaller than many of the atomic dots reported in the recent literature. For example, 1000X1000X1000, or 1X1O9A3 (5X107 atoms) has been shown in proof of principle experiments to have atomic dot properties at temperatures near 1K. For room temperature operation, the width of the atomic dots are preferably smaller than about 50A, which would have a first allowed quantum well energy level of 0.05 eV, which is about 2kT at 300K. This magnitude gives the possibility that the thermal energy will not wash out the quantum effects produced by the quantum well. See K.K. Ng, "Complete Guide to Semiconductor Devices", McGraw Hill, NY, 1995 , pp. 227-228, for the relevant formula, which is En = n2K/mr* W2 where K includes well known physical constants and is 38 eVÅ2 when W is in A, n is an integer, with n = 1 for the lowest allowed energy level in the quantum well, and mr* is the conductivity effective mass of the carrier relative to the rest mass of the electron, which is 0.26 for the electron and 0.47 for the hole in silicon.
If the "cutting wafer" is the same orientation of the metal coated wafer in the groove, as in the present example, then the dots are separated by an average pitch of about 18A in both x and y directions on the (5 5 12), or a spacing of 16.3A on the (1 1 4). If the cutting wafer is the (1 1 0), the x-separation will be 5.43A, while the y-separation will be the same as before, namely an average of 18A or 16.3A for the (5 5 12) or the (1 1 4), respectively.
It should be appreciated that all the ranges above refer to Si and must be increased or decreased by up to 30% for other crystals unless otherwise indicated.
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The atomic tips of the present invention may also be formed by following the process described above for forming atomic tips, but skipping the light etching step. Such a process is described in U.S. Patent Application No. 09/187,730 entitled "Quantum Ridges and Tips", filed November 9, 1998, the entire contents and disclosure of which is hereby incorporated by reference.
When atomic tips are formed on an Si(5 5 12) substrate a the process such as those described above, the tip spacing of 5.4 nm in both the X and Y directions provides a theoretical atomic tip density of about 3 x 101 /cm2. When atomic tips arc formed on an Si(l 1 4) substrate using a process such as those described above, the tip spacing of 1.63 nm provides a theoretical atomic tip density of about 4 x 10l3/cm2. When atomic tips are formed on an Si(l 1 2) substrate using a process such as those described above, the tip spacing in both the X and Y directions provides a theoretical atomic tip density of about 1 x 1014/cm2. Based on these theoretical tip densities, multi-tip arrays (MTA) on the (5 5 12) that are 10 ??m x 10 urn in size can have about 3x10 atomic tips and may be readily produced by the method of the present invention. However, for special applications, still larger total tip counts may be produced using Si(l 1 4) and Si(l 1 2) substrates.
Fig. 23 illustrates an atomic claw 2302 of the present invention. Atomic claw 2302 includes a paddle 2304 including a multi-tip array 2306 that may be formed in the manner described above. Paddle 2304 is connected to a mounting block 2308 by a cantilever 2310 including two arms 2312 and 2314. Cantilever 2310 is preferably made of Si and is flexible enough so that paddle 2304 may be moved in an arc 2316 in the plane of paddle 2304. Cantilever 2310 is also sufficiently flexible to allow paddle 2304 to move back and forth in an arc 2318 in a plane perpendicular to the plane of paddle 2304. Paddle 2304 has a length a of preferably 1 to 20 ??m, and a width b of 1 to 20 ??m. When cantilever 2310 is made of Si, cantilever 2310 has thickness t of 5 to 500 nm and a length L of 50 to 100 ??m.
The atomic claw of the present invention may be designed to be mounted in devices for manipulating conventional AFM (atomic force microscopy) probes or a
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similar type of device, such as the devices for manipulating AFM probes described in U.S. Patent Nos. 5,959,957; 6,066,265; 6,100,524 the entire disclosure and contents of which arc hereby incorporated by reference. Furthermore, the mounting block and cantilever may be made using the conventional methods of forming mounting blocks and cantilevers for AFM probes such as the methods described in U.S. Patent Nos. 5,959,957; 6,066,265; 6,100,524 the entire disclosure and contents of which are hereby incorporated by reference. The paddle of the atomic claw of the present invention may be moved by conventional means such as capacitive, piezoelectric, temperature effects using diffused resistors, or other known methods.
A 10 urn x 10 ??m array size is consistent with a readily obtainable size of ultraflat regions produced by using depression patterning and conditioning of a Si substrate. In depression patterning, light assisted chemical etch (LACE) process, an E-beam process, or FIB/GAE, may be performed to produce convex regions at desired locations in the depression patterning process. Depression patterning may also be done using a chemical etching process along the lines described in U.S. Patent Application No. 09/187,730, filed November 9, 1998, the entire contents and disclosure of which is hereby incorporated by reference. Any of these localized etching process may be followed by a brief CMP touch up process, if desired.
The convex regions of the treated substrate may then be conditioned to be atomically flat (1 1 X) over tens of microns using Ar ion bombardment at 825 to 900°C for 1 to 5 minutes or allowing molecular oxygen to impinge on the surface at a pressure of 10"8 torr at 825 to 900°C for 1 to 5 minutes. Another way to condition the convex regions to make them atomically flat is to heat the substrate in ultrahigh vacuum (UHV) at about 1200DC for several hours, but using a processes having an operating temperature less than 975°C arc preferred in most cases to avoid plastic deformation of Si.
The neighboring flat regions in which the multi-tip arrays are formed do not have to be exactly in the same plane for the multi-tip arrays to be useful, since the multi-
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tip arrays may be easily adjusted to the position of the individual flat regions across a Si substrate. For particular applications, such as the fabrication of X-ray diffraction gratings, it may be possible to produce neighboring flat regions in exactly the same atomic plane using Low Energy Electron Microscopy, LEEM, regions while doing the ultraflat-region processing described above.
A multi-tip array of the present invention may have various tips removed by e-beam, FIB, FIB/GAE using conventional means such as an atomic-SCULPT tool to provide a multi-tip array with a specific pattern of tips. However, other methods may be employed to remove undesirable tips.
Figs. 24A and 24B illustrate a multi-tip array in a regular grid pattern in which undesirable tips have been removed. The single and double tips left behind on the multi-tip array form artificial H atoms and H2 molecules, respectively. By forming different patterns, more complex artificial molecules and a greater variety of artificial molecules may be produced using the method of the present invention. Different coatings or pretreatments on the tips may provide different characteristics. Different spacings between the individual groups of tips may also provide different characteristics. As shown in Fig. 24B, the tips may be n-type semiconductors and the substrate a p-typc semiconductor or the tips may be a p-type semiconductor and the substrate an n-type semiconductor. Alternatively, the tips and substrate may be the same type of semiconductor.
The present invention also encompasses multi-tip arrays that behave as inverse artificial molecules. Such inverse artificial molecules may be formed when only one, two or more tips are removed from a complete array of tips in a regular grid pattern as shown in Figs 25A and 25B. If a missing or anti-tip region is an acceptor type region, the missing region may take on a negative charge by extracting an electron from one or more neighboring tips to create a hole in the surrounding tip crystal. One example of such an acceptor region is where the tips are an n-type semiconductor and the substrate is a p-type semiconductor. As the hole in the surrounding tip crystal moves from tip to tip around the negatively charged anti-tip, an inverse artificial H-atom is formed. More
42

complex inverse-molecules may also be produced by removing two or more neighboring tips form the tip array which is also illustrated in Fig. 25A and Fig. 25B.
The artificial atoms, artificial molecules, inverse artificial atoms, and inverse artificial molecules described above may be used as sensors for various elements and molecules in gases or liquids. The artificial atoms, artificial molecules, inverse artificial atoms, and inverse artificial molecules will act as sensors for gases or liquids that modify the electron and hole orbits around the tips or anti-tips. The character of the original tips structures or the gas-exposed structures may be detected by such conventional methods such as measuring the localized luminescent character, by the measuring the electrical effect on closely neighboring MOSFETs, by monitoring the gas composition with a closely juxtaposed CCD-type detector, etc. An efficient way to setup a sensor employing artificial atoms, artificial molecules, inverse artificial atoms, and inverse artificial molecules would be to arrange columns of a given artificial atom type, artificial molecule type, inverse artificial atoms or inverse artificial molecules.
Multi-tip arrays of the present invention may be used in a variety of applications. For example, multi-tip arrays may be used to cut DNA or other long chain or elongated molecules such as carbon nanotubes into equal or different length segments. The long chain molecules may be cut into segments using an electric field to stretch the long chain molecules out and laying out the long chain molecules in Si or SiO2 templates to cut the DNA into segments of pre-determined lengths. The method for forming such Si or SiO2 templates is described in U.S. Patent Application No. 09/187,730, filed November 9, 1998, the entire contents and disclosure of which is hereby incorporated by reference. When carbon nanotubes are the elongated molecules being cut, the cut segments may be deposited into grooves of a substrate including atomic ridges and used to form MOSFETs as described in the concurrently filed U.S. Patent Application entitled "Strongly Textured Atomic Ridge (STAR) and Dot (STARDOT) MOSFETs, Sensors, and Filters," the entire disclosure and contents of which is hereby incorporated by reference.
The multi-tip arrays of the present invention may be used to arbitrarily SCULPT integrated circuits and devices on a scale of nanometers. And example of such a single
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electron type of device having many parallel ultra-thin metal or inversion or accumulation layers is shown in Fig. 26. Such a device employing Au or Ag atomic dots may be heated electrostatically to a temperature of 300°C to lift Au or Ag toward the gate metal interface with a ~Vg bias. This will allow adjustment of the threshold
voltage Vt by reducing the effective surface state density Qss. The latter process may
reduce the ~1015/cm2 values of Qss of the metal monolayers to much more tractable values of 10 to 10 /cm2 that will keep the inversion layers from overlapping.
A related method for adjusting Vt that does not necessarily involve SCULPT uses Ag nanowires of the type described in the concurrently filed U.S. Patent Application entitled "Strongly Textured Atomic Ridge and Dot Fabrication", the entire disclosure and contents of which is hereby incorporated by reference. A small amount of Au, on the order of 0.001 ML is deposited on the Ag nanowires. The Ag is removed by conventional wet chemistry (e. g., nitric acid) methods without removing the Au. The amount of remaining Au may be further controlled by additional cleaning or by heating to 300°C using an electric-field movement as described above to ensure overlap or near overlap of the individual ion induced inversion layer regions of a MOSFET. Fig. 26 illustrates such a MOSFET 2602 including an inversion layer 2604 underneath the +charged remaining Au ions at the interface. MOSFET 2602 also includes a p-type Si substrate 2606, a gate conductor 2608, a layer of dielectric material 2610, a source 2612 and a drain 2614. The ability to used a metallic template, such as the Au inversion layers shown in Fig. 26, to geometrically control the position and quantity of Qss in a MOSFET is a significant advance in the field of MOSFET design and provides an important new control parameter for IC chip manufacture. It is also possible to use the SCULPT process to tailor the spacing and density of the Ag or Au charged states. It is important to note that the induced inversion layers in Fig. 26 are aligned in straight lines and no STAR etching is involved.
The present invention will now be described by way of examples:
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EXAMPLE 1 (Figures 1, 2, and 4)
The reconstructed (5 5 12)-2xl surface consists of well-ordered rows oriented along [110], see Fig. 1. These rows incorporate structural units which have been
observed on other Si surfaces, including dimers, tetramers, and pi-bonded chains. The pi-chains were the brightest rows on the surface, where three such rows occur within each (5 5 12)-2xl unit cell (0.77 x 5.35 nm2). Another prominent defect structure found on this surface is the presence of disruptions in the (5 5 12) periodicity. The (5 5 12) unit cell may be divided into two subunits: (7 7 17) and (337), and the disruptions correspond to an extra or missing (337) unit cell, see Fig. 2. When Si(5 5 12) is used as a template in the growth of nanowires, the presence of disruptions in the periodic nature of this surface impacts the formation of such wires. Fig. 4 shows two Ag nanowires that appear to be misaligned. This misalignment is caused by the presence of an extra (337) unit cell. Therefore, these defect structures may affect the periodic structure of overlayer metal rows.
EXAMPLE 2 (Figure 3)
0.2 to 0.3 ML Ag was deposited onto a Si(5 5 12) wafer and annealed at 450 to 500 °C. Straight Ag nanowires form with a pitch of 5.35 nm, as shown in Fig. 3. These nanowires are 1.5 to 2 nm wide and have an average length of ~65 nm. Preferential nucleation of Ag on the (5 5 12) surface leads to the ordered formation of a periodic array of nanowires.
EXAMPLE 3 (Figure 5)
0.25 to 0.5 ML Ag was deposited onto a Si(5 5 12) wafer and annealed at 500 to 600 °C. The morphology at this coverage regime resembles nanoscale sawtooths along the [110] direction, as shown in Fig. 5. The sawtooths are about 0.4 nm tall and have a pitch comparable to the (5 5 12) unit cell.
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EXAMPLE 4 (Figure 6)
0.5 ML Ag was deposited onto a Si(5 5 12) wafer and annealed at 500 to 600°C. A well-ordered array of "double rows" is formed, as shown in Fig. 6. These double rows are the most ordered structures induced by Ag at any coverage and annealing temperature explored in our studies.
EXAMPLE 5 (Figure 7)
0.04 to 0.12 ML of Au may be deposited onto a Si(7 7 15) wafer and annealed at 800°C. Perfectly straight nanowires with a pitch of precisely 3.45 run are formed over wide expanses of the Si wafer.
EXAMPLE 6
0.2 to about 1.0 ML of Au maybe deposited on a Si(5 5 11) wafer and annealed at ~800°C. Perfectly straight nanowires with a pitch of 2.5 run are formed.
EXAMPLE 7 (Figure 9) Wet or Dry Etch Nano Fabrication Method - One step process
After the steps of Examples 2, 3, or 4 are performed, the Ag nanowires are used as an etch mask for a brief dry etch process using one of the well known plasma etching processes such as RIBE. This etch process is often quite brief because the Ag layers are only about 1 ML thick and therefore erode reasonably fast in most dry etching processes. The Ag layers may be thickened by evaporating a few ML of additional Ag or Au at a substrate temperature in the range of 200 to 350°C after the Ag nanowires have been formed, see Figure 9. This temperature range is sufficiently low to avoid the eutectic melting temperature of Au:Si of ~370°C, and high enough to allow considerable surface diffusion and to not allow condensation on the Si surface except at the thin Ag lines. This thickening process allows thicker grooves to be etched into the Si in this one step etching process, but is still probably limited to a depth of less than about
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20 nm before the somewhat thicker metal lines are excessively eroded by the wet or dry etching process.
EXAMPLE 8 (Figure 9 ^ Dry Etch Nano Fabrication Method - Two-step negative-resist process
After the steps of Example 7 are completed, an oblique angle evaporation of Au, Ag, Cd, or other metal within about 5° of grazing incidence is performed at RT or lower temperature while rotating the wafer. According to a method discussed in the 1998 U.S. Patent Application No. 09/187,730, this will result in nearly vertically disposed metal ridges that will be much thicker than the original Ag or Au nanowire layers. The results of highly oblique evaporation are discussed by K. Robbie, et al, J. Vac. Sci. Tech. B, 16(3), 1115-1122 (1998). This evaporated thicker metal nanowire is more robust in wet chemical etching processes, and will survive the much longer dry etch treatment of the second etching step. For a narrow metal ridge with a thickness of 10 to 50 nm, corresponding depths of at least 10 to 50 nm, respectively, will be obtainable using almost any of the modern plasma etching methods. Much deeper grooves may be obtained using the directed beam chemically reactive plasmas typical of RIBE and related processes. Such deep vertical grooves are important to the Buckyball superconductor applications discussed in the 1998 Pending Patent, as well as to the atomic-width filters and sensors discussed in the companion patent submitted along with this one. The oblique incidence evaporation may be preceded by a few ML of an evaporated adhesion-promoting metal layer such as Ti or Cr to ensure that the metal ridges stay in place during the wet or dry etching processes. The adhesion layer may be deposited at either oblique or near normal incidence depending on the particular application and the desired robustness. It is clear from Figure .9 that the groove is etched where there is no metal mask, which reverses the pattern of the metal pattern. This is therefore also a negative nano-lithography process. The positive etch-resist process was discussed earlier and is illustrated in Figure 10.
Although the present invention has been fully described in conjunction with the preferred embodiment
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thereof with reference to the accompanying drawings, it is to be understood that various changes and modifications may be apparent to those skilled in the art. such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims, unless they depart therefrom. For example, the same general methods are applicable to all semiconductors, and in fact to all crystalline materials that exhibit open channels along particular crystal directions. Also, it should be appreciated that most off the ranges above refer to Si and may be increased or decreased by up to 30% for other crystals unless otherwise indicated.
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WE CLAIM :
1. A MOSFET device comprising :
a substrate including a plurality of atomic ridges, each of said atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound ;
a plurality nanogrooves between said atomic ridges ;
at least one elongated molecule located in at least one of said nanogrooves ; and
a porous gate layer located on top of said plurality of atomic ridges.
2. The MOSFET device as claimed in claim 1, wherein said atomic ridges
have a pitch of about 2 to 5.4 nm.
3. The MOSFET device as claimed in claim 1, wherein said dielectric
layer comprises SiO2.
4. The MOSFET device as claimed in claim 1, wherein said at least one
elongated molecule comprises a long chain molecule.
5. The MOSFET device as claimed in claim 1, wherein said at least one
elongated molecule comprises a carbon nanotube.
6. The MOSFET device as claimed in claim 5, wherein said nanotubes
are capable of detecting the presence of NH3 and NO2 gas molecules.
7. The MOSFET device as claimed in claim 1, wherein said at least one
elongated molecule comprises a plurality of elongated molecules located in
said plurality of nanogrooves.
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8. The MOSFET device as claimed in claim 1, wherein said porous gate
layer has pores having diameters of 0.8 to 4.0 nm.
9. The MOSFET device as claimed in claim 8, wherein said porous gate
layer comprises a high conductance metal.
10. The MOSFET device as claimed in claim 1, wherein said porous gate
layer has pores having diameter of 0.3 to 0.7 nm.
11. The MOSFET device as claimed in claim 10, wherein said porous gate
layer comprises Au.
12. The MOSFET device as claimed in claim 1, wherein said porous gate
layer has pores that all are the same diameter to a tolerance of 0.2 nm.
13. The MOSFET device as claimed in claim 1, wherein said porous gate
layer includes pores that differ in diameter by at least 0.7 nm.
14. A MOSFET device, substantially as herein described, particularly with
reference to and as illustrated in the accompanying drawings.
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The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; and a porous gate layer located on top of the plurality of atomic ridges.

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Patent Number 199338
Indian Patent Application Number IN/PCT/2002/00324/KOL
PG Journal Number 11/2007
Publication Date 16-Mar-2007
Grant Date 16-Mar-2007
Date of Filing 08-Mar-2002
Name of Patentee STARMEGA CORPORATION,
Applicant Address PATENT ADMINISTRATION OFFICE, 512 TASSY CT., SE ALBUQUERQUE, NEW MEXICO 87123,
Inventors:
# Inventor's Name Inventor's Address
1 KENDALL L DON 512 TASSY CT., SE ALBUQUERQUE, NEW MEXICO 87123,
2 GUTTAG MARK 610 SOUTH FAYETTE STREET, ALEXANDRIA VA 22314
PCT International Classification Number G0IN23/00,G21B7/00,
PCT International Application Number PCT/US00/24815
PCT International Filing date 2000-09-08
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 60/153,088 1999-09-10 U.S.A.