Title of Invention

AN IMAGE PROCESSING APPARATUS

Abstract

ABSTRACT AN IMAGE PROCESSING APPARATUS An image processing apparatus capable of overlaying a plurality of images, comprises a graphic controller for performing image processing and control; video memory connected to said graphic controller for the storage of image data; and an image overlay processor connected to graphic controller. It has internal overlay image memory to provide outputs to graphic controller. The outputs are image data that are stored in said overlay image memory instead of image data stored in said video memory.

Full Text

The invention relates to an image processing apparatus. Recently, with the spread of multimedia, the demand has for computer systems that provide graphics controllers, for image processing, and peripheral circuits having improved performances. Especially important today, for the simultaneous display single screen of moving images and static images that have received from a plurality of sources, are techniques for superimposition and display of images, i.e., overlay techniques. The main conventional overlay techniques are 1) a system that provides for the high speed switching of the output of image display signals, and 2) a system in which memory is shared. These two systems, however, have the following problems. Brief Description of the accompanying drawings : Fig. 1 is a diagram illustrating a computer system for carrying out the present invention. Fig. 2 is a block diagram illustrating a logical circuit inside the computer system for carrying out the present invention. Fig. 3 is a block diagram illustrating a conventional system for the high speed switching of image display signals output. Fig. 4 is a block diagram illustrating a conventional shared memory system. Fig. 5 is a block diagram illustrating the peripheral graphics circuit fo^ carrying out the present invention. Fig. 6 is a detailed block diagram illustrating an overlay data processor for carrying out the present invention. Fig. 7 is a flowchart of the processing by the present invention for overlaying image data. Fig. 8 is a flowchart of the processing by the present invention for fetching image data from a video A/D converter. Fig. 9 is a flowchart of the processing by the present invention for fetching image data across the system bus. High speed switching system for the output of image signals : This system will now be explained while referring to Fig. 3. In Fig.3 are shown a graphic controller 31 that is connected to a system bus 30 to provide full control of a screen display; a video memory 33 in which screen display data are stored under the control of the graphic controller 31; an overlay data processor 34 that stores and processes display data that are different from those stored in the video memory 33; and a switch circuit 32 that switches between an image signal 35 from the graphic controller 31 and an image signal 36 from the overlay data processor 34. As is described above, however, this system generally requires two independent image output circuits: a graphic controller circuit and an overlay data processor circuit. Further, since the image display signals are analog signals, the design of a circuit and a board required for processing the signals is more complicated than when the image display signals are digital signals. In addition, since the two circuits are redundantly provided with similar structures, manufacturing costs are also increased. And if the switching of an image display signal is performed before it is converted into an analog signal, asynchronous display signals from the two different signal sources must be synchronized with each other. Shared memory system : This system will now be explained while referring to Fig. 4. The system comprises: a graphic controller 42 that is connected to a system bus 41, which is the same as the system bus 30 in Fig.3, to provide full control of a screen display; a video memory 46 in which screen display data are stored under the control of the graphic controller; and an overlay data processor 47 that stores and processes display data that are different from those stored in the video memory 46. An arbitration function for memory access arbitration is required so that the graphic controller 42 and the overlay data processor 47 can alternately access the same video memory 46. The employment of the arbitration function can resolve the problem of simultaneous access of the same video memory 46. According to this system, the graphic controller 42 must have the arbitration function for accessing the video memory 46. Only a graphic controller that has an arbitration function can be employed for this system. And as only a few graphic controllers that have such an arbitration function are sold on the market and the manufacturing costs for such controllers are high, there is only a very limited selection of graphic controllers that can be used for a computer system. Further, in the shared memory system, original image data at an address that is the same as the overlay image data are actually overwritten by using the overlay image data. Then, when the image data are to be changed back to the original image data, the original data must be rewritten at the same address in the video memory, a process for which extra time is required. Objective : It is one object of the present invention to resolve the problems of the conventional overlay systems, by using hardware. through the addition of an overlay function to a common graphic controller. More specifically, according to the present invention, provided is an overlay circuit for which (1) the design is easy and manufacturing can be performed at a low cost because the image data processing is performed by a digital circuit; (2) communication using a fast clock signal is not required because there is no need to synchronize two different display signals with each other; and (3) a common graphic controller widely sold on the market can be employed. Summary of the Present Invention : To carry out the present invention, a newly improved overlay data processor is introduced. The overlay data processor comprises, as characteristic components, an address search circuit, internal video memory, and an overlay data controller. The address search circuit constantly monitors a target address for the reading operation performed by the graphic controller, and image data for overlaying are stored in the internal video memory. When a read address designated by the graphic controller falls in an address region that is a target for overlaying, the overlay data controller controls a data buffer that is connected to the graphic controller and transmits to the graphic controller the image data from the internal video memory, instead of the image data from the usual video memory. Through the above process, desired image data is overlaid at a desired screen position. Accordingly the present invention provides an image processing apparatus capable of overlaying a plurality of images, comprising : (a) a graphic controller for performing image processing and control; (b) video memory connected to said graphic controller for the storage of image data; and (c) an image overlay processor connected to said graphic controller and which has internal overlay image memory to provide outputs to said graphic controller, image data that are stored in said overlay image memory instead of image data stored in said video memory when said graphic controller reads data from a predetermined address area in said video memory. A description following the subject order shown below will be given for one embodiment of the present invention with reference to the accompanying drawings. For convenience sake, the arrangement and the processing of a system according to the present invention will be described by employing a notebook computer that has lately become popular on the market. The use of the present invention, however, is not limited to notebook computers, but can also be applied for various other types of computer systems, such as desktop and floor models. Personal computer system (Fig. 1) : Fig. 1 is a diagram illustrating the complete computer system that carries out the present invention. A main body 10 of the computer system may be a portable PC as illustrated, or may be a desktop or another type of PC, or a workstation. As a standard, the computer system 10 comprises: a keyboard 12 that serves as a device for inputting characters; a liquid crystal panel 13 that serves as an output device for characters and graphics; a CD-ROM drive 14 that serves as a large capacity memory media device; a loudspeaker that serves as an output device for speech, etc.; and a video camera 15 that serves as an image input device, which is recently added. As the details of the keyboard 12 and the liquid crystal panel 13 are not directly related to the structure of the present invention, they are not shown in Fig. 1. Hardware structure of personal computer system (Fig. 2): Fig. 2 is a block diagram illustrating a logical circuit that is normally located above a mother board (planar board) inside the notebook computer 10 in Fig. 1. The present personal computer system has a plurality of buses connected to devices that have different processing speeds, and a circuit, which is called a bus bridge, that performs protocol conversion between buses to permit the plurality of buses to communicate with each other. As specific bus structures, in Fig. 2 are shown a CPU local bus 212 that is directly connected to a CPU 202; PCI buses 213 and 216 that communicate with relatively high speed peripheral devices; and an ISA bus 221, a PCMCIA bus 219 and an IDE bus 217 that communicate with relatively low speed peripheral devices. Further, in Fig. 2 are shown a host bridge/memory controller 204 for connecting the CPU bus 212 to the PCI bus 213; a PCI-ISA bus bridge circuit 215 for connecting the PCI bus 213 to the ISA bus 221; and a PCI-PCMCIA bus bridge circuit 214 for connecting the PCI bus 213 to the PCMCIA bus 219. The individual buses are connected to a plurality of peripheral devices that match the processing speeds of the respective buses. For example, the highest speed CPU local bus 212 that literally communicates with the CPU 202. The PCI bus 213 communicates with a high speed graphic/video controller 222. The ISA bus 221 communicates with a keyboard controller 229, an audio controller 230, and a Super I/O controller 231, which is a general-purpose I/O controller. The host bridge/memory controller 204, which has not only a bus bridge function but also a memory control function, is connected to a BIOS ROM 206 and a main memory RAM 207 via a memory data buffer 205. The graphic/video controller 222, which is connected to the PCI bus 213, has as one component a screen display video memory 223. The graphic/video controller 222 employs a digital signal to communicate with an LCD panel via a buffer 224, digitizes the analog video input from an external device via an analog front end (AFE) 225, and fetches the digital data. Peripheral circuit for graphic controller (Fig. 5) : Fig. 5 is a schematic diagram illustrating the arrangement of the present invention. The arrangement in Fig. 5 corresponds to the above described background in Figs. 3 and 4. As main components, in Fig. 5 are shown a graphic controller 502 (corresponding to 222 in Fig. 2) connected to a system bus 501 (corresponding to 213 in Fig. 2); a video memory 505 (223 in Fig. 2) in which image data are stored; an overlay data processor 503; and a data buffer 504. One of the differences in the arrangement of the present invention from those shown in Figs. 3 and 4 is that the graphic peripheral circuit includes the data buffer 504 betw the graphic controller 502. The other difl processor 503 is directly connected to the , of the computer system can directly access tu 503. The overlay data processor 503 is connected u signal of the buffer 504 by a gate control signal 512, an^ disables data output from the video memory 505 by using the gaiw signal 512. More specifically, when the output of the gate control signal 512 is enabled by the overlay data processor 503, the buffer 504 outputs the data from the video memory 505 to the data bus 510. When the output of the gate control signal 512 is disenabled by the overlay data processor 503, the buffer 504 does not output the data from the video memory 505 to the data bus 510. The overlay data processor 503 incorporates its own image memory, which will be described later, and fransmits the image data to the graphic controller 502 across the data bus 511 and the data bus 510, which communicates with the graphic controller 502. Upon the receipt of the image data from the video memory 505 and the overlay data processor 503, the graphic confroller 502 processes them and transmits the resultant data across the display signal line 508 to a display device (not shown), which is connected to the computer system 10, and finally an overlaid image is displayed on the display device. Internal structure of overlay data processor of the present invention (Fig. 6) : In Fig. 6 is shown the detailed internal structure of the overlay data processor 503, one of the characteristic components of the present invention shown in Fig. 5. An overlay data processor 600 (corresponding to 503 in Fig. 5) comprises, as its primary components, an overlay data controller 607 that controls the entire overlay data processor 600; a memory controller 610 that is connected to the overlay data controller 607 to control an internal video memory 604; a system bus interface circuit 609 that serves as an interface with a system bus 601; an address search circuit 606 that monitors a target address, for reading and writing data, that is transmitted from a graphic chip 602, which serves as a graphic controller, across an address and control line 613 to the video memory 604; a digital video interface circuit 608 that fetches, for the overlay data processor 600, a digital video signal from a video AID converter 605 that converts into a digital signal an analog signal from an extemal video device; and a format converter 611 that performs conversion for a plurality of video data formats, such as RGB and a YUV. The overlay data processor 600 can be so designed that it incorporates a data buffer 603. An internal memory 612 may be designed that is provided outside the overlay data processor 600. The processing by the overlay data processor 600 in Fig. 6 will now be described while referring to Figs. 7 through 9. Processing of the present invention (Figs. 7 through 9) : Fig. 7 is a flowchart of the processing by the present invention when two image data are to be overlaid. First, at block 71, an address range for an overlay in a video memory area is designated. At block 72, the address search circuit 606 constantly monitors an address, which is to be read next from the video memory 604 (corresponding to 505 in Fig. 5) by the graphic chip 602 (corresponding to 502 in Fig. 5), and determines whether or not the read address falls within the designated address range for an overlay. As a result, when the address to be read falls within the address area for an overlay, program control advances to block 73. When the address to be read is outside the address range, program control returns to block 72, where at the monitoring of the read address is continued. At block 73, since the graphic chip 602 is to read the address area designated for an overlay, the overlay data processor 600 employs the internal overlay data controller 607 to control the data buffer 603. The overlay data controller 607 actually inhibits the output from the data buffer 603 (corresponding to 504 in Fig. 5) across a control line 621. Following this, program control moves to block 74. The overlay data processor 600 employs the internal memory controller 610 to read image data to be overlaid from the internal memory 612. The overlay data controller 607 outputs the overlay data that were read from the internal memory 612 across data lines 613 and 614. As a result, the graphic chip 602 reads the overlay data from the memory 612, instead of the data from the video memory 604. The overlay data are transmitted to a display device by the graphic chip 602 and are displayed on a screen. Program control thereafter returns to block 72, and the above described process is repeated, so that desired image data are overlaid at desired areas on the display device. Fig. 8 is a flowchart showing the processing of the overlay data processor 600 when it fetches image data from an extemal video device. At block 81, a data format is designated that is employed after conversion of data which were fetched from the extemal video device. At block 82, the digital video interface circuit 608 transfers video data that were received from the video AID converter 605 to the format converter 611. At block 83, upon receipt of the video data, the format converter 611 converts the fetched video data into data having a data format designated at block 81. Then, the video data in the designated data format are written into the internal memory 612 under the control of the memory controller 610. Fig. 9 is a flowchart of the processing of the overlay data processor 600 when it fetches image data across the system bus 601. A data format that is employed after conversion is designated (block 91). The system bus interface circuit 609 receives image data that are transferred from a master device, such as a processor, across the system bus 601 to the overlay data processor 600, and transmits the image data to the format converter 611 (block 92). The format converter 611 converts the received image data into data having the designated data format. The converted image data are written into the video memory 612 under the control of the memory controller 610 (block 93). Through the above described process that is performed by the overlay data processor 600, image data from a master device, such as a processor, are fetched into the video memory. In conclusion, the following matters are disclosed concerning the configuration of the present invention. The image processing apparatus, is capable of overlaying a plurality of images. It comprises: an image processing controller for performing image processing and control; image memory, which is connected to the image processing controller, for the storage of image data; and an overlay processor, which is connected to the image processing controller and which has internally overlay image memory, that, when the image processing controller reads data from a predetermined address area in the image memory, outputs to the image processing controller image data that are stored in the overlay image memory instead of image data thai are stored in the image memory. The image processing apparatus further comprises: a data buffer that is connected between the image processing controller and the image memory, wherein output of image data from the data buffer is inhibited when the image processing controller reads data from the predetermined address area in the image memory. The image overlay processor, which is connected to and cooperates with a graphic controller and a video memory to perform image overlay, comprises: an address search circuit for monitoring an address in the video memory, at which data is to be read, when the graphic controller reads the data from the video memory; overlay memory that is independent of the video memory to store an overlay image; and (c) a circuit that, when the address search circuit detects a predetermined address for data reading, transfers to the graphic controller data that correspond to the predetermined address in the overlay memory, instead of data at the predetermined address in the video memory. The image overlay processor further comprises: a buffer circuit that is connected to the video memory to control data output by the video memory to the graphic controller. The image overlay processor further comprises: a system bus interface circuit, for exchanging data with a system bus, that permits a CPU of the computer system to directly access the overlay memory. The image overlay processor further comprises: a format converter for performing format conversion of image data. The image overlay processor further comprises: an image interface that is employed to fetch image data from an external device. A computer system is provided which comprises an image overlay processor that is connected to and cooperates with a graphic controller and a video memory to perform image overlay. The computer system comprises: a processor; main memory; a system bus employed to connect peripheral devices; a graphic controller connected to the system bus; video memory connected to the graphic controller; and an overlay processor connected to the system bus, the overlay processor including, an address search circuit for monitoring an address in the video memory, at which data is to be read, when the graphic controller reads the data from the video memory, overlay memory that is independent of the video memory to store an overlay image, and a circuit that, when the address search circuit detects a predetermined address for data reading, transfers to the graphic controller data that correspond to the predetermined address in the overlay memory, instead of data at the predetermined address in the video memory. An image overlay method is provided for a computer system that comprises a graphic controller, a video memory which is connected to the graphic controller, and an image overlay processor that is connected to the graphic controller and the video memory and that incorporates overlay memory and that overlays images. The method comprises: a step of reading an address, in the video memory, at which data are to be read when the graphic controller reads the data from the video memory; a step of comparing the address, which is read at the step of reading the address, with a predetermined address; and a step, when it is determined at the step of comparing the address that the address and the predetermined address match, of transferring to the graphic controller data that correspond to the predetermined address in the overlay memory, instead of data at the predetermined address in the video memory. As is described above, with the configuration of the present invention, provided is an overlay function, by using hardware, with which the problems of the conventional overlay systems are resolved, that is added to a common graphic controller. WE CLAIM : 1. An image processing apparatus capable of overlaying a plurality of images, comprising: (a) a graphic controller for performing image processing and control; (b) video memory connected to said graphic controller for the storage of image data; and (c) an image overlay processor connected to said graphic controller and which has internal overlay image memory to provide outputs to said graphic controller, image data that are stored in said overlay image memory instead of image data stored in said video memory when said graphic controller reads data from a predetermined address area in said video memory. 2. The apparatus according to claim 1, wherein a data buffer is connected between said graphic controller and said video memory for inhibiting output of image data from said data buffer when said graphic controller reads data from said predetermined address area in said video memory. 3. The apparatus according to claim 1, wherein said image overlay processor comprises an address search circuit for monitoring an address in said video memory for reading data, when said graphic controller reads said data from said video memory; an overlay memory that is independent of said video memory to store an overlay image; and a circuit for transferring data that correspond to said predetermined address in said overlay memory to said graphic controller when said address search circuit detects a predetermined address for data reading. 4. The apparatus according to claim 3, wherein said image overlay processor is provided with a buffer circuit connected to said video memory to control data output by said video memory to said graphic controller. 5. The apparatus according to claim 3, wherein said image overlay processor is provided with a system bus interface circuit for exchanging data with a system bus, that permits a CPU of a computer system to directly access said overlay memory. 6. The apparatus according to claim 3, wherein said image overlay processor is provided with a format converter for performing format conversion of image data. 7. The apparatus according to claim 3, wherein said image overlay processor is provided with an image interface to fetch image data from an external device. 8. A computer system having an image processing apparatus comprising a processor; main memory; a system bus employed to connect peripheral devices; a graphic controller connected to said system bus; video memory connected to said graphic controller; and an image overlay processor connected to said system bus, said image overlay processor comprising an address search circuit for monitoring an address in said video memory for reading data when said graphic controller reads said data from said video memory, an overlay memory that is independent of said video memory to store overlay image, and a circuit for transferring data to said graphic controller that correspond to said predetermined address in said overlay memory, instead of data at said predetermined address in said video memory when said address search circuit detects a predetermined address for data reading. 9. An image processing method for a computer system Goi^^^i^fe-a graphic controller, a video memory which is connected to said graphic controller, and an image overlay processor that is connected to said graphic controller and said video memory and incorporates overlay memory and overlays images, said method comprising the steps of (a) reading an address, in said video memory, at which data are to be read when said graphic controller reads said data from said video memory; (b) comparing said address, which is read in said step (a) with a predetermined address; and (c) when it is determined that said address and said predetermined address match, transferring data to said graphic controller that correspond to said predetermined address in said overlay memory, instead of data at said predetermined address in said overlay memory. 10. An image processing apparatus, substantially as hereinabove described and illustrated with reference to the accompanying drawings.

Documents:

2060-mas-1996 abstract duplicate.pdf

2060-mas-1996 abstract.pdf

2060-mas-1996 claims duplicate.pdf

2060-mas-1996 claims.pdf

2060-mas-1996 correspondence others.pdf

2060-mas-1996 correspondence po.pdf

2060-mas-1996 description (complete) duplicate.pdf

2060-mas-1996 description (complete).pdf

2060-mas-1996 drawings duplicate.pdf

2060-mas-1996 drawings.pdf

2060-mas-1996 form-2.pdf

2060-mas-1996 form-26.pdf

2060-mas-1996 form-4.pdf

2060-mas-1996 form-6.pdf

2060-mas-1996 others.pdf

2060-mas-1996 petition.pdf