Title of Invention  A HARDWARE FUZZY INFERENCE SYSTEM 

Abstract  A hardware fuzzy inference system comprising: a fuzzyfier for each crisp input for finding membership function and degree of membership for the said inputs, the output of the said fuzzyfiers is connected to  a) Cf MIN units where Q is the overlap factor and 'n' the number of inputs to find the minimum of the degrees of the membership of the inputs corresponding to a membership function, and b) n" rule modules to store the inferred result corresponding to a given rule in the form of the number of its membership function in the output variable space, the output of said MIN units and the rule modules is connected to aggregate unit, the output of aggregate unit is connected to the defuzzyfier unit which receives digital inputs from output variable memory and the defuzzy partial sum memory to find crisp output value corresponding to the given inputs 2. A hardware fuzzy inference system as claimed in claim 1 wherein the said crisp inputs to the system, the UoD (Universe of disclosure) and the the degrees of membership are of any resolution. " ■ ^ 3. A hardware fiizzy inference system as claimed in claim 1 wherein the look up table for fuzzification is RAM, ROM or PLA and for each input to the system there is a corresponding look up table that stores the membership function numbers associated with every element in the UoD and the degrees of membership in atmost Q. fuzzy sets. 4. A hardware fuzzy inference system as claimed in claim 1 wherein the MIN units are comparators each connected to a multiplexer to find the minimum of the inputs to perform the antecedent evaluation by finding the minimum of the degrees of membership associate with each antecedent of a rule 
Full Text  This invention relates to a hardware fuzzy inference system that aims at parallel firing of all active rules with minimized memory using the proposed generalized procedure for rule distribution across memory modules. Background Fuzzy logic [1], [2] processing, though inherently complex supports parallelism to a great ex¬tent. Exploiting this parallelism is imperative for enhancing the performance of any hardware fuzzy inference system. Towards this end, several architectures [3], [4] have been suggested in the literature. The one proposed in [4], aims at parallel rule firing by implementing 2" or NSA (Nuihber of Simultaneously Active) identical rule bases, assuming an Overlap Factor (H) of two, where Q. is defined as the maximum number of membership functions in which a given input vector has nonzero membership grade. With n input variables, each taking on m used to achieve parallel firing of all active rules and the memory size increases significantly as the number of inputs increase. Keeping this in mind, an improved fuzzy logic processing architecture has been developed and is described in this document. ' The objective of this invention is to design fuzzy inferencing architecture that incorporate concurrent rule firing with reduced memory requirnents for the rule base. To achieve the said objective this invention provides a hardware fuzzy inference system comprising: a fiizzifier for each crisp input for finding the membership function and degree of membership for the said inputs, the output of the fiizzifier is connected to  a) Q" MIN units, where CI is the overlap faictor and 'n' the number of inputs, to find the minimum of the degrees of the membership of the inputs corresponding to a membership function, and b) Q" rule modules to store the inferred result corresponding to a given rule in the form of the number of its memberp function m the output variable space, the output of MIN units and the rule modules is connected to aggregate unit, the output of aggregate unit is connected to the defiizzifier unit which receives digital inputs from output variable memory and the defuzzy partial sum memory to find the crisp output value corresponding to the given inputs The said crisp inputs to the system, the UoD (Universe of discourse) and the degreed of' membership are of any resolution and the lookup table for fuzzification is RAM, ROM or PLA and for each input to the system there is a corresponding look up table that stores the membership function numbers associated with every element in the UoD and the degrees of membership in atmost Q. fuzzy sets. Each of the MIN units is a comparator cormected to a multiplexer to find the minimum of its inputs to perform the antecedent evaluation by finding the minimum of the degrees of membership associated with each antecedent of a rule The rule base is also RAM, ROM or PLA to store the inferred results corresponding to a given rule in the form of its membership function number in the output variable space, and the aggregate unit consists of hardware logic to perform the rule aggregation which is the combination of the result of all rules that update similar membership functions for finding the fiizzy output. In the fuzzification lookup table, an evennumbered membership function and the corresponding . degree of membership are output on MFE and GRE buses, respectively, while an oddnumbered membership function and the corresponding degree of membership are output on MFQ and GRo buses, respectively. The rulebase is distributed across H" modules resulting in parallel firing of all the active rules and significant saving in memory required to implement the rulebase. The output variable memory stores the membership functions corresponding to each fuzzy set ' in the output UoD. . The defuzzy partial sum memoiy stores the defuzzification partial sums as desoibed in [4]. The defuzzy unit performs the defuzzification of the fuzzy output by the Centre of Gravity or any other defuzzification technique to yield a crisp output. The invention will now be described with reference to the accompanying drawings and table.. Figure 1 shows the pipestages architecture of the fuzzy inference system Figure 2 shows the block diagram architecture of the fuzzy inference system Table 1 gives the rule distribution across memory modules for Q =2. Table 2 gives a comparison of the size of memory required for the rulebase for .Chieuh's architecture, ideal case and the two cases proposed in the new design. New Architecture The pipestages for the new architecture are shown in Figure 1. In stage 1, the digitized crisp values of the observed inputs are fuzzified. Two functional entities work in parallel in stage 2 to perform the evaluation of the antecedent and determining the consequent of the rule unlike the previous implementations where consequent determination is followed by antecedent evaluation to elongate the pipeline. In stage 3, rule aggregation or combining the result of all firable rules that update the same output space is done. The aggregated output space is then defuzzified in stage 4 to yield a crisp output. The most important feature of this architecture is that parallel firing of all the active rules is achieved by distributing a single rule base across NSA number of rule memory modules so that there is significant saving in memory. The distribution of rules in the rule memory modules is done according to the following procedure. ( ) the membership function number corresponding to a particular linguistic value of the i"* input. The rule distribution and the number of rules in each module are given in Table 1. This table gives the rules to be stored in each rule module. For example, the third row of the Statement: With the rule distribution given in Table 1, no two rules in a rule module will fire simultaneously. Procedure for Rule Distribution for any fi : Here, rules are distributed across Q** memory modules. Generally as fi increases, m increases and therefore the number of possible rules (= m") also increases. However, though this is large, the number of rules specified in the ruleset is actually small in most applications. Therefore in such cases, it is easier to select every rule and decide the number of the rule module to which it belongs rather than choose every single rule module and decide the set of all possible rules that must belong to each. Keeping this in mind, and also the fact that the procedure for rule distribution suggested in Table 1, gets complicated as Q increases, the following procedure has been proposed. f' I Figure 2 shows a block diagram for a twoinput, single output Fuzzy Inference System (FIS). The observed input values are assumed to be digitized into 6 bits. Each input variable of the system has three membership functions so that there are nine possible rules and a maximum of four active rules. The membership grades and numbers of the membership functions are encoded into four and two bits, respectively. Fuzzification is performed in the input lookup tables. Each table is addressed by the cor¬responding crisp observed input value. The organization of the lookup table is different from that suggested in earlier architectures. The lownumbered and highnumbered membership functions and their corresponding membership grades are output in the earlier designs. Here, always the evennumbered membership function and the corresponding degree of member¬ship are output on . buses respectively while the oddnumbered membership function and the corresponding degree of membership are output on buses respectively. This effectively means that the numbers of the membership functions {and grades) stored as a word in memory for a given input vector need not be in ascending order. By this reorganization of the lookup table, it becomes possible to address the rulememory modules using selected bits of the buses. This results in considerable reduction in the size of memory required for a given rulemodule by eliminating redundant memory. In Chieuh's architecture [4] each rule base is addressed using bits, so that the depth of each is of these locations are required. The exact reduction in memory is explained later. The individual lines on respectively, where i can take integral values from 0 to It must be noted that if any raw input does not map into a region of overlap, then that input has nonzero membership grade in only one linguistic value and the fuzzification lookup table outputs zero on the appropriate grade and membership function buses. The buses form the addresses to the* rule memory modules that store the consequents of the rules. The array of MIN units performs the antecedent evaluation by taking the minimum of all combinations of the membership grades of the two inputs. The number of the MIN units required here is four and in general equal to NSA (= Q"). Rule aggregation which is the combination of the result of all rules that update the same output is performed in the Aggregate Unit. The output is defuzzified by the Centre of Gravity (COG) method in the defuzzification unit to yield a crisp output. Comparison of Memory Required for the Rulebase In [4] parallel firing of all active rules is achieved by having identical rule bases. Here a single rule base, with rules distributed across memory modules achieves the same result. Memory modules with a size equal to a power of two can be implemented in either of the two ways mentioned below. Let Si be the actual size of the t** memory module where i iakes on values from 0 to (2" — 1). 1. The size of each module can be made equal to the size of the largest module rounded to a power of two. The total memory size A/i, in bits, required for the rule base is (3) where d is an integer such that (m" + d) is the smallest power of two greater than m. 2. The size of each module can be made equal to 5 = {Si + d') where d' is an integer such that S[ is the smallest power of two greater than 5, (the actual size of the memory module). The total size of rule base memory M2, in this case is (4) A comparison of the sizes of memory required for the rule base in the two cases, M1 i M2 along with that required ideally / and that used in Chieuh's architecture C is en in Table 2. It is seen that the total memory required in the proposed scheme for the Iementation of the rule base, is significantly less when compared to the one in Chieuh's litecture and is very close to the ideal memory requirement in both cases. Also, in Case r m = 3 and any n, the memory size is equal to the ideal size. We claim: 1. A hardware fuzzy inference system comprising: a fuzzyfier for each crisp input for finding membership function and degree of membership for the said inputs, the output of the said fuzzyfiers is connected to MIN units where Q is the overlap factor and 'n' the number of inputs to fmd the minimum of the degrees of the membership of the inputs corresponding to a membership function, and n" rule modules to store the inferred result corresponding to a given rule in the form of the number of its membership function in the output variable space, the output of said MIN units and the rule modules is connected to aggregate unit, the output of aggregate unit is connected to the defuzzyfier unit which receives digital inputs from output variable memory and the defuzzy partial sum memory to fmd crisp output value corresponding to the given inputs 2. A hardware fuzzy inference system as claimed in claim 1 wherein the said crisp inputs to the system, the UoD (Universe of disclosure) and the . degrees of membership are of any resolution. 3. A hardware fuzzy inference system as claimed in claim 1 wherein the look up table for fuzzification is RAM, ROM or PLA and for each input to the system there is a corresponding look: up table that stores the membership function numbers associated with every element in the UoD and the degrees of membership in atmost Q fuzzy sets. 4. A hardware fuzzy inference system as claimed in claim 1 wherein the MIN units are comparators each connected to a multiplexer to fmd the minimum of the inputs to perform the antecedent evaluation by finding the minimum of the degrees of membership associate with each antecedent of a rule 5 A hardware fuzzy inference system as claimed in.claim 1 wherein the rule base is RAM, ROM or PLA to store the inferred result? corresponding to a given rule in the form of the number of its membership function in the output variable space. 6. A hardware fuzzy inference system as claimed in claim 1 wherein the aggregate unit consists of hardware logic to perform the rule aggregation which is the combination of the result of all rules that update similar membership functions for finding the fuzzy output. 7. A hardware fuzzy inference system as claimed in claim 1 wherein, in the fuzzification lookup table, an evennumbered membership function and the corresponding degree of membership are output on MFE and GRE buses, respectively, while an odd . numbered membership function and the corresponding degree of membership are output on MFo and GR 8. A hardware fuzzy inference system as claimed in claim 1 wherein the rulebase is distributed across H" modules resulting in parallel firing of all the active rules and significant saving in memory required to implement the rulebase. 9. A hardware fuzzy inference system as claimed in claim 1 substantially as herein described with reference to the accompanying drawings. J 1. References j Lotfi.A.Zadeh. Fuzzy sets. Information and Control. 8:338353, 1965. ] Lotfi.A.Zadeh. Outline of a new approach to the analysis of complex systems and decision processes, IEEE Transactions on Systems, Man, and Cybernetics, 3(l):2845. January 1973. ' ' M.Togai and H.VVatanabe. Expert System on a chip: An Engine for RealTime Approx¬imate Reasoning. IEEE Expert, l(3):55€2, 1986. T.Chieuh. Optimization of Fuzzy Logic Implementation. In Proc.oJ 21st International Symposium on Multiple Valued Logic, pages 343355. 1991. 

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1364mas1997 correspondenceothers.pdf
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1364mas1997 description (complete) duplicate.pdf
1364mas1997 description (complete).pdf
1364mas1997 drawings duplicate.pdf
Patent Number  198027  

Indian Patent Application Number  1364/MAS/1997  
PG Journal Number  33/2010  
Publication Date  13Aug2010  
Grant Date  
Date of Filing  23Jun1997  
Name of Patentee  REGISTRAR,  
Applicant Address  INDIAN INSTITUTE OF SCIENCE, DEPARTMENT OF ELECTRICAL COMMUNICATION ENGINEERING, BANGALORE  560 012  
Inventors:


PCT International Classification Number  G06F 7/00  
PCT International Application Number  N/A  
PCT International Filing date  
PCT Conventions:
