Title of Invention	A FRAME OF A VIDEO SIGNAL ON A SDRAM
Abstract	A motion picture decoder uses a synchronous dynamic random access memory (SDRAM) as a frame memory in which the SDRAM is used to store a one-frame video signal. By using a SDRAM which can operate at high speed, a one-frame motion picture data is appropriately recorded in the SDRAM, to thereby enable processing complicated predictions of the motion compensation using the frame memory.

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BACKGROUND OF THE INVENTION The present invention relates to a method to recording a refrance video ripnal on a SDRAM & more pante-culaly frame memory for use in a motion picture decoder, and more particularly, to a frame memory which can perform a motion compensation at high speed in which a synchronous dynamic random access memory (SDRAM) is used to store a reference picture. Generally, a system such as a high-definition TV or a digital VCR encodes and decodes digital audio and video signals. A video encoder performs orthogonal transformation, quantization, variable-length coding, and motion estimation and compensation coding, with respect to input video signals. FIG. 1 shows an apparatus for decoding video data encoded by the above video encoder. In the FIG. 1 video decoder, a variable-length decoder 11 variable-length-decodes received encoded data. An inverse quantizer 12 inversely quantizes the variable-length-decoded data. An inverse discrete cosine transformer (inverse DCT) 13 transforms the inversely quantized data into video data having a spatial domain. A motion compensator 14 reads video data of a macroblock corresponding to a motion vector from a frame memory 15 and performs motion compensation with respect to the video data supplied from the inverse DCT 13. The motion compensated video data is output to a downstream block (not shown) and also stored in the frame memory 15 which will be used for subsequent motion compensation. Here, the motion vector, is applied-from the variable-length decoder 11 and is usually supplied from an encoder, together with the encoded video data. A "prediction" is to read data of a predictive macroblock designated by a motion vector, from the frame memory 15. There are two kinds of prediction, one is a "field prediction" with respect to a reference field picture stored in the frame memory 15; and the other is a "frame prediction" with respect to a reference frame picture stored in the frame memory 15. Meanwhile, a picture is classified into a "field picture" which is decoded or encoded in units of a field, and a "frame picture" which is decoded or encoded in units of a frame. Also, two field pictures corresponding to one frame is composed of a top field and a bottom field. The field picture is used only for field prediction and the frame picture is used for both field prediction and frame prediction. To process such prediction without delay, data stored in a frame memory 15 should be swiftly read out . However, as a motion amount between pictures becomes larger, a more amount of data should be read out from the frame memory 15. As a result, it is required that a frame memory 15 should swiftly output stored data. SUMMARY OF THE INVENTION To solve the above problem, it is an object of the present invention to provide a motion picture decoder which performs motion compensation prediction at high speed, by using a SDRAM which operates even at a frequency of about 100 MHz as a frame memory. The present invention, therefore, provides a method of recording a frame video signal on a synchronous dynamic random access memory (SDRAM) ,the video signal recording method comprising the step of: disposing vertical 16 lines of a one-macroblock to horizontal 16 columns in the SDRAM in which a video signal having a vertical one word and horizontal 16 lines in the one-frame video signal is defined as a one-macroblock. It is another object of the present invention to provide a method of recording a one-frame video signal to match the features of a SDRAM. To accomplish the above object of the present inv.ention. there is provided a motion picture decoder using a SDRAM as a frame memory. The above other object of the present invention can be accomplished by providing a method of recording a one-fn?me video signal on a SDRAM, the video signal recording method comprising the steps of: disposing vertical 16 lines of a one-macroblock to horizontal 16 columns in the SDRAM in which a video signal having a vertical one word and horizontal 16 lines in the one-frame video signal is defined as a one-macroblock; disposing a one-slice video signal to a domain of 128 columns by N rows (N is a natural number) in the SDRAM, by changing and disposing the rows of the SDRAM for every other 8-macroblock; and disposing every 8-macroblock of 4 slices so that row addresses are identical to each other, by changing and disposing the bank of the SDRAM for every other 2-slice, BRIEF DESCRIPTION OF THE DRAWINGS The above object of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: FIG. 1 is a block diagram of a general motion picture decoder. FIG. 2 shows video data of a general one-frame. FIG. 3 shows video data of a one-slice in FIG. 2. FIG. 4 shows the structure of a SDRAM according to the present invention. FIG. 5 is a view for explaining a method of disposing video data of a one-macroblock in the SDRAM according to the present invention. FIG. 6 is a view for explaining a method of disposing video data of a one-slice in the SDRAM according to the present invention. FIG. 7 is a view for explaining a method of disposing video data of a one-frame in the SDRAM according to the present invention. FIG. 8 is a view for explaining a method of disposing video data of a one-frame in the SDRAM from the viewpoint of data, FIG. 9 is a conceptual diagram for explaining a predictive macroblock designated by a motion vector in integers-pixel units, FIG. 10 is a conceptual diagram for explaining a predictive macroblock designated by the motion vector in half-pixel units. FIG. 11 shows a frame prediction embodiment in the frame picture1. FIG. 12 shows a field prediction embodiment in the frame picture. FIG. 13 shows a field prediction embodiment in the field picture. FIG. 14 is a timing diagram showing control commands resulting from combination of control input signals in the SDRAM. FIG, 15 is a timing diagram for explaining a write operation of writing one-macrohtock video data on the SDRAM according to the present invention. FIGs. 16A-16C are timing diagrams for explaining a read operation of reading a part of predictive macroblocks shown in FIG. 11. FIGs. 17A and 17B are tables showing variation of the row and bank addresses of each block shown in FIG. 11. FIGs. 18A and 18B are view showing the relationship between addresses of the column of the predictive macroblock and that of an actual memory. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below in more detail with reference to the accompanying drawings. FIGs. 2 and 3 are views for explaining the structure of a one-frame of digitally encoded video data. In FIG. 2, a one-frame is composed of horizontal 1920 pixels and vertical 1088 lines, and a one-slice is composed of horizontal 1920 pixels and vertical 16 lines within the one-frame. That is, a one-frame is composed of 68 slices S0-S67. Assuming that horizontal 16 pixels is a one-word, a one-macroblock composed of 16 by 16 pixels in the horizontal and vertical directions can be represented as a horizontal one-word multiplied by vertical 16 lines. Thus, a one-slice is composed of 120 macroblocks M0-M119 as shown in FIG. 3. FIG. 4 shows the structure of a SDRAM which is used in the present invention. A main feature of the SDRAM is that all signals operate in synchronization with a clock pulse. Thus, differently from other RAMs which operate during an interval of time determined by a pulsewidth of a control signal, the SDRAM generates a control signal for performing a corresponding operation in synchronization with clock. A frame memory processes data in units of a word, for example, 16 bits in this embodiment. Accordingly, it is possible to construct a frame memory by connecting 8 SDRAMs each having a 16-bit data bus in parallel with each other. In FIG. 4, the SDRAM is composed of two banks, each of which has 256 columns by 2048 rows. In such a SDRAM, a row address is determined by 11-bit input pins A10-A0, and a column address is determined by 8-bit input pins A[7..03. also, a bank address is determined by an input pin All. In the following description, a row address is represented as R[ ], and a column address is represented as C[ ]. FIGs. 5-8 are views for explaining patterns of disposing video data of a one-frame in the SDRAM according to the present invention. As shown in FIG. 5, a one-macroblock of the video data represented as a one-word by 16 lines is positioned in horizontal 16 columns by a vertical single row of the SDRAM. Since successive eight macroblocks are disposed on the same row, video data of a one-slice is disposed in 128 columns by 15 rows in the SDRAM as shown in FIG. 6. The successive two slices are positioned on the same bank in the SDRAM. The successive four slices are disposed in 512 columns by 15 rows in the SDRAM. Then, the following successive four slices are disposed with the space of a one-row from the previous successive four slices. In other words, a one-row is spaced for every other successive four-slice arrangement. Accordingly, 255 row addresses are actually assigned to the one-frame video data among 272 row addresses represented as an equation R=16i+j where i is a natural number of 0-16 and j is a natural number of 0-14. That is, the video data having 68 slices S0-S67, i.e., the one-frame video data is disposed to match the size of the SDRAM as shown in FIG. 7. If video data is disposed in the SDRAM as shown in FIG. 7, the eight macroblocks contained in the four slices have the same row address in the SDRAM. FIG. 7 shows an arrangement of the slices of the video data in the SDRAM, and FIG. 8 shows a relationship between the row address and the word of the SDRAM with respect to the one-frame video data. The eight macroblocks having the same row address in FIG. 7 are represented as eight words having the same row address in FIG. 8. FIG. 9 is a conceptual diagram for explaining a predictive macroblock designated by a motion vectorin in integer units. In case when a motion vector represents even a half-pixel units, it is required that a predictive macroblock has video data having a horizontal one pixel and a vertical one line more than a macroblock having a size of 16 by 16 pixels, in performing motion compensation. In this case, the predictive macroblock has a size of horizontal two words and vertical 17 lines as shown in FIG. 10. When the vertical components of the motion vector are constant, and the horizontal components thereof vary in the range of 0 — 15, a predictive macroblock having a size of 17 by 17 is varied within the range of the predictive macroblocks designated by "P" and the neighboring hatched portions in FIG. 10. In this case, the macroblocks used for reading video data from the memory are not varied. Since the motion compensation technique using a motion vector of even a half-pixel unit is well known, the detailed description thereof will be omitted. FIGs. 11-13 are views for explaining a sequence of reading video data stored in the SDRAM in connection with various kinds of prediction. The video data having 8 words by 64 lines shown in FIGs. 11-13 has any one row address in FIG. 8. FIG. 11 shows a possible arrangement of a predictive macroblock with respect to a frame picture used for frame prediction. FIG. 12 shows- a possible arrangement of a predictive macroblock with respect to a frame picture used for field prediction. The example of FIG. 12 uses the same frame picture as that of FIG. 11, so that the macroblocks read for prediction are same as in FIG. 11. However, since prediction is accomplished in units of a field, data is read one line per two lines. FIG. 13 shows a field prediction embodiment in the field picture. A one-slice of the field picture occupies the same memory space as that of two slices of the frame picture. That is, the field picture is disposed in a single slice not two slices within the same row address and the bank address as those of FIG. 7. Thus, the video data of two lines with respect to a single word is read 17 times over 34 lines in FIG. 13. FIG. 14 is a timing diagram showing control commands resulting from combination of control input signals in the SDRAM. The control input signals are a chip select signal /CS for enabling the SDRAM, a row address strobe signal /RAS and a column address strobe signal /CAS respectively representing that an input address is an effective row address and column address, and a write enable signal AVE for recording data in a corresponding address. The control commands as shown in FIG. 14 such as a low active signal (a), a read signal (r), a write signal (w) and a precharge signal (p) are constituted according to combination of the control input signals. A series of control command signal composed of these control commands is used to control of the SDRAM. The operations of recording and reading video data to and from the SDRAM using these control command signal will be described below, referring to row addresses represented as an equation R=16i+j and column addresses represented as an equation C=128k+16/, where k is a natural number of 0 — 3 and / is a natural number of 0 — 7. FIG. 15 is a timing diagram for explaining a write operation of writing the motion-compensated macroblock video data on the SDRAM. In FIG. 15, the data of the twenty-seventh macroblock M26 in the fifth slice S4 is written in the position of the memory having the row address of 19 (=16x1+3) and the column address of 32 (=16x2). the one-macroblock video data is synchronized with 16 clock pulses and recorded on the corresponding positions in the SDRAM. A read operation of reading predictive macroblocks of the video data from the SDRAM will be described with reference to FIGs. 16A-16C. FIG. 16A is a timing diagram for reading a predictive macroblock A shown in FIG. 11. The FIG. 11 predictive macroblock A belongs to reference macroblocks having the same bank and row addresses. Accordingly, 34 data signals DQ[7..0] (=17 lines by 2 words) are read during generation of the 34 clock pulses, using commands such as a low active signal (a), a write signal (r) and a precharge signal (p) shown in connection with the predictive macroblock A in FIGs. 17A and 17B. Here, the first column address of the firstly read reference macroblock becomes 33 (=16x2 +1). The data of the sixteenth line in the predictive macroblock A belongs to a slice different from that of the fifteenth line. Thus, the column address of the sixteenth data becomes 160 (=128+16x2) not 46. If the sixteenth and seventh line data is completely read, the following word belonging to the predictive macroblock A is read, in which the column address becomes 49 (=16X3+1). FIG. 16B is a timing diagram for reading the predictive macroblock B of FIG. 11. The predictive macroblock B of FIG. 11 has one row address and two bank addresses as shown in FIGs. 17A and 17B, whose start column address becomes 163 (=128+16x2+3). Then, when the second word data belonging to the predictive macroblock B is read, the bank address is changed to thereby _start to read data, starting from data having the column address of 179 (=12+16x3+3). When data of the- line whose bank address is changed within the same predictive macroblock is read as in the data of the fourteenth line in the predictive macroblock B, the memory having a structure of a single bank reads 13 data signals and then requires the command of a low active signal (a) to read data starting from the data of the fourteenth line after receiving the command of a precharge signal (p). However, the present invention uses a SDRAM having two banks, to thereby send a command of a low active signal (a) for reading data recorded in the second bank during duration of the empty clock pulse between the read signal (r) and the precharge signal (p). That is, if such a bank structure is used when the bank alternates, a time consumed when data is read and written can be saved. FIG. 16C is a timing diagram for reading the predictive macroblock E of FIG. 11. The predictive macroblock E of FIG. 11 has different row addresses in two words as shown in FIGs. 17A and 17B. Therefore, the commands such as the low active signal (a), the read signal (r) and the precharge signal (p) are required in reading each word. Since the operation of reading the data belonging to the predictive macroblock E is understood by a person skilled in the art through the above-described examples, the detailed description thereof will be omitted. The above-described examples of FIGs. 16A-16C use the SDRAM which is designed in such a manner that a column address strobe signal /CAS lapses by three clock pulses before a data processing becomes effective. FIGs. 17A and 17B are tables showing variation of the row and bank addresses of each predictive macroblock shown in FIG. 11. FIG. 17A shows variation of the row addresses with respect to the control command's (a). FIG. 17B shows variation of the bank addresses with respect to the control commands (a), (r) and (p). Here, R represents a row address where a reading operation starts in the predictive macroblock. The predictive macroblock H of FIG. 11 has two words having different row addresses in which the bank address is changed in the middle' of the predictive macroblock. If a row address starting to read the predictive macroblock H is "R", when the bank address is changed from "1" to "0," the second commands (a), (r) and (p) are generated. In this case, the row address become "R+16". If the bank address is changed again into "1," the third commands (a), (r) and (p) are generated, in which case the row address becomes "R+l" which is larger by one than the first row address "R", Then, if the bank address is changed into "0," the fourth control commands (a), (r) and (p) are generated in which case the row address becomes R+16+1. If a row address is R[10..0], the row address in the frame prediction is as follows. R[ia.0J=Fp[i0..0]+Sp[6..2] x 16+Mp[6..3] Here, Fp represents a predictive frame address. Sp represents a predictive slice address and Mp represents a predictive macroblock address, which are expresses as the following equations. Sp[ ]=Sc[ ]+Vy[7..4], and Mp[ ]=Mc[ ]+Vx[7..4]. Here, Sc[ 3 and Mc[ 3 represent the current slice address and the current macroblock address, respectively. Vx[ ] and Vy[ 3 represent motion vectors of the horizontal and vertical components, respectively. The row is changed in units of the eight macroblocks. Thus, the row address is not influenced when the number of the blocks is less than eight. Also, the row is changed in units of the four slices, in which case the row address is not influenced when the number of the slices is less than four. The Sp[l] among the bits which are not used in the slice address is involved with the bank address. The Sp[0] and Mp[2..03 which are not used in the above-description are used as the column addresses, which will be described with reference to FIGs. 18A and 18B. In case of the filed prediction, the row address is as follows. R[10..0]=Fp[10..0]+Sp[5..1] x 16+Mp[6..3] FIGs. 18A and 18B are view showing how addresses of the column of the predictive macroblock correspond to those of an actual memory. FIG. 18A represents a case of the frame prediction. The column address of the predictive macroblock is composed of eight bits, in which four lower bits are used as the lower bits Vy[3..03 of the vertical motion vector. The fifth bit from the least significant bit (LSB) is used as the LSB Sp[0] of the predictive slice address, and the three higher bits are used as three lower bits Mp[2..3 of the predictive macroblock address. Ca is a counter value in which an initial column address of the predictive macroblock is received and the counter^value increases by one for every clock pulse at the interval of the control command (r). Also, Cb represents a column address of the actual memory corresponding to the counter value Ca, The fact that the column address of the actual memory is not equal to the counter value which increases by one, is due to the above-described video signal arrangement method according to the present invention. That is,., ^f*- the vertical motion vector becomes more than 16 lines resulting from incrementing the counter value by one, the slice address is varied. Then, after reading a one-word, the macroblock address increases by eight. However, the column address assigned to the actual memory changes the slice address after eight macroblocks each having 16 lines lapse. Taking the FIG. 11 predictive macroblock A as an example, the sixteenth data is read in synchronization with the sixteenth clock pulse. That is, the data of the 16 lines of the one-word is read when the counter value Ca is 16. However, the actual column address of the sixteenth line becomes one after the eight macroblocks lapse from the column address of the fifteenth line. Thus, the counter is required for making the initial value of the column address correspond to that of the actual memory. FIG. 18B shows how the column address of the predictive macroblock during the field prediction corresponds to that of the actual memory. As described with reference to FIGs. 11 and 13, the one slice of the field picture is assigned to the same memory region as that of the two slices in the frame picture. Thus, in case of the field picture, the boundary of the slice is same as that of the bank, which does not require the predictive slice address Sp[ ] shown in FIG. 18A. Thus, if the vertical motion vector becomes larger than 16 lines, the bank address is changed. Then, the least significant bit Cl2CO] in the column address of the memory is used for discriminating a top field and a bottom field. In the above-described embodiment of the present invention, the one-word is defined as horizontal 16 pixels of the one-frame. However, it is possible to constitute a one-word with two, four or eight pixels. As described above, the frame memory in the motion picture decoder according to the present invention is embodied using a SDRAM which can operate at high speed, in which the one-frame motion picture data is appropriately disposed in the SDRAM, to thereby enable processing complicated predictions of the motion compensation using a frame memory. While only certain embodiments of the invention have been specifically described herein, it will apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention. We Claim: 1. A method of recording a frame video signal on a synchronous dynamic random access memory (SDRAM) ,the video signal recording method comprising the step of: disposing vertical 16 lines of a one-macroblock to horizontal 16 columns in the SDRAM in which a video signal having a vertical one word and horizontal 16 lines in the one-frame video signal is defined as a one-macroblock. 2. The method of recording a one-frame video signal on a synchronous dynamic random access memory (SDRAM) as claimed in claim 1 wherein the step of disposing a one-slice video signal to a domain of 128 columns by N rows (N is a natural number) in the SDRAM, by changing and disposing the rows of the SDRAM for every other 8-macroblock. 3. The method of recording a one-frame video signal on a synchronous dynamic random access memory (SDRAM) as claimed in claim 2 wherein the step of disposing every 8-macroblock of 4 slices so that row addresses are identical to each other, by changing and disposing the bank of the SDRAM for every other 2-slice. 4. The method of recording a one-frame video signal on a synchronous dynamic random access memory (SDRAM) as claimed in claim 1 wherein said one word comprises two, four, eight or sixteen pixels horizontally in the one-frame video signal. 5. A method for recording a one-frame video signal substantially as herein described with reference to and as illustrated by the accompanying drawings.

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