Title of Invention


Abstract The large bandwidth available in Optical Fiber links can be exploited using digital pulse-position modulation (DPPM) to improve receiver sensitivity. Usually the digital signals are available in Pulse-Code-Modulated (PCM) form. For transmission of signals over fiber-optic links using DPPM, PCM-to-DPPM conversion is needed which usually involves parallel to serial conversion if the signal to be transmitted is a multi-bit parallel signal. A novel and in-expensive circuit for this purpose has been presented in this paper. The proposed circuit converts the multi-bit parallel PCM signal at its input to a serial DPPM signal at the output. The proposed circuit is modified at a very low cost to generate encrypted DPPM signal corresponding to the multi-bit parallel PCM signal The circuits for recovering the PCM signal at the receiver end have also been presented. The developed circuits can be attractive for commercial application in many communication and instrumentation systems.
Optical Fiber (O.F) communication systems are becoming popular for long-haul communication due to a multitude of reasons. Several PTT administrations have installed O. F. links for various inland and under-sea systems. With advanced single-mode fibers like dispersion shifted and dispersion flattened fibers coming in the market, and with the popularity of the optical fiber amplifiers, intensity modulated direct detection (IMDD) systems are becoming quite popular. A large bandwidth available with these systems is not fully exploited by existing PCM systems used for data transmission.
It has been proved that receiver sensitivity below 100 photons per binary bit can be achieved with direct detection using Digital Pulse Position modulation (DPPM), even at high data rates, thereby exploiting the large bandwidth offered by mono-mode fibers. DPPM systems over mono-mode fibers, thus offer much improved receiver sensitivity. Hence there has been a tendency to use DPPM instead of PCM wherever possible.
Since most of the modems for digital communication have been designed for PCM, a PCM-to-DPPM converter is required if DPPM is to be used for data transmission. Similarly, DPPM-to-PCM converter will be needed at the receiver end as most of the destination units operate on PCM

signals. Circuits reported in the literature for this purpose are usually complex (refer to IEEE Transactions on Communication, Vol. COM-31, No.4, pp. 518-525, 1983).
An optical fiber is increasingly becoming analogous to free space channel, as a large number of signals arc being transmitted simultaneously through the fiber by using various techniques. In view of the paramount importance of message security against eavesdropping, the encryption of signals before transmission through the optical fiber becomes, thus, very attractive.
In light of the above discussion, a simple technique for PCM-to-DPPM conversion has been invented. A 3-bit parallel PCM-message signal is directly converted into the corresponding DPPM signal, using the proposed circuit. Receiver circuit for DPPM-to-PCM conversion is also presented. The proposed circuit for PCM-to-DPPM conversion can be used to incorporate the encryption of the DPPM signal lor message security against eavesdropping, without using additional hardware. The resultant DPPM signal can be easily demodulated into the original PCM signal and the corresponding circuit for the demodulator has been presented. The experimental results obtained after simulating the proposed circuits on a digital computer using PSpice software have been presented. Since the circuits will be used as hardware modules for various commercial applications, hardware prototype models for the proposed technique have been developed using integrated circuits (ICs). Experimental results carried out over the hardware modules of the proposed circuits have been presented.
Fig. 1 shows the circuit diagram of the PCM-to-DPPM converter. 3-bit parallel PCM message words to be converted into the DPPM signal, are used as the control word or line select input of a l-to-8-line de-multiplexer (DMUX), as shown. For laboratory testing, message words used are generated by a specially designed counter (which generates eight 3-bit words) whose circuit/state
diagram is shown in Fig. 2. The output of DMUX is linearly multiplexed/scanned by an 8-to-l line multiplexer (MUX), whose control word or line select input is the 3-bit output of a -^8 linear counter. The DMUX and MUX are connected together by order of their line numbers as shown in Fig.l. The source-clock (CKS) used as the clock signal for the linear counter has a frequency

equal to 8 times that of the message-clock (CKM) so that the output of the DMUX remains unchanged during the period all of its 8 output lines are scanned by the MUX. The source-clock and the message-clock can thus he taken as shown in Fig. 1. Since the input to the DMUX is grounded (Fig. 1), a certain output line of the DMUX selected by a particular PCM message word, applied at the line select input of the DMUX, will become low or 0 whereas the rest of the output lines remain at high or at level-1, during the given message-bit-interval. As the MUX scans all the 8 output lines of the DMUX during one message bit interval, this arrangement divides each
«& pmessage bit interval into eight subintervals or time slots and generates, at the output of the MUX,fa narrow bit low-pulse on one of the eight time slots, while the output remains high for rest of the seven subintervals of the message-bit-period. The position of the selected time slot, to carry the low-pulse, in a given message interval, will be decided by the PCM word applied at the line-select input of the DMUX, corresponding to that message interval. Hence, the output of the MUX is the DPPM signal corresponding to the original PCM message signal.
Alternatively, binary serial PCM signals from three different message sources will be applied as the control word of the DMUX. In such a case the DPPM signal generated at the output of the PCM-to-DPPM converter embeds all the three input signals into a single output signal, thereby enabling multisignal transmission over a single channel.
If a guard-band between two consecutive message intervals in the DPPM signal is needed, as is the case in most of the applications, the arrangement shown in Fig. 3 is used, which is slightly modified form of that shown in Fig. 1. The arrangement shown in Fig. 3 divides each message bit interval into 10 sub-intervals and places a narrow-bit low pulse on any one of the first eight time slots and a guard-band (of high level, for a duration equal to two sub-intervals) at the end of the message bit interval.
Message security can be incorporated in the PCM-to-DPPM converter by simply interchanging the control bits or line select input So, Si, 82 of the MUX in Figs.l or 3. Alternatively a code converter can be used which converts the 3-bit output of the counter into a pseudo-random signal before it is applied to the MUX. An encrypted DPPM signal will, thus, be generated at the output of the MUX. The resultant circuit is an example of a Transposition Cipher, where the position of pulses
in the DPPM signal is changed in a non-linear manner. An unauthorized receiver will find it difficult to extract the correct information in the encrypted DPPM signal, so long as he does.not know the positions of control bits of the MUX or the code converter.
A specially designed counter, in which the output words are generated in a pseudo-random way can also be used in place of the linear counter in Figs.l or 3 for providing the message security. The specially designed counter known only to the transmitter and the authorized receiver thus defines the positions of the message bits in the corresponding encrypted DPPM signal.
Fig. 4 shows the circuit diagram of the DPPM-to-PCM converter corresponding to the PCM-to-DPPM converter shown in Fig. 1. The position of any pulse in the DPPM signal is read by using a 2-input AND gate with the inverted DPPM and the source-clock (CKS) signals as the inputs (as shown in Fig. 4). It is clear from Figs. (4) & (5) that when the AND gate output, VS, goes high, the count in the linear counter (in Fig.4) at that instant is the same as the PCM word applied at the transmitter input (in Fig.l). This count gets 'loaded' into the D-type latches by the leading edge of the sampling pulse VS. The output (m2, mi, mo) of the D-type latches can now be 'read', by the trailing edge of the sampling pulse, as the received 3-bit parallel PCM signal.
In case of the encrypted DPPM-to-PCM converter, the position of output bits of the linear counter at the receiver in Fig. 4 is interchanged in a way corresponding to that at the transmitter. Further, if a specially designed counter is used at the transmitter as proposed in section C, the same counter must be used at the receiver in Fig. 4. Note that the linear/specially-designed counter used at the receiver has to operate in synchronism with that used at the transmitter in case of encrypted as well as non-encrypted transmission.
Fig. 5 shows a plot of the experimental results obtained after simulating the PCM-to-DPPM converter, shown in Fig.l, using PSpice software. The circuit in Fig. 2 generates 3-bit parallel PCM message words used in the investigation. Waveforms generated at trie corresponding

receiver are also plotted in Fig. 5. CKS and CKM as shown in Fig. 5(a), are the source and message clocks, respectively, used in Fig.1. C, B and A, with A as the LSB, are the waveforms of 3-bit message used. The corresponding DPPM signal is also plotted in the figure
At the receiver, the sampling pulses are obtained by applying the inverted DPPM signal and the clock signal CKS to an AND gate, as shown in Fig. 4. The resultant sampling pulses are plotted as VS in Fig. 5(b). The output waveforms generated by the receiver are plotted as m2, nil and m0 (with m0 as LSB) in the figure. It is clear that at Ihe trailing edges of the sampling pulses, the received signal m2, m, and m0 is same as the corresponding transmitted PCM-signal C, B and A in a given message bit interval. The PCM output can thus be obtained by sampling the output signal m2, mi and m0 during the trailing edge of the sampling pulse VS. The results of computer simulation tests presented in Fig. 5 are obtained at a source clock frequency of 500 KHz.
Transmission and reception of encrypted DPPM signal using the proposed circuits is also worked out successfully in a similar manner.
Fig. 6 shows the results of a few tests carried out over the hardware modules of the proposed circuits. The photographs show waveforms of the encrypted DPPM signals corresponding to a typical 3-bit PCM message sequence. The message sequence at the corresponding receiver output is found to coincide with the corresponding transmitted sequence at the trailing edges of the sampling pulses. The circuits have been tested for various clock frequencies as shown in the figure.
Since DPPM has been popularly used for data communication over optical fiber links, many techniques for the DPPM signal generation are reported in literature. However, these techniques require complex circuitry at the transmitter and at the receiver. One of the widely used techniques has been reported by Ian Garrett in his research paper entitled "Pulse Position Modulation for Transmission over Optical Fibers with Direct or Heterodyne Detection" (IEEE Trans. On Communication, Vol COM-31, No.4, pp.525, 1983). The circuit for DPPM signal generation developed by Ian Garrett is outlined in Fig. 7. A comparison of the technique outlined in Fig. 7 with that proposed in this invention (Fig. 1) shows that the technique proposed herein is far less complex and thereby cheaper than its prior alternatives. Further, simple encryption can be incorporated in the proposed circuit without any additional hardware. Using comparatively lesser hardware, the propagation delay of the proposed circuit can be shown to be lesser than its counter parts, thereby providing larger speeds of operation.

We claim:
I A novel low-cost PCM-to-DPPM converter comprising of a l-to-8 line DMUX connected
to an 8-to-l line MUX, by order of their line numbers, wherein a 3-bit parallel PCM signal is applied at the line-select terminals of the DMUX with its single input terminal grounded, and a modulo-8 linear counter is used to generate the line-select input for the MUX wherein the MUX scans all the 8 output lines of the DMUX in a given message-bit interval, so that a DPPM signal is generated at the output of the MUX, corresponding to the applied PCM signal.
2. A PCM-to-DPPM converter as claimed in claim 1, wherein the positions of the line-select
inputs of the MUX are interchanged in order to generate an encrypted DPPM signal at the
output of the MUX, corresponding to the applied PCM signal.
3. A PCM-to-DPPM converter as claimed in claims I or 2 wherein a suitable guard-band
between the adjacent DPPM pulses can be provided by using a higher order MUX
(compared to DMUX) and keeping the additional input lines of the MUX at logic 1.
4. A PCM-to-DPPM converter as claimed in any of the claims 1 to 3 wherein the clock
driving the modulo-n linear counter is n times the message clock and that the message
clock is obtained from the linear counter.
5. A PCM-to-DPPM converter as claimed in any of the claims 1 to 4 wherein the DPPM
signal generated can be demodulated into original PCM signal by obtaining sampling
pulses from the DPPM signal itself using bubled AND gate and then latching the output
state of a linear counter, similar to that used in the PCM-to-DPPM converter, at the
sampling intervals.


Patent Number 196826
Indian Patent Application Number 1076/DEL/2003
PG Journal Number 37/2008
Publication Date 12-Sep-2008
Grant Date 16-Mar-2007
Date of Filing 01-Sep-2003
# Inventor's Name Inventor's Address
PCT International Classification Number H03K 11/00
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA