Title of Invention

A RAKE RECEIVER FOR RECEIVING A DATA SIGNAL TRANSMITTED FROM A TRANSMITTER IN A SPREAD SPECTRUM COMMUNICATION SYSTEM

Abstract

A RAKE receiver for receiving a data signal transmitted from a transmitter in a spread spectrum communication system comprises a symbol combiner having an adder for adding Walsh index output values, sequentially generated from a correlator using a fast Walsh transform algorithm according to N Walsh code sequences, to a value generated from a last stage of an N-stage shift register, and having the N-stage shift register for shifting an accumulated value of an output of a RAKE receiver corresponding to each index for a Walsh symbol generated from the adder each time a rake is assigned to each finger. The RAKE receiver also comprises a first decision logic unit for determining a maximum value by sequentially sorting an output of the symbol combiner and generating a Walsh index corresponding to the determined maximum value as a code word; and a second decision logic unit for sorting and substracting the output of the symbol combiner according to a state of each bit of a corresponding index and generating a probability value for the code word.

Full Text

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CDMA (Code Division Multiple Access) communication technique in a cellular radio telephone communication system and, more particularly, to a RAKE receiver for receiving a data signal , transmitted from a transmitter in a spread spectrum communication system . 2. Description of the Related Art In a spread spectrum system, if a spread spectrum signal passes through a multipath fading channel, a received signal appears as a form obtained by adding components of paths each having a different amplitude and phase to each other. In this case, it is not preferable in an aspect of power efficiency to receive only one main path signal having the strongest power since power components of other multipath signals are lost. In a RAKE receiver, plural receivers of a parallel form are used as shown in Fig. 1 in order to unitedly take part in demodulation without losing these power components of the multipath signals. Outputs of the receivers are combined through a combiner. A concept diagram shown in Fig. 1 is described in the book "SYNCHRONOUS DIGITAL COMMUNICATION", pp. 353-354, issued on Jul. 20, 1995 by KYOHAKSA, Inc. A time interval between multipath receivers is variable, and the multipath power component is demodulated with a delay time ti through a tapped delay line (TDL) etc. The delay time ti is dynamically adjusted by an additional control circuit. Such a construction maximizes a SNR (Signal-to-Noise Ratio) of an output signal of the RAKE receiver. Although the RAKE receiver is very favorable in the efficient use of a signal power, there is a limit to the number of parallel circuits since many additional hardware constructions are required. The RAKE receiver is based on the principle that if a spectrum width of a signal at a frequency selective fading channel is greater than a delay spread value, it is possible to classify signal components into independently faded components according to several spectrums. If the number of parallel hardware circuits is greater than the number of actual paths, the performance of the RAKE receiver is degraded. If the strength values of powers between the actual paths are similar to or equal to each other, the RAKE receiver shows the maximum performance. Meanwhile, U.S. Pat. No. 5,237,586, issued on Aug. 17, 1993, entitled "RAKE RECEIVER WITH SELECTIVE RAY COMBINING" describes a RAKE receiver including multipliers for multiplying outputs of a fast Walsh -2- transformer by a weight, accumulators for accumulating outputs of the multipliers and a decision device for detecting a received code word on a basis of outputs of the accumulators. In operation, a descrambler descrambles (or despreads) a received sample. A single correlator calculates result values corresponding to each Walsh index by using FWT (Fast Walsh Transform). The multipliers multiply the result values by complex weights, and the accumulators accumulate the outputs of the multipliers. The accumulated values are supplied to the decision device. The decision device sequentially sorts the accumulated values and determines the Walsh index having a maximum value as the received code word. However, since the RAKE receiver disclosed in the aforementioned U.S. Pat. No. 5,237.586 uses an additional accumulator with respect to each Walsh index, there are needed a lot of hardware circuits. Further, since the decision device generates only the Walsh index having the maximum value, the above RAKE receiver leaves much to be desired in search (indicating an operation for determining a signal component, that is, a pseudo noise phase component to be demodulated by demodulator fingers within the RAKE receiver) performance. SUMMARY OF THE INVENTION It is therefore an object of the invention to provide a RAKE receiver for reducing the consumption of hardware without deteriorating processing performance. It is another object of the invention to provide a RAKE receiver for -3 - reducing the consumption of hardware and improving search performance without deteriorating processing performance. In one aspect of the invention, a RAKE receiver for receiving a data signal transmitted from a transmitter in a spread spectrum communication system includes: a symbol combiner having an adder for adding output values of Walsh indexes which are sequentially generated from a correlator using a fast Walsh "transform algorithm according to N Walsh code sequences to a value generated from a last stage of an N-stage shift register, and having the N-stage shift register for shifting an accumulated value of an output of a RAKE receiver corresponding to each index of a Walsh symbol generated from the adder each time a rake is assigned to each finger; a first decision logic portion for determining a maximum value by sequentially sorting an output of the symbol combiner and generating a Walsh index corresponding to the determined maximum value as a code word; and a second decision logic portion for sorting and subtracting the output of the symbol combiner according to a state of each bit of a corresponding index and generating a probability value of the code word. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS The above and other objects, features and advantages of the invention will be more clearly understood from the following detailed description when read with the attached drawings in which: Fig. 1 is a concept diagram of a general RAKE receiver; Fig. 2 is a functional block diagram of a RAKE receiver in accordance with the present invention; -4- Fig. 3a is a table showing size values corresponding to 8 Walsh indexes; and Fig. 3b shows operation implementation of a soft-decision logic portion indicated in Fig. 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In the present invention, a RAKE receiver and a symbol combiner thereof used to cope with the distortion of a signal caused by many paths in radio circumstances are improved. The RAKE receiver compensates different arrival delay time while information sent from a transmitter arrives at a receiver via different paths by various causes such as whether, terrain, etc. To this, the RAKE receiver receives not only a signal having the strongest strength but various signals of paths having different delay time and adds theses signals to each other, thereby raising receiving sensitivity. Fig. 2 is a functional block diagram of a RAKE receiver in accordance with the present invention. In Fig. 2, an RF (Radio Frequency) receiver 31, an I (in-phase) sample buffer 32a, a Q (quadrature) sample buffer 32b, a multiplexer 33, a descrambler 34, a single correlator 35, complex multipliers 36-1 to 36-N are the same construction as a corresponding block construction shown in Fig. 11 of The above U.S. Pat. No. 5,237,586 >nd perform a similar operation. That is, a composite signal is received and sampled by the RF receiver 31 and generated as I and Q samples. The I and Q samples are buffered in the I and Q buffers 32a and 32b, respectively. If a regular RAKE approach is used, the multiplexer 33 selects ranges of samples which need not correspond -5 - to different I and Q components. If a limited RAKE approach is used, the multiplexer 33 selects ranges of I and Q samples. In both cases, the selected sample ranges are independent of each other. The descrambler 34 eliminates a scrambling code from the samples either by inverting each sample or not, depending on the bit polarity of the scrambling code. The samples are transmitted in parallel to the single correlator 35. The single correlator 35 simultaneously correlates the samples with several known code sequences using a FWT algorithm. The correlation results are multiplied by complex weights in the multipliers 36-1 to 36-N. In the RAKE receiver shown in Fig. 11 of the above U.S.Pat. No. 5.237,586,accumulators are connected to the multipliers 36-1 to 36-N and a decision device is connected to the accumulators. In a preferred embodiment of the present invention, since the correlator 35 uses the FWT algorithm of N Walsh code sequences (Walsh-Hadamard = N), N outputs of the correlator 35 correspond to N Walsh indexes. For example, if the Walsh-Hadamard is 8, there are 8 Walsh indexes. Unlike the abovelU.S. Pat. No. 5,237,586) the RAKE receiver according to the present invention has a symbol combiner 40, a hard-decision logic portion 48 and a soft-decision logic portion 50 which are connected after the multipliers 36-1 to 36-N. The symbol combiner 40 includes an adder 42, a saturation logic portion 44, and a shift register 46 consisting of N registers, and combines received symbols with one another. The adder 42 adds output values of the multipliers 36-1 to 36-N to a value generated from an N-th register REG N of the shift register 46. The saturation logic portion 44 saturates an output value of the adder 42 so as not to exceed a preset maximum value. An output of the -6- saturation logic portion 44 is applied to a first register REG 1 of the shift register 46. Each of the registers REG 1 to REG N of the shift register 46 include an accumulated value of a RAKE receiver output corresponding to each index of a Walsh symbol. The hard-decision logic portion 48 and the soft-decision logic portion 50 are connected to an output of the first register REG 1 of the shift register 46. The hard-decision logic portion 48 determines a maximum value by sequentially sorting the output of the first register REG 1 of the shift register 46 within the symbol combiner 40, and generates the Walsh index corresponding to the determined maximum value as a code word. The hard-decision logic portion 48 includes a comparison and storage portion 60, a maximum value register 62 and an index register 64. The soft-decision logic portion 50 sorts and subtracts the output of the first register REG 1 of the shift register 46 within the symbol combiner 40 according to a state of each bit of a corresponding index, and generates a probability value of the code word. The soft-decision logic portion 50 has m (= log2N) decision logic portions 50-1 to 50-m, m being the number of bits constituting each Walsh index. Each of the decision logic portions 50-1 to 50-m includes first and second comparison and storage portions 100 and 104, first and second registers 102 and 106, and a subtracter 108. The first comparison and storage portion 100 determines a maximum value by sequentially sorting a corresponding output value according to binary logic "0" of the constituent bits, and stores the determined maximum value in the first register 102. The second comparison and storage portion 104 determines a maximum value by sequentially -7- sorting a corresponding output value according to binary logic "1" of the constituent bits, and stores the determined maximum value in the second register 106. If the Walsh symbol of one period is processed, the subtracter 108 subtracts the value stored in the second register 106 from the value stored in the first register 102 and generates result values R1-Rm. The result values R1-Rm are standards indicating a probability of the code word determined in the hard-decision logic portion 48. Sign values S1-Sm of the result values R1-Rm are equal to the code word. An operation of the RAKE receiver according to the present invention will now be described in detail. For convenience, it is assumed that the Walsh-Hadamard is 8. In a typical CDMA system, the Walsh-Hadamard is 64. Figs. 3a and 3b are depicted to describe the operation of the soft-decision logic portion 50. Fig. 3a is a table showing size values corresponding to 8 Walsh indexes. Fig. 3b shows operation implementation of the soft-decision logic portion 50. The size values of the Walsh symbols corresponding to the Walsh indexes of the correlator 35 are shown in Fig. 3a. The Walsh symbols corresponding to the Walsh indexes are multiplied by the weights in the multipliers 36-1 to 36-N. The multiplied results are sequentially applied to the adder 42. The adder 42 adds the size values of the Walsh symbols to the value generated from the N-th register REG N of the shift register 46. Since it is assumed that there are 8 Walsh indexes, the shift register 46 has 8 registers. Therefore, two input sources added in the adder 42 are a symbol size value of a previous rake of a -8- corresponding index and a symbol size value of a current rake. The result obtained from the adder 42 is supplied to the saturation logic portion 44. Since the result of the adder 42 is obtained by repeatedly adding the symbol size values for various rakes, an overflow may be generated. If the output of the adder 42 exceeds a preset maximum value, the saturation logic portion 44 replaces the output value of the adder 42 with the maximum value. The output of the saturation logic portion 44 is applied to the first register REG 1 of the shift register 46. An enable signal EN is supplied to the first to N-th registers REG 1 to REG N of the shift register 46 each time the rake is assigned to a finger. The shift register 46 right-shifts the accumulated value whenever the enable signal EN is applied. As a result, the registers REG 1 to REG N of the shift register 46 has the accumulated value of an output of the RAKE receiver corresponding to each index of the Walsh symbol. The output of the first register REG 1 of the shift register 46 is applied to the soft-decision logic portion 50. The output of the first register REG 1 of the shift register 46 is also applied to the comparison and storage portion 60 of the hard-decision logic portion 48. For example, as indicated in Fig. 3, the size values 3, 7, 5,...,1 and 2 corresponding to the Walsh indexes are sequentially supplied to the comparison and storage portion 60. The comparison and storage portion 60 of the hard-decision logic portion 48 compares a previous size value with a current size value and stores a larger value in an internal storage porion. For instance, if a size value 3 of a Walsh index 000 is compared with a size value 7 of a Walsh index 001, the size value 7 is stored in the internal storage portion. In this case, the index 001 of the larger value 7 is also stored in the internal storage portion. If such a process is repeated for one period, a maximum -9- size value Vmax and the index corresponding thereto are stored in the internal storage portion. Referring to Fig. 3a, the maximum size value Vmax is 20 and its index is 100. The maximum size value Vmax is temporarily stored in the maximum value register 62 and the index 100 corresponding thereto is temporarily stored in the index register 64. The index which is temporarily stored in the index register 64 corresponds to the code word. Meanwhile, the size values corresponding to the Walsh indexes of bits B0, Bl and B2 having binary logic "0" among the output values of the first register REG 1 of the shift register 46 are sequentially applied to each first comparison and storage portion 100 of first to m-th (where m is 3) logic portions 50-1 to 50-m of the soft-decision logic portion 50. For example, the size values 3, 5, 20 and 1 corresponding to the Walsh indexes of the least significant bit (LSB) B0 having binary logic "0" are sequentially supplied to the first comparison and storage portion 100 of the first logic portion 50-1. The size values 3, 7, 20 and 4 corresponding to the Walsh indexes of the bit B1 having binary logic "0" are sequentially supplied to the first comparison and storage portion 100 of the second logic portion 50-2. The size values 3, 7, 5 and 6 corresponding to the Walsh indexes of the most significant bit (MSB) B2 having logic "0" are sequentially supplied to the first comparison and storage portion 100 of the third logic portion 50-3. Each first comparison and storage portion 100 of the logic portions 50-1 to 50-3 compares the previous output value with the current output value and stores the larger value in an internal storage portion. The maximum size values 20(B0), 20(B1) and 7(B2) of binary logic "0" determined for one period are temporarily stored in each first register 102 of the logic portions 50-1 to 50-3, respectively. The size values corresponding to the Walsh indexes of the - 10- bits B0, B1 and B2 having binary logic " 1" among the output values of the first register REG 1 of the shift register 46 are sequentially applied to each second comparison and storage portion 104 of the logic portions 50-1 to 50-3 of the soft-decision logic portion 50. The second comparison and storage portion 104 and the second register 106 of the logic portions 50-1 to 50-3 are similar in operation to the first comparison and storage portion 100 and the first register 102. The maximum size values 7(B0), 6(B1) and 20(B2) of binary logic "1" determined for one period are temporarily stored in each second register 106 of the logic portions 50-1 to 50-3, respectively. The maximum size values which are temporarily stored in the first register 102 and the second register 106 according to each binary logic state "0" or "1" of the bits B0, Bl and B2 of the Walsh index are shown in Fig. 3b. Each subtracter 108 of the logic portions 50-1 to 50-3 subtracts the value stored in the second register 106 from the value stored in the first register 102 and generates the result values R1-R3. Referring to Fig. 3b, the result values are as follows: Rl = + 13, R2= + 14, and R3=-13. The result values R1-R3 indicate the probability of the code word determined in the hard-decision logic portion 48. The larger the size of the result value is, the higher the probability of the code word has. If the result value is a positive number, the sign value is "0", and if it is a negative number, the sign value is "1". Therefore, the sign values S1-S3 are 0, 0 and 1 which are equal to the code word (B0=0, B1=0 and B2=l). The output values R1, S1 to R3, S3 of the soft-decision logic portion 50 speed up a determination for a signal component to be demodulated. That is, the soft-decision logic portion 50 raises search performance. - 11 - The outputs of the hard-decision logic portion 48 and the soft-decision logic portion 50 are applied to a subsequent signal processor, a channel decoder for example. The channel decoder determines the signal component to be demodulated by using the outputs of the hard-decision logic portion 48 and the soft-decision logic portion 50, and demodulates the signal component. As may be apparent from the aforementioned description, the RAKE receiver is useful in the consumption of hardware without lowering processing performance. For example, if 64 Walsh codes are used, a conventional RAKE receiver requires 64 accumulators. However, the illustrated preferred embodiment of the present invention uses only one accumulator and does not lower a processing speed. Moreover, since the present invention utilizes soft-decision, the search performance is improved. While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. - 12- WE CLAIM: 1. A RAKE receiver for receiving a data signal transmitted from a transmitter in a spread spectrum communication system comprising: a symbol combiner (49) for combining transmitted symbols, said symbo1 combiner comprising; an adder (42)for adding Walsh index values to a value generated by a last stage of an N-stage shift register (46), wherein the Walsh index values are sequentially generated by a correlator (35) using a fast Walsh transform algorithm according to N Walsh code sequences; and said N-stage shift register (46) for shifting an accumulated value of an output of the RAKE receiver corresponding to each Walsh index value generated by said adder (42) each time a rake is assigned to each finger; a first decision logic unit (48) for determining a third maximum value by sequentially sorting an output of said symbol combiner and generating a Walsh index corresponding to the determined maximum value as a code word; and a second decision logic unit (50) for sorting the output of said symbol combiner according to first and second binary logic states of each bit of a corresponding Walsh index to determine first and second maximum values and subtracting the first and second maximum values to generate a probability value for said code word. 13. 2. The RAKE receiver as claimed in claim 1, wherein said symbol combiner additionally comprises a saturation logic unit connected between said adder and said N-stage shift register, and wherein said saturation logic saturates an output value of said adder so as not exceed a maximum value. 3. The RAKE receiver as claimed in claim 1, wherein said second decision 1ogic unit comprises M decision logic units, wherein M is the number of bits of said Walsh index, wherein each of the M decision logic units comprises: a first maximum value determiner for determining the first maximum value by sequentially sorting an output value of said symbol combiner according to a first binary logic state of a corresponding bit of the output value; a second maximum value determiner for determining the second maximum value by sequentially sorting the output value of said symbol combiner according to a second binary logic state of the corresponding bit of the output value; a substractor for substracting the second maximum value of said second maximum value determiner from the first maximum value of said first maximum value determiner. 4. The RAKE receiver as claimed in claim 3, wherein said output of the symbol combiner is an output of a first stage of the hostage shift register. 14. 3. The RAKE receiver as claimed in claim 3, wherein said first decision 1ogic unit comprises; a third maximum value determiner -for determining the third maximum value by sequentially sorting said output value of said symbol combiner; a maximum value storage unit for storing and outputting a size of the determined third maximum value as a size of the code word; and an index storage unit for storing and outputting the Walsh index corresponding to the value having the determined third maximum value. 6. The RAKE receiver as claimed in claim 5, wherein said output of the symbol combiner is an output of a first stage of the N— stage shift register. 7- A method for receiving a data signal transmitted from a transmitter, comprising the steps of: (a) combining symbols transmitted to the transmitter, the step of combining additionally comprising: to a finger; 15. (b) determining third maximum value by sequentially sorting the shifted added index values and generating an index corresponding to the third maximum value as a code word; and (c) sorting the shifted added index values according to first and second binary logic states of a bit of the corresponding index to determine the first and second maximum values and subtracting the first and second maximum values thereby generating a probability value of said code word. 8. The method as claimed in claim 7 wherein said transform algorithm is a fast Walsh transform algorithm and the index values are Walsh index values. 9. The method as claimed in claim 8 wherein said transform algorithm generates the Walsh index values according to N Walsh code sequences, where N is an integer. 10. The method as claimed in claim 8, wherein said generating an index corresponding to the third maximum value as a code word comprises: (bl) storing and outputting a size of the third maximum value as a size of the code word; and (b2) storing and outputting the Walsh index corresponding to the value having the third maximum value. 16. 11. The method as claimed in claim 7 comprising: (d) providing a saturated output value as the added index value so as not to exceed a maximum value when adding the index values. 12. The method as claimed in claim 7, wherein said generating a probability value comprises: (cl) determining the second maximum value by sequentially sorting the shifted added index values according to a second binary logic state of the corresponding bit of the output value; and (c2) substracting the second maximum value from the first maximum value, thereby producing the probability value for said code word. 17. A RAKE receiver for receiving a data signal transmitted from a transmitter in a spread spectrum communication system comprises a symbol combiner having an adder for adding Walsh index output values, sequentially generated from a correlator using a fast Walsh transform algorithm according to N Walsh code sequences, to a value generated from a last stage of an N-stage shift register, and having the N-stage shift register for shifting an accumulated value of an output of a RAKE receiver corresponding to each index for a Walsh symbol generated from the adder each time a rake is assigned to each finger. The RAKE receiver also comprises a first decision logic unit for determining a maximum value by sequentially sorting an output of the symbol combiner and generating a Walsh index corresponding to the determined maximum value as a code word; and a second decision logic unit for sorting and substracting the output of the symbol combiner according to a state of each bit of a corresponding index and generating a probability value for the code word.

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00139-cal-1998 abstract.pdf

00139-cal-1998 claims.pdf

00139-cal-1998 correspondence.pdf

00139-cal-1998 description(complete).pdf

00139-cal-1998 drawings.pdf

00139-cal-1998 form-1.pdf

00139-cal-1998 form-2.pdf

00139-cal-1998 form-3.pdf

00139-cal-1998 form-5.pdf

00139-cal-1998 pa.pdf

00139-cal-1998 priority document others.pdf

00139-cal-1998 priority document.pdf

139-cal-1998-granted-abstract.pdf

139-cal-1998-granted-claims.pdf

139-cal-1998-granted-correspondence.pdf

139-cal-1998-granted-description (complete).pdf

139-cal-1998-granted-drawings.pdf

139-cal-1998-granted-examination report.pdf

139-cal-1998-granted-form 1.pdf

139-cal-1998-granted-form 2.pdf

139-cal-1998-granted-form 3.pdf

139-cal-1998-granted-form 5.pdf

139-cal-1998-granted-letter patent.pdf

139-cal-1998-granted-pa.pdf

139-cal-1998-granted-priority document.pdf

139-cal-1998-granted-reply to examination report.pdf

139-cal-1998-granted-specification.pdf

139-cal-1998-granted-translated copy of priority document.pdf