Title of Invention	A NOVEL , HIGH THROUGHPUT PLASMA ETCHING PROCESS FOR TEXTURING OF SILICON WAFERS
Abstract	A novel, high throughput plasma etching process for texturing of silicon wafers for texturing and plasma damage removal of silicon wafers, by introducing process gas mixture (SF6 and O2) in the chamber through MFCs (Mass Flow Controller) in a predetermined ratio and setting RF (Radio frequency) power to a predetermined value and switching on the matching network control in automode. The plasma etching process is carried out after premixing the etching gases and in that the gas mixture is uniformly distributed over the silicon wafers mounted on the carrier plate, using a showerhead electrode.

Title of Invention

A NOVEL , HIGH THROUGHPUT PLASMA ETCHING PROCESS FOR TEXTURING OF SILICON WAFERS

Abstract

A novel, high throughput plasma etching process for texturing of silicon wafers for texturing and plasma damage removal of silicon wafers, by introducing process gas mixture (SF6 and O2) in the chamber through MFCs (Mass Flow Controller) in a predetermined ratio and setting RF (Radio frequency) power to a predetermined value and switching on the matching network control in automode. The plasma etching process is carried out after premixing the etching gases and in that the gas mixture is uniformly distributed over the silicon wafers mounted on the carrier plate, using a showerhead electrode.

Full Text	FIELD OF INVENTION: Solar cells are fabricated from multicrystalline silicon wafers (mc-si). One of the essential requirements for high efficiency solar cells is minimization of the reflection of incident light from its front surface for enhanced light harvesting. The present invention relates to development of a novel high throughput plasma etching process for texturing multicrystalline silicon wafers (mc-Si) and their application in solar cell fabrication. BACKGROUND OF THE INVENTION; Plasma etching provides a stress-free method suitable for texturing thin silicon wafers, independent of crystal orientation, for obtaining isotropically texturised mc-Si surface that is not possible with wet alkaline method used for texturing monocrystalline silicon wafers. In recent publications on the subject, improvement in efficiency of mc-Si solar cells has been reported using plasma texturing process when compared to other methods of surface texturing. The improvement in efficiency of mc-Si solar cells has been attributed to: a) complete suppression of reflectivity ( broad spectral range (300-1000 nm) leading to black silicon surface, b) implementation of the texturing process in the chemical etching dominated mode that results in reduced surface damage or additionally performing defect removal etching and c) passivation of the surface and bulk defects in silicon by the PECVD deposited silicon nitride AR coating film. Using optimum ratios of flow rates of SF6 and O2 etch precursors under the influence of 13.56 MHz RF power and pressure-electrode gap combination, a reaction byproduct causing self-masking was created on the surface of mc-Si wafer to give random etching, independent of the crystal orientation. This random etching of silicon surface lead to wavelength scale nanostructures (typical size: 150-200 nm) exhibiting enhanced light harvesting property. The high throughput of the texturing process was realized through a custom designed, three chamber industrial system (one process and two load lock chambers) suitable for processing 20 wafers per batch (each of 156 mm sq. size). The uniformity in texturing was obtained by introducing innovative features like, premixing of process gases (high molecular weight SF6 gas with low molecular weight O2 gas through a gas blender) and uniform distribution of premixed gasses to obtain uniform plasma over the entire wafer carrier (Si2e:~0.7 m2)was carried out through a showerhead electrode. A process invention (Ref: Patent application No. 768/KOL/2007 A, Date of filing application: 18/05/2007) disclosing a self-masking, low energy, RIE (Reactive Ion Etching) plasma process for surface texturing of 125 mm sq mc-Si wafers for use in solar cell is in the process of granting the patent. SF6 and O2 gas mixture under 13.56 MHz RF power, produces reactive ions responsible for random surface etching of silicon wafers called texturing. The process resulted in formation of nanostructures with size comparable to wavelength of incident light exhibited efficient light trapping and facilitated enhanced surface passivation due to hydrogen released by PECVD SiNx. The wafer surface was polished with alkali solution essential for initiating texturing process on damage-free surface to get optimum quality solar cell emitter. Use of minimum RF power density and mounting of the wafer on grounded carrier plate lead to a damage- free textured surface of the wafer. Further, wafer surface was treated with acid based damage removal etch to eliminate possibility of any plasma damaged textured surface. The overall outcome of the multicrystalline silicon texturing process lead to an improved solar cell efficiency upto 15.1% for 125 mm sq size, which is 2.4% absolute higher compared to the one without RIE texturing. In the prior art, a) the process gases were fed to the plasma chamber without premixing leaving a room for non-uniformity of plasma precursors and b) the gas mixture was not uniformly delivered over the silicon wafers mounted on the carrier plate acting as a ground electrode. In the present invention the plasma etching process is carried out after premixing the etching gases and the gas mixture was uniformly distributed over the silicon wafers mounted on the carrier plate, using a showerhead electrode. Due to inclusion of these additional processes, it is possible to texture 20 silicon wafers of size upto 156 mm sq. per batch. The objects of the present invention is to disclose a high throughput plasma texturing process capable of producing 20 textured wafers per batch each of 156 mm sq. size with consistently uniform texturisation, low reflection and damage-free surface suitable for solar cell applications. The present invention discloses set of process parameters creating specific condition of self-masking due to in-situ formation of randomly absorbed polymer giving rise to selective etching of silicon, yielding least reflecting, uniformly textured wafers placed over the entire carrier. To reduce the etching damage of the silicon wafers, wafer carrier was grounded and hence process done in chemical etching dominated mode. Inventive feature of the present invention lies in:- Introduction of gas blending process resulting in an uniform mixture of process gases viz., SF6 and O2. Maintaining uniform flow of premixed gases over 20 silicon wafers each of 156 mm x 156 mm size, mounted on a SS carrier, by introducing a showerhead electrode coupled with the wafer carrier designed to exhaust the residual gases uniformly. Enhanced plasma stability and uniformity leading to uniform texturing and a throughput of 20 wafers per batch by introducing independent RF earthing system and excellent matching network. A combination of process parameters (given in detailed Technical write up) resulting in a product called, plasma textured silicon wafer (size: 125 mm sq. or 156 mm sq.) with reduced average reflectance ~ 8% forming an input to solar cell process exhibiting cell efficiency. For example, solar cells processed out of the plasma textured multicrystalline silicon wafers showed efficiency upto 15.6% and the improvement achieved in average efficiency of the solar cell is upto 1.5% higher compared to the one without plasma texturing. SUMMARY OF THE INVENTION; The present invention discloses a novel, high throughput plasma etching process for texturing multicrystalline silicon wafers and its application in solar cell fabrication. The process was carried out in a custom designed multichamber plasma etching system. Features of the system resulting in novel high throughput plasma etching process include, uniform distribution of premixed gases to obtain uniform plasma over the entire wafer carrier (Size: ~0.7m2) by using showerhead electrode for gas distribution, grounding of the wafer carrier to minimize the sputter damage due to accelerated radicals/ions in the plasma, and use of PLC based SCADA automation system for process operation. Using optimum flow rates and ratio of SF6 and O2 etch precursors under the influence of 13.56 MHz RF power and combination of pressure-electrode gap, a reaction causing self- masking on the surface of mc-Si wafers was created to give random etching independent of crystal orientation. This random etching of silicon surface lead to wavelength scale nanostr.uctures (typical size: 150-200 nm) exhibiting enhanced light harvesting property. A number of process experimentation runs were carried out by varying critical process parameters for achieving optimum surface texturing of mc-Si wafers of size 125 mm sq. and 156 mm sq. The average reflectance measured was -8.4% on more than 100 textured wafers after carrying out damage removal etching (DRE) process. Theses plasma textured mc-Si wafers were processed for cells using standard manufacturing steps. Current-Voltage characteristics of the plasma textured cells under standard test conditions show highest conversion efficiency of 15.6% whereas that for cells without plasma texturing it was 13.9%, clearly showing an improvement of 1.7% absolute in efficiency. ACCOMPAYING DRAWINGS; Fig.l. A view of the three-chamber Plasma Etching System for texturing of mc-Si wafers. Fig.2. Photographs of the 20 silicon wafers loaded in the carriers, a) left side: saw damage removed wafers kept in the loading station, b) right side: Plasma textured wafers kept in the unloading station. Fig.3. A view of process chamber showing plasma of sulphur hexafluoride and oxygen process gases. Fig.4. Run chart for diffused reflectance of mc-Si wafers after plasma texturing and damage removal etching (DRE). Fig.5. Histogram distribution of efficiency of the mc-Si solar cells processed in a manufacturing line using mc-Si wafers with and without plasma texturing. Fig.6. Current-Voltage characteristics of mc-Si solar cells with and without plasma texturing. Fig.7. SEM micrographs of sample plasma textured Silicon wafers at different magnifications a) 3,000X b) 10,000X. Fig.8. Microscope image of sample RIE textured mc-Si wafer (Magnification: 2000X) Fig.9. Typical surface profile of a plasma textured wafer. Fig.10. Quantum efficiency measurements on typical mc-Si solar cells with and without plasma texturing. Fig.11. Photographs of solar cells: with (Left side) and without (Right side) plasma texturing. Fig.12. Schematics of plasma texturing system used in Plasma texturing process. Fig.13. Schematic of the shower head electrode showing four capillaries for four silicon wafers for simplicity. Fig.14. Process Flow in Solar cell fabrication. DEATILED DESCRIPTION OF THE INVENTION: The invention will now be described in an exemplary embodiment as depicted in the accompanying drawing. There can however be other embodiments of the same invention, all of which are deemed covered by this description. The present invention relates to development of a high throughput plasma etching process suitable for uniform texturing of 20 silicon wafers for use in high efficiency solar cell process. The process was carried out in a custom designed industrial three chamber plasma etching system comprising a process chamber and two load lock chambers placed on both sides of the process chamber to avoid possible contamination to wafers due to atmospheric or other exposure. Loading and unloading stations for wafer carrier were provided to facilitate the start up and completion of the process cycle. Fig.1. shows a view of the three-chamber Plasma Etching System having essential accessories, like mass flow controllers (MFCs) for monitoring and maintaining the gas flow in the process chamber, customized gas blender for premixing of process gases, pressure gauges to monitor pressure of the process chamber and load-lock chambers to facilitate on-line transfer of wafer carrier across the vacuum chambers and their entry to and exit from the chambers, vacuum pumps for evacuating residual gases and reaction byproducts from the process chamber and equalization of chamber pressure during carrier transfer, custom designed showerhead electrode for effective uniform distribution of process gases across the entire wafer carrier, RF power supply and matching network for splitting the precursor gases into etch radicals and ions, 'o' ring sealed slit valves to avoid cross contamination within chambers and from outside environment, variable frequency drive (VFD) motors for transport of wafer carrier and PLC based process automation and SCADA monitoring system for process operation etc. are integrated with the system. Fig.2. a) On left side: gives photographs of the wafer carrier placed in the loading station, with 20 mc-Si wafers after saw damage removal, whereas in b) on right side: textured mc-Si wafers kept in the unloading station are shown. Fig.3. illustrates a view of process gas plasma (Sulphur Hexafluoride and Oxygen) in the process chamber. Process optimization runs for texturing silicon wafers of size up to 156 mm x 156 mm, were carried out, as per the design of experiments planned for the most critical set of process parameters, as given in the example of process parameters. The measurement of diffused reflection of these wafers (more than 100 pcs.) showed an average reflectance of ~8.4%. Using these textured wafers the best cell efficiency of 15.6% was obtained in a batch of 82 solar cells using conventional solar cells manufacturing steps. The details of the results achieved are given in Figs. 4, 5 and 6. Fig.4. gives a run chart for diffused reflectance of mc-Si wafers after plasma texturing and damage removal etching (DRE) process. Fig.5. illustrates a histogram of efficiency of the cells processed in the manufacturing line using wafers with and without plasma texturing. It can be observed that approximately 90% of the plasma textured cells are falling in 14-15% efficiency range - whereas 7.3% cells are in 15-16% efficiency range. Fig.6. shows current- voltage characteristics of mc-Si solar cells with and without plasma texturing in a customized Plasma reactor. Fig.7. gives SEM micrographs of plasma textured sample Silicon wafers at different magnifications of a) 3,000X and b) 10,000X. Fig.8. gives a typical surface profile of the plasma textured wafer. Fig 9. shows quantum efficiency measurements of typical mc-Si solar cells with and without plasma texturing. It could be observed from QE curves that the plasma texturing has enhanced the long wavelength response of the solar cell due to passivation of defects near Aluminum BSF junction and light trapping on the rear of the cell. Fig.10 exhibits photographs of solar cells: with (Left side) and without (Right side) plasma texturing. The texturing of silicon wafers through plasma etching process was carried out as shown in the flow chart of Fig. 14 and explained below. 20 silicon wafers each 156mm x 156mm in size were mounted on a Stainless steel carrier after they were polished with an alkali solution with a concentration of 10-30% and at a temperature 70°- 85°C. The process chamber was evacuated to a chamber pressure of 150 to 300 m Torr and the gas mixture (SF6 and O2) was introduced in the chamber through Mass Flow Controllers (MFC) used for monitoring and control of gas flow in the process chamber. The gas mixture was uniformly distributed over the silicon wafers mounted on the carrier plate through a shower head electrode. Following this, the RF power (Radio Frequency Power) was switched on and maintained at a predetermined value. The showerhead electrode was capacitively coupled with the wafer carrier for striking plasma as well as designed to exhaust the residual gas uniformly. RF Power was switched off after a preset time and the chamber was purged with Nitrogen for a couple of minutes. The wafer carrier was transferred to the exit load lock chamber. From the load lock chamber wafer carrier was transferred to the unload station and then the textured wafers were unloaded in an etching basket. An etchant made up of HF-, HNO3 and H2O (2:48:50) was used at 8-15 Deg C temperature for damage removal etching. The textured wafers were dipped in the solution for 10-30 seconds, rinsed thoroughly in DM water and dried. The diffused reflectance of the textured wafers was measured and the wafers accepted if it was less than 10%. Examples of the critical Process parameters for Plasma texturing process: Fixed Parameters • Wafer size: 125 mm sq. or 156 mm sq. • Showerhead Electrode size :930mm x 740mm =6900 cm2 • Carrier plate size: 685 mm x 880 mm suitable for 5x4 wafer matrix. • Etching gases: SF6 and O2. • Type of Saw damage removal Etch: Alkali (20% NaOH) for 1-2 min • Damage Removal Etch composition: HF:HNO3:H2O (2:48:50) and Duration: 10 to 20 see. DRE Bath Temp: 10-15°C. WE CLAIM; 1, A method for high throughput plasma etching process for texturing and plasma damage removal of silicon wafers consist steps of:- - loading the wafer carrier with alkali polished wafers in the Process Chamber. - evacuating the Process Chamber. - introducing process gas mixture (SF6 and 02) in the chamber through MFCs (Mass Flow Controller) in a predetermined ratio. - setting RF (Radio frequency) power to predetermined value and switching on the matching network control in automode. - keeping the RF power ON for a predetermined value. - switching OFF the RF power. - evacuating the Process Chamber. - purging the Process Chamber with Nitrogen. - transferring the wafer carrier to the exit load lock Chamber. - venting the exit load lock Chamber. - transferring the wafer carrier to the unload station. - unloading the textured wafers in an etching basket. - preparing a HF, HNO3 and H2O (2;48:50) etchant and maintain its temperature at 10-15°C. - dipping the textured wafers in the solution for 10-30 sec, DI water rinse and dry. - measuring diffused reflectance, R and accepting, if R 10%. characterized in that the plasma etching process is carried out after premixing the etching gases and in that the gas mixture is uniformly distributed over the silicon wafers mounted on the carrier plate, using a showerhead electrode. 2. A method as claimed in claim 1 wherein the fixed ratio of process gas flows SF6:O2 is maintained in the range of 2:1 or 3:1. 3. A method as claimed in claim 1 wherein the chamber pressure is evacuated to 150 to 300mm Torr. 4. A method as claimed in claim 1 wherein the process duration continued in the range of 5 to 10 minutes for optimum texture of silicon wafers. 5. A method as claimed in claim 1 wherein a gas blender is used for premixing of gases. 6. A method as claimed in claim 1 wherein the gas blender and the showerhead electrode is mounted on an SS carrier designed for loading of mc-Si wafers. 7. A method as claimed in claim 1 wherein the RF Power density is in the range of 0.15-0.22 w/cm2. 8. A method as claimed in claim 1 wherein alkali solution used for polishing the wafers has a concentration of 10-30% and a temperature 70°-85°C prior to texturing. 9. A method as claimed in claim 1 wherein process chamber is purged by Nitrogen for a duration of 3 minutes. 10. The textured silicon wafers as claimed in claim 1 wherein the wafers are uniformly textured and have an average reflectivity of 8%. 11.The silicon wafers as claimed in claim 10 have damage free light harvesting surface worthy of producing upto 15.6% efficient multicrystalline silicon solar cells. A novel, high throughput plasma etching process for texturing of silicon wafers for texturing and plasma damage removal of silicon wafers, by introducing process gas mixture (SF6 and O2) in the chamber through MFCs (Mass Flow Controller) in a predetermined ratio and setting RF (Radio frequency) power to a predetermined value and switching on the matching network control in automode. The plasma etching process is carried out after premixing the etching gases and in that the gas mixture is uniformly distributed over the silicon wafers mounted on the carrier plate, using a showerhead electrode.

Full Text

FIELD OF INVENTION:
Solar cells are fabricated from multicrystalline silicon wafers
(mc-si). One of the essential requirements for high efficiency
solar cells is minimization of the reflection of incident light
from its front surface for enhanced light harvesting.
The present invention relates to development of a novel high
throughput plasma etching process for texturing multicrystalline
silicon wafers (mc-Si) and their application in solar cell
fabrication.
BACKGROUND OF THE INVENTION;
Plasma etching provides a stress-free method suitable for texturing
thin silicon wafers, independent of crystal orientation, for
obtaining isotropically texturised mc-Si surface that is not
possible with wet alkaline method used for texturing
monocrystalline silicon wafers. In recent publications on the
subject, improvement in efficiency of mc-Si solar cells has been
reported using plasma texturing process when compared to other
methods of surface texturing.
The improvement in efficiency of mc-Si solar cells has been
attributed to: a) complete suppression of reflectivity ( broad spectral range (300-1000 nm) leading to black silicon
surface, b) implementation of the texturing process in the chemical
etching dominated mode that results in reduced surface damage or
additionally performing defect removal etching and c) passivation
of the surface and bulk defects in silicon by the PECVD deposited
silicon nitride AR coating film.
Using optimum ratios of flow rates of SF6 and O2 etch precursors
under the influence of 13.56 MHz RF power and pressure-electrode
gap combination, a reaction byproduct causing self-masking was
created on the surface of mc-Si wafer to give random etching,
independent of the crystal orientation. This random etching of
silicon surface lead to wavelength scale nanostructures (typical
size: 150-200 nm) exhibiting enhanced light harvesting property.
The high throughput of the texturing process was realized through a
custom designed, three chamber industrial system (one process and
two load lock chambers) suitable for processing 20 wafers per batch
(each of 156 mm sq. size).
The uniformity in texturing was obtained by introducing innovative
features like, premixing of process gases (high molecular weight
SF6 gas with low molecular weight O2 gas through a gas blender) and
uniform distribution of premixed gasses to obtain uniform plasma
over the entire wafer carrier (Si2e:~0.7 m2)was carried out through
a showerhead electrode.
A process invention (Ref: Patent application No. 768/KOL/2007 A,
Date of filing application: 18/05/2007) disclosing a self-masking,
low energy, RIE (Reactive Ion Etching) plasma process for surface
texturing of 125 mm sq mc-Si wafers for use in solar cell is in the
process of granting the patent. SF6 and O2 gas mixture under 13.56
MHz RF power, produces reactive ions responsible for random surface
etching of silicon wafers called texturing. The process resulted in
formation of nanostructures with size comparable to wavelength of
incident light exhibited efficient light trapping and facilitated
enhanced surface passivation due to hydrogen released by PECVD
SiNx.
The wafer surface was polished with alkali solution essential for
initiating texturing process on damage-free surface to get optimum
quality solar cell emitter. Use of minimum RF power density and
mounting of the wafer on grounded carrier plate lead to a damage-
free textured surface of the wafer. Further, wafer surface was
treated with acid based damage removal etch to eliminate
possibility of any plasma damaged textured surface.
The overall outcome of the multicrystalline silicon texturing
process lead to an improved solar cell efficiency upto 15.1% for
125 mm sq size, which is 2.4% absolute higher compared to the one
without RIE texturing.
In the prior art, a) the process gases were fed to the plasma
chamber without premixing leaving a room for non-uniformity of
plasma precursors and b) the gas mixture was not uniformly

delivered over the silicon wafers mounted on the carrier plate
acting as a ground electrode.
In the present invention the plasma etching process is carried out
after premixing the etching gases and the gas mixture was uniformly
distributed over the silicon wafers mounted on the carrier plate,
using a showerhead electrode. Due to inclusion of these additional
processes, it is possible to texture 20 silicon wafers of size upto
156 mm sq. per batch.
The objects of the present invention is to disclose a high
throughput plasma texturing process capable of producing 20
textured wafers per batch each of 156 mm sq. size with consistently
uniform texturisation, low reflection and damage-free surface
suitable for solar cell applications.
The present invention discloses set of process parameters creating
specific condition of self-masking due to in-situ formation of
randomly absorbed polymer giving rise to selective etching of
silicon, yielding least reflecting, uniformly textured wafers

placed over the entire carrier. To reduce the etching damage of the
silicon wafers, wafer carrier was grounded and hence process done
in chemical etching dominated mode.
Inventive feature of the present invention lies in:-
Introduction of gas blending process resulting in an uniform
mixture of process gases viz., SF6 and O2.
Maintaining uniform flow of premixed gases over 20 silicon wafers
each of 156 mm x 156 mm size, mounted on a SS carrier, by
introducing a showerhead electrode coupled with the wafer carrier
designed to exhaust the residual gases uniformly.
Enhanced plasma stability and uniformity leading to uniform
texturing and a throughput of 20 wafers per batch by introducing
independent RF earthing system and excellent matching network.
A combination of process parameters (given in detailed Technical
write up) resulting in a product called, plasma textured silicon
wafer (size: 125 mm sq. or 156 mm sq.) with reduced average

reflectance ~ 8% forming an input to solar cell process exhibiting
cell efficiency.
For example, solar cells processed out of the plasma textured
multicrystalline silicon wafers showed efficiency upto 15.6% and
the improvement achieved in average efficiency of the solar cell is
upto 1.5% higher compared to the one without plasma texturing.
SUMMARY OF THE INVENTION;
The present invention discloses a novel, high throughput plasma
etching process for texturing multicrystalline silicon wafers and
its application in solar cell fabrication. The process was carried
out in a custom designed multichamber plasma etching system.
Features of the system resulting in novel high throughput plasma
etching process include, uniform distribution of premixed gases to
obtain uniform plasma over the entire wafer carrier (Size: ~0.7m2)
by using showerhead electrode for gas distribution, grounding of
the wafer carrier to minimize the sputter damage due to accelerated
radicals/ions in the plasma, and use of PLC based SCADA automation
system for process operation. Using optimum flow rates and ratio of
SF6 and O2 etch precursors under the influence of 13.56 MHz RF power
and combination of pressure-electrode gap, a reaction causing self-
masking on the surface of mc-Si wafers was created to give random
etching independent of crystal orientation. This random etching of
silicon surface lead to wavelength scale nanostr.uctures (typical
size: 150-200 nm) exhibiting enhanced light harvesting property.
A number of process experimentation runs were carried out by
varying critical process parameters for achieving optimum surface
texturing of mc-Si wafers of size 125 mm sq. and 156 mm sq. The
average reflectance measured was -8.4% on more than 100 textured
wafers after carrying out damage removal etching (DRE) process.
Theses plasma textured mc-Si wafers were processed for cells using
standard manufacturing steps. Current-Voltage characteristics of
the plasma textured cells under standard test conditions show
highest conversion efficiency of 15.6% whereas that for cells
without plasma texturing it was 13.9%, clearly showing an
improvement of 1.7% absolute in efficiency.
ACCOMPAYING DRAWINGS;
Fig.l. A view of the three-chamber Plasma Etching System for
texturing of mc-Si wafers.
Fig.2. Photographs of the 20 silicon wafers loaded in the carriers,
a) left side: saw damage removed wafers kept in the loading
station, b) right side: Plasma textured wafers kept in the
unloading station.
Fig.3. A view of process chamber showing plasma of sulphur
hexafluoride and oxygen process gases.
Fig.4. Run chart for diffused reflectance of mc-Si wafers after
plasma texturing and damage removal etching (DRE).
Fig.5. Histogram distribution of efficiency of the mc-Si solar
cells processed in a manufacturing line using mc-Si wafers
with and without plasma texturing.
Fig.6. Current-Voltage characteristics of mc-Si solar cells with
and without plasma texturing.
Fig.7. SEM micrographs of sample plasma textured Silicon wafers at
different magnifications a) 3,000X b) 10,000X.
Fig.8. Microscope image of sample RIE textured mc-Si wafer
(Magnification: 2000X)
Fig.9. Typical surface profile of a plasma textured wafer.
Fig.10. Quantum efficiency measurements on typical mc-Si solar
cells with and without plasma texturing.
Fig.11. Photographs of solar cells: with (Left side) and without
(Right side) plasma texturing.
Fig.12. Schematics of plasma texturing system used in Plasma
texturing process.
Fig.13. Schematic of the shower head electrode showing four
capillaries for four silicon wafers for simplicity.
Fig.14. Process Flow in Solar cell fabrication.
DEATILED DESCRIPTION OF THE INVENTION:
The invention will now be described in an exemplary embodiment as
depicted in the accompanying drawing. There can however be other
embodiments of the same invention, all of which are deemed covered
by this description.
The present invention relates to development of a high throughput
plasma etching process suitable for uniform texturing of 20 silicon
wafers for use in high efficiency solar cell process. The process
was carried out in a custom designed industrial three chamber
plasma etching system comprising a process chamber and two load
lock chambers placed on both sides of the process chamber to avoid
possible contamination to wafers due to atmospheric or other
exposure. Loading and unloading stations for wafer carrier were
provided to facilitate the start up and completion of the process
cycle.
Fig.1. shows a view of the three-chamber Plasma Etching System
having essential accessories, like mass flow controllers (MFCs) for
monitoring and maintaining the gas flow in the process chamber,
customized gas blender for premixing of process gases, pressure
gauges to monitor pressure of the process chamber and load-lock
chambers to facilitate on-line transfer of wafer carrier across the
vacuum chambers and their entry to and exit from the chambers,
vacuum pumps for evacuating residual gases and reaction byproducts
from the process chamber and equalization of chamber pressure
during carrier transfer, custom designed showerhead electrode for
effective uniform distribution of process gases across the entire
wafer carrier, RF power supply and matching network for splitting
the precursor gases into etch radicals and ions, 'o' ring sealed
slit valves to avoid cross contamination within chambers and from
outside environment, variable frequency drive (VFD) motors for
transport of wafer carrier and PLC based process automation and
SCADA monitoring system for process operation etc. are integrated
with the system.
Fig.2. a) On left side: gives photographs of the wafer carrier
placed in the loading station, with 20 mc-Si wafers after saw
damage removal, whereas in b) on right side: textured mc-Si wafers
kept in the unloading station are shown. Fig.3. illustrates a view
of process gas plasma (Sulphur Hexafluoride and Oxygen) in the
process chamber.
Process optimization runs for texturing silicon wafers of size up
to 156 mm x 156 mm, were carried out, as per the design of
experiments planned for the most critical set of process
parameters, as given in the example of process parameters. The
measurement of diffused reflection of these wafers (more than 100
pcs.) showed an average reflectance of ~8.4%. Using these textured
wafers the best cell efficiency of 15.6% was obtained in a batch of
82 solar cells using conventional solar cells manufacturing steps.
The details of the results achieved are given in Figs. 4, 5 and 6.
Fig.4. gives a run chart for diffused reflectance of mc-Si wafers
after plasma texturing and damage removal etching (DRE) process.
Fig.5. illustrates a histogram of efficiency of the cells processed
in the manufacturing line using wafers with and without plasma
texturing. It can be observed that approximately 90% of the plasma
textured cells are falling in 14-15% efficiency range - whereas
7.3% cells are in 15-16% efficiency range. Fig.6. shows current-
voltage characteristics of mc-Si solar cells with and without
plasma texturing in a customized Plasma reactor. Fig.7. gives SEM
micrographs of plasma textured sample Silicon wafers at different
magnifications of a) 3,000X and b) 10,000X. Fig.8. gives a typical
surface profile of the plasma textured wafer. Fig 9. shows quantum
efficiency measurements of typical mc-Si solar cells with and
without plasma texturing. It could be observed from QE curves that
the plasma texturing has enhanced the long wavelength response of
the solar cell due to passivation of defects near Aluminum BSF
junction and light trapping on the rear of the cell. Fig.10
exhibits photographs of solar cells: with (Left side) and without
(Right side) plasma texturing.
The texturing of silicon wafers through plasma etching process was
carried out as shown in the flow chart of Fig. 14 and explained
below.
20 silicon wafers each 156mm x 156mm in size were mounted on a
Stainless steel carrier after they were polished with an alkali
solution with a concentration of 10-30% and at a temperature 70°-
85°C. The process chamber was evacuated to a chamber pressure of
150 to 300 m Torr and the gas mixture (SF6 and O2) was introduced in
the chamber through Mass Flow Controllers (MFC) used for monitoring
and control of gas flow in the process chamber. The gas mixture was
uniformly distributed over the silicon wafers mounted on the
carrier plate through a shower head electrode. Following this, the
RF power (Radio Frequency Power) was switched on and maintained at
a predetermined value. The showerhead electrode was capacitively
coupled with the wafer carrier for striking plasma as well as
designed to exhaust the residual gas uniformly. RF Power was
switched off after a preset time and the chamber was purged with
Nitrogen for a couple of minutes. The wafer carrier was transferred
to the exit load lock chamber. From the load lock chamber wafer
carrier was transferred to the unload station and then the textured
wafers were unloaded in an etching basket. An etchant made up of
HF-, HNO3 and H2O (2:48:50) was used at 8-15 Deg C temperature for
damage removal etching. The textured wafers were dipped in the
solution for 10-30 seconds, rinsed thoroughly in DM water and
dried. The diffused reflectance of the textured wafers was measured
and the wafers accepted if it was less than 10%.
Examples of the critical Process parameters for Plasma texturing
process:
Fixed Parameters
• Wafer size: 125 mm sq. or 156 mm sq.
• Showerhead Electrode size :930mm x 740mm =6900 cm2
• Carrier plate size: 685 mm x 880 mm suitable for 5x4 wafer
matrix.
• Etching gases: SF6 and O2.
• Type of Saw damage removal Etch: Alkali (20% NaOH) for 1-2
min
• Damage Removal Etch composition: HF:HNO3:H2O (2:48:50) and
Duration: 10 to 20 see. DRE Bath Temp: 10-15°C.
WE CLAIM;
1, A method for high throughput plasma etching process for
texturing and plasma damage removal of silicon wafers consist
steps of:-
- loading the wafer carrier with alkali polished wafers in
the Process Chamber.
- evacuating the Process Chamber.
- introducing process gas mixture (SF6 and 02) in the
chamber through MFCs (Mass Flow Controller) in a
predetermined ratio.
- setting RF (Radio frequency) power to predetermined value
and switching on the matching network control in
automode.
- keeping the RF power ON for a predetermined value.
- switching OFF the RF power.
- evacuating the Process Chamber.
- purging the Process Chamber with Nitrogen.
- transferring the wafer carrier to the exit load lock
Chamber.
- venting the exit load lock Chamber.
- transferring the wafer carrier to the unload station.
- unloading the textured wafers in an etching basket.
- preparing a HF, HNO3 and H2O (2;48:50) etchant and
maintain its temperature at 10-15°C.
- dipping the textured wafers in the solution for 10-30
sec, DI water rinse and dry.
- measuring diffused reflectance, R and accepting, if R 10%.
characterized in that the plasma etching process is carried
out after premixing the etching gases and in that the gas
mixture is uniformly distributed over the silicon wafers
mounted on the carrier plate, using a showerhead electrode.
2. A method as claimed in claim 1 wherein the fixed ratio of
process gas flows SF6:O2 is maintained in the range of 2:1 or
3:1.
3. A method as claimed in claim 1 wherein the chamber pressure
is evacuated to 150 to 300mm Torr.
4. A method as claimed in claim 1 wherein the process duration
continued in the range of 5 to 10 minutes for optimum texture
of silicon wafers.
5. A method as claimed in claim 1 wherein a gas blender is used
for premixing of gases.
6. A method as claimed in claim 1 wherein the gas blender and
the showerhead electrode is mounted on an SS carrier designed
for loading of mc-Si wafers.
7. A method as claimed in claim 1 wherein the RF Power density
is in the range of 0.15-0.22 w/cm2.
8. A method as claimed in claim 1 wherein alkali solution used
for polishing the wafers has a concentration of 10-30% and a
temperature 70°-85°C prior to texturing.
9. A method as claimed in claim 1 wherein process chamber is
purged by Nitrogen for a duration of 3 minutes.
10. The textured silicon wafers as claimed in claim 1 wherein the
wafers are uniformly textured and have an average
reflectivity of 8%.
11.The silicon wafers as claimed in claim 10 have damage free
light harvesting surface worthy of producing upto 15.6%
efficient multicrystalline silicon solar cells.

A novel, high throughput plasma etching process for texturing of
silicon wafers for texturing and plasma damage removal of silicon
wafers, by introducing process gas mixture (SF6 and O2) in the
chamber through MFCs (Mass Flow Controller) in a predetermined
ratio and setting RF (Radio frequency) power to a predetermined
value and switching on the matching network control in automode.
The plasma etching process is carried out after premixing the
etching gases and in that the gas mixture is uniformly distributed
over the silicon wafers mounted on the carrier plate, using a
showerhead electrode.

Documents:

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Patent Number

270489

Indian Patent Application Number

844/KOL/2010

PG Journal Number

01/2016

Publication Date

01-Jan-2016

Grant Date

28-Dec-2015

Date of Filing

02-Aug-2010

Name of Patentee

BHARAT HEABY ELECTRICALS LIMITED

Applicant Address

REGIONAL OPERATIONS DIVISION (ROD), PLOT NO : 9/1, DJBLOCK 3RD FLOOR, KARUNAMOYEE, SALT LAKE CITY, KOLKATA-700091, HAVING ITS REGISTERED OFFICE AT BHEL HOUSE, SIRI FORT, NEW DELHI - 110049, INDIA

Inventors:

#	Inventor's Name	Inventor's Address
1	DR. BASUDEV PRASAD	BHEL ASSCP, GWALPAHARI, GURGAON, INDIA
2	DR. SANGALA RAGHUNATH REDDY	BHEL ASSCP, GWALPAHARI, GURGAON, INDIA
3	DR. ANIL KUMAR SAXENA	BHEL ASSCP, GWALPAHARI, GURGAON, INDIA
4	SUDIP BHATTACHARYA	BHEL ASSCP, GWALPAHARI, GURGAON, INDIA
5	MANISH PATHAK	BHEL ASSCP, GWALPAHARI, GURGAON, INDIA
6	DR. RAMESH KUMAR BHOGRA	BHEL ASSCP, GWALPAHARI, GURGAON, INDIA

PCT International Classification Number

H05H1/46

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA