Title of Invention

"SYSTEM FOR SIMPLIFYING THE PROGRAMMABLE MEMORY TO LOGIC INTERFACE IN FIELD PROGRAMMABLE GATE ARRAY (FPGA)

Abstract

The present invention provides a structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable logic blocks and the input-output resources of the FPGA access the embedded memory or RAM using dedicated direct interconnects. A major part of these direct interconnects surface from programmable logic blocks in vicinity of the RAM. The rest run between the input-output (IO) pads/routing and the RAM blocks. A dedicated bus-routing architecture is provided to club the memories to emulate larger RAM blocks. This bus routing is devoted to interconnection among RAM blocks and is isolated from the PLB routing resources.

Full Text

Field of the Invention This invention relates to a system for simplifying the programmable memory to logic interface in field programmable gate array (FPGA). Background of the Invention An FPGA is a semi custom device based on an array of generic cells or logic blocks, each having a programmable function, surrounded by a programmable interconnect network. Inclusion of RAM blocks in the FPGA architecture saves lot of valuable logic & routing resources. Memory intensive applications are accommodated within an FPGA with embedded RAM blocks. Also, many wide input output functions are absorbed into the RAM blocks, thus saving logic and interconnect resources. Such RAM blocks are generally evenly distributed on the FPGA chip. An interconnect system is provided for the RAM to interface with other logic resources on chip. In the prior art of patent number 5933023 of Xilinx, routing lines which access the logic blocks also access address, data, and control lines in the RAM blocks. This results in great routing flexibility between the RAM and other logic blocks, but at the same time offers a very complex model to the software tool. A plethora of constraints in terms of intra bus net slack, general routing asymmetry, routing congestion and many others come into picture. The object and summary of the invention The object of this invention is to obviate the above drawback. To achieve the said objectives, this invention provides a field programmable gate array (FPGA) comprising: • a plurality of embedded memories having a plurality of address lines, data lines, and control lines connected thereto; • a plurality of programmable logic blocks (PLBs); • a plurality of input/output (I/Os); • a plurality of routing lines interconnecting said embedded memories, said PLBs, and said I/Os; • a plurality of programmable switches for isolating the routing lines from said address lines, data lines, and control lines; and • a plurality of dedicated connections for connecting said PLBs and said I/Os to said embedded memories. The said embedded memories comprise input and output terminals; and wherein said dedicated connections connect PLBs adjacent respective input terminals thereto, and connect PLBs adjacent respective output terminals thereto. The said embedded memories further comprise input and output terminals; and further comprising at least one respective multiplexer connected to said input terminals of each embedded memory, and at least one respective de-multiplexer connected to said output terminals of each embedded memory. The FPGA further comprises at least one bus for interconnecting data and address lines of said plurality of embedded memories to provide a memory of increased size. The said PLBs comprise at least one internal register for latching signals sent to or received from said embedded memories. The said internal register of said PLBs are connected to said routing lines. The said internal registers of said PLBs are selectively bypassable to provide unregistered memory inputs and outputs. Each PLB comprises a look-up table (LUT) and a flip-flop connected thereto for interfacing said embedded memories; and wherein said LUT is used at least independently of said flip-flop. The present invention also provides a method for making a field programmable gate array (FPGA) comprising: • providing at least one embedded memory and connecting a plurality of address lines, data lines, and control lines thereto; • providing a plurality of programmable logic blocks (PLBs) and a plurality of input/outputs (I/Os); • interconnecting the at least one embedded memory, the PLBs, and the I/Os using a plurality of routing lines; • isolating the routing lines from the memory address lines, data lines, and control lines; and • connecting the PLBs and the 1/Os to the at least one embedded memory using dedicated connections. The at least one embedded memory further comprises input and output terminals; and wherein the dedicated connections connect PLBs adjacent respective input terminals thereto, and connect PLBs adjacent respective output terminals thereto. The at least one embedded memory further comprises input and output terminals; and further comprising connecting at least one multiplexer to the input terminals and at least one demultiplexer to the output terminals. The method further comprises connecting the at least one multiplexer to at least one of the PLBs. The method further comprises connecting the at least one multiplexer to at least one of the I/Os. The method further comprises connecting the at least one de-multiplexer to at least one of the PLBs. The method further comprises connecting the at least one de-multiplexer to at lease one of the I/Os. The isolating comprises isolating the routing lines from the address lines, data lines, and control lines using a plurality of programmable switches. The at least one embedded memory comprises a plurality of embedded memories; and further comprising interconnecting data and address lines of the plurality of embedded memories to provide a memory of increased size using at least one bus. The PLBs comprise at least one internal register for latching signals sent to or received from the at least one embedded memory. The method further comprises connecting the internal registers of the PLBs to the routing lines. The PLBs comprise at least one internal flip-flop for latching signals sent to or received from the at least and embedded memory. The PLBs comprise a look-up table (LUT) and a flip-flop connected thereto for interfacing the at least one embedded memory; and wherein the LUT is used at least independently of the flip-flop. Brief Description of the drawings The invention will now be described with reference to the accompanying drawings. Figure 1 shows FPGA chip with embedded memory RAM according to prior art. Figure 2 delineates interconnects scheme of the prior art for a rudimentary single port RAM. Figure 3 shows a simple single port memory with a plurality of multiplexers and demultiplexers at its input and output pins respectively. Figure 4 shows devoted bus based routing for clubbing data and address lines in order to combine the RAM blocks to implement larger memories according to this invention. Figure 5 shows a scheme for eliminating the internal registers of the embedded memory thereby saving significant area. Detailed Description of the Invention Figure 1 shows an FPGA chip with embedded memory (RAM) in the prior art. Item [1] is a generic programmable logic block (PLB), [3] is the RAM, [la] is the general routing fabric, [2a] are the Input-Output (IO) routing resources and [2] are the IO pads. Figure 2 delineates the interconnect scheme of the prior art for a rudimentary single port RAM. Configurable switches [3] interface the memory to the routing interconnects in the routing channel. These routing lines can also be accessed by logic blocks or IO pads through the routing channel. Thus, a lot of flexibility is provided. But many constraints are introduced and the software for routing such architectures becomes very complex as the memory (RAM) blocks in the FPGA chip are augmented. The basic embodiment of figure 3 aims to bring forth the advantages of the present invention. Referring to figure 3, a simple single port memory is shown with a plurality of multiplexers [3i] and de-multiplexers [3o] at its input and output pins respectively. It is apparent that the RAM has eight address .inputs and eight data outputs. The inputs to the multiplexers [3i] are outputs from various PLB (or even the same PLB) or from IO pads/routing. Similarly, outputs from de-multiplexers [3o] are being fed to PLB inputs or IO resources. The multiplexer [3i] & de-multiplexer [3o] will be configured during initial configuration of the device. In most cases all [3i] multiplexers and [3o] de-multiplexers can share their respective configuration bits, thus reducing the configuration latch count. The direct interconnects to/from IO routing at the device periphery may be provided to facilitate signals from a range of IO pads rather than a single pad. Therefore, by using programmable direct interconnects for memory interface. many advantages are in the offering. Some of the major advantages are given below. It is to be noted that PLBs which interact with the RAM do so only through programmable tappings to/from their inputs or outputs. Their connectivity to the general-purpose routing fabric is not altered in any way. The basic idea of extending direct interconnects from PLBs or lOs is to spare the general purpose routing from the burden of RAM interconnects. It is very obvious that the memory block will network signals to/from cither a sub-circuit or an IO resource. The invention attempts to eliminate any routing that might be used to convey signals between sub-circuits/IOs and the memory. The same arguments hold valid for control signals to/from the memory. Although some limitations are inherent in terms of flexibility when direct interconnects are used for memory interface, but the architecture becomes software friendly. Another aspect of the invention is to provide for devoted bus based routing for clubbing data and address lines in order to combine the RAM blocks to implement larger memories (figure 4). This dedicated routing extends between memory address ports or data ports that might be combined for large memory emulation. As the routing is bus based, configuration latch count is reduced because a bus is routed as a whole against a net-to-net route. In figure 5, the multiplexer[3i] sourcing a memory input is shown connected to the PLB output via a DI[7o] (Direct Interconnect). The memory block can be used in both asynchronous and synchronous mode. The asynchronous mode comes into picture when the memory block is used to implement combinatorial logic. In this mode, the memory block receives unregistered output[4o] of the LUT via multiplexer[7]. The memory output is directed through multiplexer [3o] to the PLB input [4i] that is an LUT input. The control line of the multiplexers is suitably configured by the configuration latches[5x & 7x]. In the synchronous mode, the memory block is used as a RAM. In this mode, the registered output[6o] of the LUT is connected to the Memory input via the multiplexers [7] & [3i]. The control line of the multiplexer is suitably configured by the configuration latch[7x] to include the flip-flop output. Another possibility is to connect the FF input to [5i] via multiplexer[5]. This enables the memory input signal to bypass the LUT output and approach the FF from general purpose routing. The flip-flop associated with each LUT obviates the need of internal memory registers present at the input of a conventional memory block. The clock of the flip-flop initiates the read/ write operation of the memory. Similarly, the output registers of the memory become redundant as multiplexer [3o] can drive a PLB input [5i]. Output of multiplexer[3o) is directed to FF[6) via multiplexer [5]. Thus, we can save memory registers internal to the memory in an FPGA with memory blocks. It is also apparent that if the Flip-Flop is used as a memory input/output register, the LUT can be used to perform independently. MAJOR ADVANTAGES 1. Architecture simplified, as switch pattern interfaces between general routing and the memories are eliminated. 2. Input/Output registers internal to a memory eliminated. 3. Symmetric properties of the general purpose routing are preserved. 4. Memory routing is independent of PLB routing architecture and is bus based. Results in a symmetrical PLB routing architecture. Configuration latch count in intra-memory routing is reduced with the additional advantage of improved flexibility in tying up memories. 5. There is no slack among nets comprising the address/data bus. Negligible slack that might be introduced while clubbing memories can be easily controlled. 6. Facilitates even distribution of memory resources in the FPGA without increasing complexity. 7. Greatly reduces the formidable task of routing memories to PLBs for the Place & Route tool; simplifies algorithms and time complexity of tool. We claim: 1. A field programmable gate array (FPGA) comprising: • a plurality of embedded memories having a plurality of address lines, data lines, and control lines connected thereto; • a plurality of programmable logic blocks (PLBs); • a plurality of input/output (I/Os); • a plurality of routing lines interconnecting said embedded memories, said PLBs, and said I/Os; • a plurality of programmable switches for isolating the routing lines from said address lines, data lines, and control lines; and • a plurality of dedicated connections for connecting said PLBs and said I/Os to said embedded memories. 2. The FPGA as claimed in claim 1 wherein said embedded memories comprise input and output terminals; and wherein said dedicated connections connect PLBs adjacent respective input terminals thereto, and connect PLBs adjacent respective output terminals thereto. 3. The FPGA as claimed in claim 1 wherein said embedded memories comprise input and output terminals; and comprising at least one respective multiplexer connected to said input terminals of each embedded memory, and at least one respective de multiplexer connected to said output terminals of each embedded memory. 4. The FPGA as claimed hi claim 1 comprising at least one bus for interconnecting data and address lines of said plurality of embedded memories to provide a memory of increased size. 5. The FPGA as claimed in claim 1 wherein said PLBs comprise at least one internal register for latching signals sent to or received from said embedded memories. 6. The FPGA as claimed in claim 5 wherein said internal register of said PLBs are connected to said routing lines. 7. The FPGA as claimed in claim 5 wherein said internal registers of said PLBs are selectively bypassable to provide unregistered memory inputs and outputs. 8. The FPGA as claimed in claim 1 wherein each PLB comprises a look-up table (LUT) and a flip-flop connected thereto for interfacing said embedded memories; and wherein said LUT is used at least independently of said flip-flop. 9. A method for making a field programmable gate array (FPGA) comprising: • providing at least one embedded memory and connecting a plurality of address lines, data lines, and control lines thereto; • providing a plurality of programmable logic blocks (PLBs) and a plurality of input/outputs (I/Os); • interconnecting the at least one embedded memory, the PLBs, and the I/Os using a plurality of routing lines; • isolating the routing lines from the memory address lines, data lines, and control lines; and • connecting the PLBs and the I/Os to the at least one embedded memory using dedicated connections. 10. The method as claimed in claim 9 wherein the at least one embedded memory comprises input and output terminals; and wherein the dedicated connections connect PLBs adjacent respective input terminals thereto, and connect PLBs adjacent respective output terminals thereto. 11. The method as claimed in claim 9 wherein the at least one embedded memory comprising input and output terminals; and further comprising connecting at least one multiplexer to the input terminals and at least one de-multiplexer to the output terminals. 12. The method as claimed in claim 11 comprising connecting the at least one multiplexer to at least one of the PLBs. 13. The method as claimed in claim 11 comprising connecting the at least one multiplexer to at least one of the I/Os. 14. The method as claimed in claim 11 comprising connecting the at least one de multiplexer to at least one of the PLBs. 15. The method as claimed in claim 11 comprising connecting the at least one de multiplexer to at lease one of the I/Os. 16. The method as claimed in claim 9 wherein isolating comprises isolating the routing lines from the address lines, data lines, and control lines using a plurality of programmable switches. 17. The method as claimed in claim 9 wherein the at least one embedded memory comprises a plurality of embedded memories; and comprising interconnecting data and address lines of the plurality of embedded memories to provide a memory of increased size using at least one bus. 18. The method as claimed in claim 9 wherein the PLBs comprise at least one internal register for latching signals sent to or received from the at least one embedded memory. 19. The method as claimed in claim 1 8 comprising connecting the internal registers of the PLBs to the routing lines. 20. The method as claimed in claim 9 wherein the PLBs comprise at least one internal flip-flop for latching signals sent to or received from the at least and embedded memory. 21. The method as claimed hi claim 9 wherein the PLBs comprise a look-up table (LUT) and a flip-flop connected thereto for interfacing the at least one embedded memory; and wherein the LUT is used at least independently of the flip-flop. 22. A field programmable gate array (FPGA) substantially as herein described with reference to and as illustrated in the accompanying drawings. 23. A method for making a field programmable gate array (FPGA) substantially as herein described with reference to and as illustrated in the accompanying drawings.

Documents:

729-del-2001-abstract.pdf

729-del-2001-claims.pdf

729-del-2001-complete specification (granted).pdf

729-del-2001-correspondence-others.pdf

729-del-2001-correspondence-po.pdf

729-del-2001-description (complete).pdf

729-del-2001-drawings.pdf

729-del-2001-form-1.pdf

729-del-2001-form-13.pdf

729-del-2001-form-18.pdf

729-del-2001-form-2.pdf

729-del-2001-form-3.pdf

729-del-2001-pa.pdf