Title of Invention

DIGITAL OUTPUT DRIVER AND INPUT BUFFER USING THIN-OXIDE FIELD EFFECT TRANSISTORS

Abstract

An integrated circuit comprising: a latch configured to provide a first digital signal having a first voltage range determined by a first supply voltage and an intermediate voltage; and a driver coupled to the latch and configured to receive the first digital signal and a second digital signal and lo provide a digital output signal, wherein the second digital signal has a second voltage range determined by a second supply voltage and circuit ground, wherein the digital output signal has a third voltage range determined by the first supply voltage and circuit ground, and wherein the fust supply voltage is higher than the second supply voltage.

Full Text

DIGITAL OUTPUT DRIVER AND INPUT BUFFER USING THIN-OXIDE FIELD EFFECT TRANSISTORS BACKGROUND T. Field JOOOI] The present disclosure relates generdly to electronics, and more specifically to digital output driver and input buffer for an integrated circuit (IC). II. Background [0002] Digital ICs are widely used in various applicalion3 s«ch as cominuiucation devices, computers, consumer electronics, etc. iVlai>y digital ICs are fabricated in complementary metaJ oxide semiconductor (CMOS), which utilizes both N-channel field effect transistors (N-FETs) and P-cbannel FETs (P-.FETs). F.ETs are also called transistor devices, or simply, devices. |0003{ A digital }C may utilize thin-oxide FETs, thick-oxide FETs, or a combination of both thin-oxide and thick-oxide FBTs. In general, a thin-oxide FET can operate at a lower supply voltage and has a thin oxide layei-, a lower threshold voltage, and a lower breakdown voltage. Conversely, a thick-oxide FET can tolerate a higher supply voltage and has a thick oxide layer, a higher threshold voltage, and a higlier breakdown voltage. |0004| Many digital ICs, such as those for processors, are designed v/ith mostly or only thin-oxide FETs. This is because thin-oxide FBTs scale readily with smaller transistor sizes made possible by improvements in IC fabrication technology. Furthermore, thin-oxide FETs can operate at lower supply voltages, which results in lower power consumption. Hence, thin-oxide FETs are highly desirable for portable electronics devices that operate on battery power. 10005} A digital IC typically interfaces with one or more external devices, e.g., memory devices. The external devices may use an input/output (I/O) voltage that is higher than the supply voltage for the digital IC. To accommodate the higher I/O voltage, the I/O circuitry vvithin the digital IC may be fabricated with thick-oxide FETs that can handle the higher I/O voltage. [0006] For a digital IC, thin-oxide FETs may be fabricated with some number of masks, which may be dependent on the JC process used to fabricate the digital IC. Thick-oxide FETs may be fabricated with some number of masks in addition to the masks required for the thin-oxide FETs. For a given IC die area, the cost of the IC die is roughly proportional to the total number of masks required to fabricate the IC die. Hence, it is desirable to interface with the higher I/O voltage using only thin-oxide FETs, so that the additional masks needed for duck-oxide FETs can be avoided in order to reduce manufacturing cost. SUMMARY J0007J There is therefore a need in the art for a digital output driver that can interface with a higher I/O voltage asing thin-oxide FBTs. iOOOS] A digital output driver and a digital input buffer that may be implemented with thin-oxide FETs and having good peribrmance are described hereln. The digital output driver includes a pre-driver and a driver. The pre-driver receives a distal input signal from circuitry internal to a digital IC; and generates first and second digital signals based on the digital input signal. The driver receives the first and second digital signals and provides a digital output signal for an external device. The first digital signal has a first voltage range determined by a first supply voltage and an intermediate voltage. The second digital signal has a second voltage range determined by a second supply voltage and circuit ground. The digital output signal has a third voltage range determined by the first supply voltage and circuit ground. The first supply voltage may be a pad supply voltage, Vp,y>> which is the I/O voltage for the external device. The second supply voltage is lower than the first supply voltage and may be a core supply voltage, VcoRK, for circuihy within the digital IC. |0009| in an embodiment, the pre-driver includes a latch and a latch driver. The latch stores the current logic value for the digital input signal and. may be implemented with two inverters coupled between the first apply voltage and the intermediate voltage. The latch driver writes the logic value to the latch, 'The latch driver may be enabled for only a short period of time to write the logic value and may be turned off afterward. The latch driver may include (1) a first set of N-FETs stacked together and configured to puli down a first node within the latch to write a logic high to the latch and (2) a second set of N-FETs stacked together and configured to pull down a second node Within the latch to write a logic low to the latch. One set of N-FETs may be turned on for a short period of time to write the logic value (e.g., logic high or low) to the latch. The pre-driver may further include a first buffer to buffer the first digital signal and/or a second buffer to buffer the digital input signal. |0010| In an embodiment, the driver includes at least two P-FETs and at least two N-FETs stacked together. The topmost P-FET receives the first digital signal, and tlte bottommost N-:FET receives the second digital signal. For the pre-driver and driver, the number of N-FE'l's and the number of P-FETs to stack together may be determined based on tlie first and second supply voltages and voltage limits for the P-FB'fs and N-FETs, 100.111 Tlie digital input buffer as well as various aspects and embodiments of the invention are described in furthcr detail below. BRIEF DESCRIPTION OF THE DRAWINGS }0012| The features and nature of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference character identify correspondingly throughout. |00.l3| FIG. 1 shows a block diagram of a Wireless device. f00.l4| FIG. 2 shows an I/O circuit composed of an output driver and an input buffer. fOOlSj FIG. 3 shows a block diagram of the output driver. |0016| FIG. 4 shows a schematic diagram of the output driver. |OOI7| FIG. 5 shows atiming diagram for digital signals for a lalch driver within the output driver. [OO.IS| FIG. 6 shows a schematic diagram of a gate control circuit within the latch driver. |0019| FIG. 7 shows a schematic diagram of a latch within the output driver. |0020j FIG. 8 shows a schematic diagram of the input buffer. DETAILED DESC RIPTION |002.1.} The word "exempiary" is used herein to mean "serving as an example, instance, or illustration."" .Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. (0022J The digital output driver described herein may be used for various digital ICs. For exaraple, the digital output driver may be used for an application specific integrated circuit (ASIC), a digital signal processor (DSP), a programmable logic device (PL.D), a field programmable gate array (FPGA), a processor, a controller, a microprocessor, a. radio frequency IC 100231 FIG. 1 sitows a block diagram of a wireless device 100, On the receive path, an antenna 112 receives RF signals transmitted by base stations and/or satellites and provides a. received RF signal to a receiver (RCVR) 114. Receiver 114 processes (e.g., filters, amplifies, frequency downconverts, and disgitizes) the received RF signal and provides samples to an ASIC 120 for further processing. On the transmit path, ASIC 120 processes data to be transmitted and provides data chips to a transmitter (TMTR) 116. Transmitter 116 processes (e.g., converts to analog, filters, amplifies, and frequency upconverts) the data chips and generates an output RF signal, which is transmitted via aiUenna 112. f0024]| ASIC 120 includes various processing units that support coromunjcation and other functions. For the embodiment shown in FlCi, 1, ASIC 120 includes a modem processor 122, an audio/video processor 124, an application processor 126, a main controller/processor 150, an 1/0 controller 132, and a memory controller 134. Modem processor 122 performs processing for data trmismission and reception, e.g., encoding, modulation, demodulation, decoding, and so on. Audio/video processor 124 performs processing for audio and video. Application processor 126 performs processing for various applications svtch as, e.g., multi-way calls, web browsing, games, user interface, and so on. I/O controller 132 interfaces with external devices such as an audio unit 142, a display unit 144, and a keypad 146. Memory controller 134 interfaces with external memories 148, which may include SDRAM, Flash, and so on. J002SI FIG. 2 shows an exemplary I/O circuit 220 that may be used for a digital I/O pad 210 whhin ASIC 120 in FIG. 1. I/O pad 210 provides intei-connection between circuitry internal to ASIC 120 and external circiatry. I/O pad 210 may be electrically compled to an external pin of an IC package via a bond wire, a lead frame finger, etc. (not shown in FIG. 1). I/O pad 210 is associated with I/O circuit 220 that provides signal drive and buffering for the T/0 pad. [0026J For the embodimeiU shown in FIG. 2, I/O circuit 220 includes an output driver 230, an input bulTer 240, and an electro-static discharge protection device (BSD) 250. Output driver 230 provides level shifting and signal drive for a digital signal being sent by ASIC 120 via J/O pad 210. Output driver 230 may be implemented as described below. Input buffer 240 provides buffering for a digital signal received via I/O pad 210. BSD 250 provides protection against electro-static discharge and may be implemented with a clamp diode that is coupled between a supply voltage and I/O pad 210. 10027} As shown In FIG. 2, the digital signals sent and received via I/O pad 210 are at a higher pad supply voltage, VP,AD, whereas the digital signals internal to ASIC 120 are at a lower core supply voltage, VCORK- Por example, V'PAD may be 3.3, 2,6 or 1.8 volts (V), and VCORK n:iay be 1.0 or 1,2 volts. Output driver 230 performs level shifting between Vcosji: atid VyAo- Output driver 230 should have the following characteristics; • No leakage between the core and pad supply voltages; and • Reliable and correct translation between the core and pad supply voltages. These desired characteristics may be achieved with the output driver described below. [00281 FIG. 5 shows a block diagram of an output driver 230a, which is an embodiment of output driver 230 in FIG. 2. For this embodiment, output driver 230a includes a pre-diiver 3X0 and a driver 360. Pre-driver 310 includes a latch 320, a latch driver 330, and buffers 340 and 350. I-aich driver 330 receives a digital input signal VIN from circuitry within ASIC 120, detects for a change in logic value on tlie VJN signal, and writes the detected logic value to latch 320. Latch 320 stores the logic value written by latch driver 330 and provides a latch output signal, Vj.,. Buffer 340 buffers the VL signal and provides a first driver signal, V|. Bufffjr 350 buffers the VIN signal and provides a second driver signal. Vs. The V| and Vz signals have the same logic value but are at different voltage levels. Driver 360 receives the Vj and V3 .signal.'? and provides a digital output signal, Vour, for an associated I/O pad 210, |0029| FIG, 3 shows the supply voltages for each circuit element within output driver 230a. Latch 320 operates between Vp.4.t) and an inten.nediale supply voltage. Vr,\i. Latch driver 330 operates between an upper voitage (which may be VCORK or VJHT) and a low supply voltage Vssc, which is typically circuit ground or OV. Buffer 340 operates between VI>AD and VINT- Buffer 350 operates between VCORE and Vssc-Driver 360 operates between V^AD and a low supply voltage Vssp. which is also typically circuit groand or OV. |0030| FIG. 3 also shows the range of voltages for each signal within output driver 230a. The VIK and Vj signals have a .range of OV to VCORB- The Vt and Vi signals have a range of VINT to VT>AD and are tlius shifted up to the higher pad supply voltage. The VOLT signal has a range of OV to Vp^vo- As indicated in FIG. 3, the signals along the lower signal path are at the same voitage range as the digital signals internal to ASIC 120. The signals along the upper signal path are at a higher voltage range between VJ>,'T and VfAa. [0031J VINT may be generated to satisfy the following conditions; where V^s max is the majdraura gate-to-source voltage for a diin-oxide F^T; V(p is the threshold voltage for the tliin-oxide P-FETs used in driver 360; and fj is a scaling factor. For example, considering only the condition in equation (1), if Vp^.^^) = 2.7V and Vg,..„,«^T^1.3V. AS another example, if V,,..y5 ==^ 1.8V and \».m^ °" 1-4V, then Vjjyi. > 0.5V, With VINT defined as shown in equation (I), a digital signal in the upper signal path would have a voltage that is less than or equal to Vp.\o for logic high and a voltage that is greater than or eq«al to V;PAD, - VPAD MAD for logic low. The condition in equation (1) ensures that the maximum voltage across any two terminalls of a FET in the upper signal path is within specified limits when the FET is turned on and conducting current The condition in equation (2) ensures that the P-FETs in driver 360 turn on. rj may be set to 2 or 3 to ensure that the P-FETs fully turn on. Vtst may be generated in various manners such as with an on-chip voltage regulator, a current- source bias circuit, etc. VINT may also be an external voltage that is provided to ASIC 120. VtjsT may aJso be designed to track VpJ^o so that VJK, mo.v is not violated. (0032} In general, the FETs may be stacked, and VIOT tnay be generated such that (1) the maximum voltage applied across the gate and source or drain, Vgaaax, and (2) maxinum voltage applied across the drain and source, Vd max, are both salisfied for each of the FETs. Stacking and increased cheinnd lengths tend to reduce isKies relating to Vts, and Vg and Vgd become the more critical parameter. [00331 FIG. 4 shows a schematic diagiam of an output driver 230b, which i« an embodiment of output driver 230a in FIG. 3. For this embodiment, latch 320 includes two inverters 420 ajod 422 that are coupled back-to-back. The output of inverter 420 couples to the input of inverter 422, and tlie output of inverter 422 couples to the input of inverter 420. Each inverter couples to VPAD for the upper supply voltage and to Vi^-r for the lower supply voltage. Each inverter provides a digital output signal having a voltage range of VI,ST to VPAIJ. }0034] For the embodiment shown in FIG. 4, latch driver 330 iacludes N-FETs 430, 432, 440 and 442, gate control circuits 434 and 444, and an inverter 446. N-FETs 430 and 432 are stacked and form the left branch. N-FET 430 has its source coupled to Vssc and its drain coupled to the source of N-FET 432. N-FET 432 h&s its drain coupled to node Ni, which is the input of inverter 420. The gates of N-FETs 430 and 432 are coupled to gate conuol circuit 434, which also receives the VIN signal. N-FETs 440 and 442 are also stacked and form tiiie right branch. N-FET 440 has its source coupled to Vssc and its drain coupled to the source of N~FET 442. N-FET 442 has its drain coupled to node N2, which is the input of inveiter 422, The gates of N-FETs 440 and 442 are coupled to gate control circuit 444, which also receives a Vi>j signal. Inverter 446 receives the VIN signal and provides the VIN signal, which is an inverted Vi> particular, inverter 420 senses he logic low at node Nj and provides a loj^c high at node N2. and inverter 422 senses the logic high at node N^ and provides a logic low at nodeK). j[003 FETs 440 and 442 are turned on for a short period of lime by gate control circuit 444 and pull down node N2 to logic low. After the short period of time, N-FET 440 and/or N-FET 442 are turned off by gate control circuit 444, Latch 320 latches and retains tibe logic low at node N3. Jn paiticular, inverter 422 provides a logic high at node Ni, and inverter 420 provides a logic low at node Nj. |0037{ Latch driver 330 thUsS "writes" a zero to either node Nj or N3 depending on the logic value of the Vm signal. The left branch is turned on to write a zero to node Ni, and the right branch is ttimed on TO write a zero to node N3- "When the left branch is turned on, current flows througli N-FETs 430 and 432. the drain of N-FET 430 rises, and the voltage at node Ni is divided across both N-FETs 430 and 432. Jf N-FETs 430 and 432 have the same size or dimension, then the voltage at node N.i i* divided evenly across N-FETs 430 and 43 2. [0038} FIG. 4 shows an embodiment in which two N-FETs are stacked for each famnch. hi general, the number of IM-FETs to stack, for each branch, L, may be given as: Eq(3) where "T T' denotes a ceiling operator that provides the next larger integer value for Vi'AiVVgg max- For example, two stacked N-FETs should be used for each branch if Vp^, -1.8V and V,..(,j^p ^ 1.2V. Three stacked N-FETs should be used for each branch if Vpao.'=:2.6V a.nd Vcofts - '-^V, etc. Using a sufficient number of N~FETs for each branch ensuses tliat (1) the maximum voltage applied across the gate and the dx-ain or source is within V^, max and (2) the maximum voltage applied across the drain and soxirce is within V^jjjv^^ for each N-!FET when the N-FET is turned on and conducting. |0039| .FIG. 5 shows an exemplary timing diagram for the Vr.v signal as well as the VA and VB signds provided to the gates of N-FETs 430 and 432, respectively, in FIG. 4. For this embodiment, the Vi and V v signals are initially at logic low, and the VB signal is at logic high. .N-FET 430 is turned off, N-FET 432 is turned on, and the left branch is turned off. At time T\, the VIN signal transitions from logic low to logic high, and the V.A signal also transitions to logic high. N-FETs 430 and 432 are both turned on, and the left brmich is turned on and pulls node Nj to logic low. A short time later, at time T2, (iie VB signal transitions to logic low, N~EET 432 is turned oiT, and the left branch is turned off. Thus, N-FETs 430 and 432 are both turned on for only a short time duration TON* between times Ti and Ta. At rime Tj, the Vi>^ signal transitions from logic high to logic low, the VA signal also transitions to logic low, at^d the Vn signal traitsitions to logic high. N-PET 430 is turned off, N-FET 432 is turned on, and the left branch remains off. 10040} In general, tiie VA signal for N-FET 430 and the YB signal for N-FET 432 may be generated in various manners such that the left branch is enabled for a time period that is sufficiently long to write a zero to node INI.. FIG. 5 shows one embodiment of the VA and V» signals. In another embodiment, the VA and VB signals are swapped so that N«FET 430 is turned off when die VK,\ |0042| FIG. 6 shows an embodiment of gale control circuit 434 that can generate the VA and VB signals shown in FIG. 5 for N-FETs 430 and 432, respectively. For this embodiment, gate control circuit 434 includes K series-coupled inverters 610a througi) 61 Ok and a HAND gate 612, where K is an even integer that is greater than one. The Ytfi signal is provided directly a$ the VA signal. The Vnv- signal is also provided to the input of inverter 610a and delayed by inverters 6lOa tlirough 610k, which provides a total delay of TON- NAND gate 612 receives tlie VIK signal on one input and the delayed YIN signal from invertesr 610k on another input and provides the VR signal for N-FET 432. f0043| The enibodiinent shown in FIGS. 5 and 6 provides some desirable characteristics. First, the VR signal follows the VA signal, even on the falUiig edge of the VA signal at time Tj in FIG. S. This ensures that N-FF;T 430 is turned otT before N-FET 432 is turned on. The left brajnch thus remains off during the falling edge of the ViK and VA signals at time T? and does not disturb the dhaige stoaed at node Ni. Second, any desired TON delay may be achieved by using a su0icient number of inverters 610. |0044{ FIG. 6 shows an embodiment for generating the V^. and VR signals shown in FIG. 5. These signals may also be generated with other circuits, and this is v>^tliin the scope of the invention. As noted above, the V^ and VB signals may also be defined in other manners. an.d other circuits may be used to generate these other versions of the VA and VB signals. Tlie gate control signals for N-FETs 440 and 442 for the right branch of latch driver 330 may be generated in the same manner as the V.^^ and Vi^ signals for N-FETs 430 and 432. [0045} Referring back to FIG. 4, the pai'ftsitic capacitance at node Ni and the drive capability of N-FETs 430 and 432 determine tlie amount of time to turn on the .N-F,ETs in order to pull down nodeNi to logic low. .In one embodiment, which is sbowi^ in FIG. 6, N-FETs 430 and 432 are turned on for a tlxed time duration TON, which may be longer than or equal to the expected amount of time needed to pull node Ni to logic low. In another embodiment, N-FETs 430 and 432 are turned on for a variable time duration determined by a sense circuit. The sense circuit senses the voltage at node Nj and turns otT N-FET 430 and/or 432 when this voltage is sufficiently low. (0046| FIG. 7 shows a schematic diagram of an embodiment of latch 320. For this embodiment, inverter 420 includes a P-FET 710 stacked with an N-FET 71.2. The gates of PnFIiT 730 and N~FET 712 coiipie together and form the input of inverter 420. The drains of P-FET 710 and N-FET 712 couple together and form tlie output of inverter 420. The source of P-FET 710 couples to VJ>AO, and the source of N-FET 712 couples to VINT. Inverter 422 includes a P-FET 720 and an N-FET 722 that are coupled in similar manner as P-FET 710 and N-FET 712, respectively, inverters 420 and 422 operate between VI?AI) and VINI-. |0047] Referring back to FIG. 4, latdi driver 330 wtites a zero to eitlier node Nj or N2 based on the VIN signal. Latch 320 stores this zt*ro as either logic low or logic high depending on the node being written to. Latch 320 provides a leveJ-sbifted Vj. signal that is at VPAB for logic high and is at VJNT for logic low. [0048] FIG, 4 also shows an embodiment of driver 360 within output drivei- 230b. For diis embodiment, driver 360 includes P-FETs 460 and 462 and N-FETs 464 and 466 thai are stacked together. P-FET 460 has its soui-ce coupled to VTAX), its gate receiving the V] signal from buffer 340, and its drain coupled to the source of P-FET 462. P-FET 462 lias its gate receiving a V? bias signal and its drain coupled to the drain of N-FET 464. N-FET 464 has its gate receiving a Vyr bias signal and its source coupled to the drain of N-FET 466. N-FET 466 has its gate receiving the Vj signal from buffer 350 and its source coupled to V,ssp. 10049} The Vt' and VN bias signals turn on P-FET 462 and IM-FET 464, respectively, all the time. Tlie Vp bias signal has a voltage that is selected to prevent P*FETs 460 and 462 from violating their Vg, ,„„x limits. Similarly, tlie V?^ bias .signal has a voltage that is selected 10 prevent N-FETs 464 and 466 from violating their Vj^ ,«:«limits. The V^ bias signal may be generated from VCORK or VrNT and may also be coupled directly to VcoJtc or VJ^T if reliability can be assured by using the voltage for one of these voltage supplies. The Vp bias signal may be covipled directly to VINT if reliability can be assmed witih tlie voltages for VfAi> and V^Nf-r. Alternatively, the Vj> bias signal may be generated with a reference circuit that can provide the desired voltage. 10050] P-FETs 460 and 462 and N-FETs 464 and 466 operate as an inverter. When. the Vi and V2 signals are at logic low, P-FET 460 is turned on by the Vi signal, H-FET 466 is turned off by the V2 signal» and P-FETs 460 and 462 drive the Voux signal toward VPAO. Conversely, when the \\ and Vi signals are at logic high, P-FET 460 is turned off by the Vi signal N-FET 466 is turned on by the V2 signal, and N-FETs 464 and 466 pull the Vou^r signal toward Vsav- The VQVT signal thus swings the full vollage range from OV to VpAr> even tliough each PET within driver 360 swings only a fraction of the full range. If P-FETs 460 aiid 462 have Ihe same size, then the voltage between V,p,\t> and Vout is divided ecjualiy between the two P-FETs. Similarly, if N-FETs 464 and 466 have the same size, then the voltage between Voirr and VSSP is divided equally between the two N-FBTs. [OOSl] FIG. 4 shows an embodiment in which two P-FETs and two N-FETs are stacked in driver 360. The number of P-FETs (L) and the number of .N-FETs (L) to stack, may be determined as shown in equation (3). L ■■• I P-FETs may be turned on all the lime, and one P-FET (e.g., the topmost P-T?ET) may be controlled witli the Vj signal. Similaily, L-l N-FETs may be tuned on all the time, and one N-FET (e.g., the bottommost N-FET) may be controlled with the Va signal. L-l bias signals may be used for the L-l, P-FETs that are turned on all the time, md .L ~ 1 bias signals may be used for tlie L-l N-FETs tliat are turned on all the time. These bi^ signals may be generated based on VCORE, VIKT and/or Vjvw such that all of the P-FETs and N-FBTs do not violate their Vg^msx limits. }0052| The signal inversion by driver 360 may be compensated in various manners. For example, buffers 340 and 350 may be replaced with inverters, the Vxtn signal may be inverted, the VIIN signal may be provided to gate control circuit 444, and the VIN signal may be provided to gate control circuit 434, and so on. 10053} The output drivei" described herein may have various advantages. First, the circuits within pre-driver 310 may operate based on digital signals. Each digital signal transitions between an upper voltage and a lower voltage for a specific voltage range. This avoids the need to generate bias and reference voltages for the pre-driver. Second, there may be no leakage paths for static current during steady state. Each circuit is turned off once steady state is reached. Third, N-FETs may be used as pull-down transistors in latch driver 330. N-FETs are much more effective than P-FETs at pulling down a node. Fourth, the digital Vn^t and VL signals for driver 360 xnay be buffered to achieve faster operating speed. FifUi, just about any VI>AJ> and VCORK voltages may be supported by stacking a sufficient number of N-FETs and P-FETs and by generating tlie proper gate control signals in latch driver 330. |0O54| FIG. 8 shows a schematic diagram of an input butYer 240a, which is an embodiment of input buffer 240 in FIG. 2. For this embodiment, input buffer 240a includes ati N-FET 810, a P-FET 812, and inveiters 814 and 816. N-FET 810 has its drain coupled to I/O pad 210, its gate coupled to VINT, and its source coupled to the input of inverter 814. P-FET 812 has its source coupled to VCORE, its gate coupled to the output of inverter 814, and its drain coupled to tlie input of inverter 814. inverters 814 and 816 are coupled in series. Inverter 816 provides a voltage-translated diptal signal. VINT generated for the output driver is advantageously used for the input buffer. |00S5) N-FET 810 attenuates the digital signal received from I/O pad 210. N-FET 810 ensures that the voltage at node A, which is the input of inverter 814, as maintained below a large vaJue when node A is driven from I/O pad 210. In general, L - 1 N-FETs may be slacked and coupled between 170 pad 210 and the input of Inverter 814, where L may be determined as shown in equation (3). P-FET 812 ensures that node A rises to VcoRB once itiverter 814 is tripped. The pull-up action by P-FET 814 is a form of positive feedback that speeds op inverter 814 and ensures that there is good switching on an input rising edge. |0056| The output driver described herein may be fabricated in various IC processes such as CMOS, N-MOS, P-MOS, bipolar, bipoiar-ClVlOS (Bi-CMOS), etc. The output driver may also be used for variotis types of IC, as noted above. |0057| the previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and Uie general principles defined herein may be applied to other embodiments without departing from the spirit or scope of tlie invention. Thus, the present invention is not intended to be limited to tlie embodiments shown herein but is to be accorded the wdest scope consistent with the principles apd novel features disclosed herein. (0058J WHAT IS CLAIMED IS: CLAIMS 1. An integrated circuit comprising: a latch configured to provide a first digital signal having a first voltage range determined by a first supply voltage and an intermediate voltage; and a driver coupled to the latch and configured to receive the first digital signal and a second digital signal and lo provide a digital output signal, wherein the second digital signal has a second voltage range determined by a second supply voltage and circuit ground, wherein the digital output signal has a third voltage range determined by the first supply voltage and circuit ground, and wherein the fust supply voltage is higher than the second supply voltage. 2. The integrated circuit of claim 1, wherein the latch comprises first and second inverters coupled between the first supply voltage and the intermediate voltage. 3. The integrated circuit of claim 1, further comprising; a latch driver coupled to the latch and configured to write logic values to the latch. 4. The integrated circuit of claim 3, wherein the latch comprises first and second nodes, and wherein the iatch driver is configured to pull down the first or second node to write a logic value to the latch. 5. The integrated circuit of claim 4, wherein the latch driver is configufed to pull down the first or second node for a predetertnined time duration to write the logic value and to turn off after the predetermined time duration. 6. The integrated circuit of claim i, further comprising: a latch driver coupled to the latch and comprising: a first set of at least two N-channe! field effect transistors (N-F£Ts) stacked together and configured to pull down a first node within the latch to write a logic high to the latch, and a second set of at least two N-FETs stacked together and configured to puU down a second node within the latch to write a logic low to the latch. 7. The integrated circuit of claim 6, wherein the latch driver further comprises a first cotitro) circuit configured to generate a first set of at least two control signals for the first set of at least two N-FETs, and a second control circuit configured to genesrate a second set of at least two contro! signals for the second set of at le-ast two N-FETs. 8. The integrated circuit of claim 7, wherein the first set of at least two control signals turn on the first set of at least two N-FETs for a predetermined time duration to write the logic high to the latch and turn off at least one of the N-FETs after the predetermined time duration. 9. The integrated circuh of claim 1, further comprising; a first butler coupled to the latch and the driver and configured to receive the first digital signal and to provide a first buffered .signal having the first voltage range, wherein the driver is configured to receive the first buffered signal. 10. The integrated circuit of claim 9, further compri sing: a second buffer coupled to the driver and configured to receive a digital input signal and to provide the second digital signal. 11. The integrated circuit of claim 1, wherein the driver comprises at least two P-ohannel field ctTect transistors (P-FETs) and at least two N-channel field effect transistors (N-FE'fs) coupled between the first supply voltage and circuit ground. 12. The integrated circuit of claim 11, wherein the at least two F-FETs and the at least two N-FETs are stacked together, wherein a toptnost P-FET among tlie at least two P-FETs receives the first distal signal, and wherein a bottoramost N-FET among the at least two P-FETs receives the .second digital signal. 13. The integrated circuit of claim 1, wherein the latch and the driver comprise only thin-oxide field effect transjgtors (KETs). 14. The integialed circuit of claim 1, further comprising: an input buffer configured to receive a digital input signal having the third voltage range and to provide a buffered digital input signal having the second voltage range, 5. An integrated circuit comprising; a pre-driver configured to generate first and second digital signals based on a digital input signal, wherein the first digital signai has a first voltage range detemined by a first supply voltage and an intermediate voltage, wherein the second digital signal has a second voltage range determined by a second supply voltage and circuit ground, and wherein the first supply voltage is higher than the second supply voltage, and a driver coupled to the pre-driver and configured to rec-eive the first and second digital signals and to provide a digital output signal having a third voltage range determined by tha first supply voltage and ciroiitground, 16. The integrated circuit of claim .15, wherein the pre-driver is configured lo generate at least one digital control signal based on the digital input signal and to generate the first digital signal with the at least one digital control signal. 17. The integrated circuit of claim 15, v/herein the first supply voltage is for an esternal device coupled to the integrated circuit, and wherein the second supply voltage is for circuitry within the integrated circuit. 18. The integrated circuit of claim 15, wherein the pre-driver and the driver comprise only thin-oxide field effect transistors (EETs). 19. The integrated circuit of claim 18, wherein each of the thin-oxide FETs in the pre-driver and the driver has a gate-to-source (Vg) voltage that is less than the second supply voltage when the thin-oxide F.ET is turned on and cond\icting current. 20. An apparatus comprising: means for generating first and second digital signals based on a digital input signal, wherein the first digital signal has a first voltage range detennined by a ilrist supply voltage and an intermediate voltage, wherein the second digital signal has a second voltage range determined by a second supply voltage and circuit ground, and wherein the first supply voltage is higher than the second supply voltage; and means for providing a digital output signal based on the first and second digital signals, the digital output signal having a third %'oltage range determined by the first supply voltage and circuit ground. 21. The apparatus of claim 20, wherein the means for generating the first and second digital signals comprises meaiis for latching the digital input signal to generate the first digital signal. 22. The apparatus of claim 21, wherein the means for latching the digital input signal comprises means for pulling down a first node or a second node based on a logic value of the digital input signal, and means for stori ng tlie 1 ogi c val ue. 23. The apparatus of claim 20. wherein the means for generating the first and second digital signals comprises means for generating at least one digital control signal based on the digital input signal, and means for generating the first digital signal based on the at least one digital control signal. 24. A method comprising; generating first and second digital signals based on a digital input signal, wherein the first digital signal has a first voltage range detennined by a fust supply voltage and an intennediate voltage, wherein the second digital signal has a second voltage range determined by a second supply voltage and circuit ground, and wherein the first supply voltage is higher than the second supply voltage; and providing a digital output signal based on the first and second digital signals, the digital output signal having a third voltage range determined by liie first supply voltage and circuit ground. 25. The method of claim 24, wherein the generating the first and second digital signals latching the digital input signal to generate the first digital signal. 26. An integrated circuit comprising: an output driver configured to receive an internal input signal having a first voltage range determined by a first supply voltage and an intermediate voltage, to generate a first digital signal having the first voltage range, to generate a second digital signal having a second voltage range determined by a second supply voltage and. circuit ground, and to provide a digital output signal having a third voltage range determined by the first supply voltage and circuit ground, wherein the first supply voltage is higher than the second supply voltage; and an input buffer configured to receive an external input signal having the third, voltage range and. to provide a buffered input signal having the second voltage range. 27. The integrated circuit of claim 26, wherein the input buffer comprises an N-channel field effect transistor (N-PET) coupled to tlie intermediate voltage and configured to receive the extemai input signal, and an inverter coupled to the N-FET and configured to receive the external input signal via the N-FET, 28. The integrated circuit of claim 27, wherein the input buffer further comprises a ?-channel field effect tnansistor (P-FET) coupled to the second supply voltage and to an input and an output of the inverter. 29. The integrated circuit of claim 26, wherein the output driver and the input buffer comprise only thin-oxide field effect transistors (FETs).

Documents:

3344-CHENP-2008 AMENDED CLAIMS 20-11-2013.pdf

3344-CHENP-2008 AMENDED CLAIMS 22-07-2013.pdf

3344-CHENP-2008 AMENDED PAGES OF SPECIFICATION 20-11-2013.pdf

3344-CHENP-2008 AMENDED PAGES OF SPECIFICATION 22-07-2013.pdf

3344-CHENP-2008 EXAMINATION REPORT REPLY RECEIVED 20-11-2013.pdf

3344-CHENP-2008 EXAMINATION REPORT REPLY RECEIVED 22-07-2013.pdf

3344-CHENP-2008 FORM-5 22-07-2013.pdf

3344-CHENP-2008 OTHERS 22-07-2013.pdf

3344-CHENP-2008 AMENDED PAGES OF SPECIFICATION 07-01-2014.pdf

3344-CHENP-2008 AMENDED CLAIMS 07-01-2014.pdf

3344-chenp-2008 claims.pdf

3344-CHENP-2008 CORRESPONDENC OTHERS 20-12-2013.pdf

3344-CHENP-2008 CORRESPONDENCE OTHERS 07-01-2014.pdf

3344-chenp-2008 description (complete).pdf

3344-CHENP-2008 FORM-3 20-12-2013.pdf

3344-CHENP-2008 OTHER PATENT DOCUMENT 20-12-2013.pdf

3344-chenp-2008 pct search report.pdf

3344-chenp-2008 pct.pdf

3344-CHENP-2008 POWER OF ATTORNEY 22-07-2013.pdf

3344-chenp-2008 correspondence -others.pdf

3344-chenp-2008 drawings.pdf

3344-chenp-2008 form-1.pdf

3344-chenp-2008 form-18.pdf

3344-chenp-2008 form-26.pdf

3344-chenp-2008 form-3.pdf

3344-chenp-2008 form-5.pdf