Title of Invention	TRANSLATION LOOKASIDE BUFFER LOCK INDICATOR
Abstract	A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.

Title of Invention

TRANSLATION LOOKASIDE BUFFER LOCK INDICATOR

Abstract

A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.

Full Text	The persent invention relates generally to the filed of processors and in particular to a system and method of locking entries in one more Translation Lookaside buffers against replacement....................................................

Documents:

« Previous Patent

Next Patent »

Patent Number

259553

Indian Patent Application Number

419/MUMNP/2008

PG Journal Number

12/2014

Publication Date

21-Mar-2014

Grant Date

18-Mar-2014

Date of Filing

05-Mar-2008

Name of Patentee

QUALCOMM INCORPORATED

Applicant Address

5775 MOREHOUSE DRIVE, SAN DIEGO, CALIFORNIA 92121-1714,

Inventors:

#	Inventor's Name	Inventor's Address
1	AUGSBURG, VICTOR ROBERTS	304 VERSAILLES DRIVE, CARY, NORTH CAROLINA 27511,
2	DIEFFENDERFER, JAMES NORRIS	4000 Inkberry Court Apex North Carolina 27539 (US)
3	BRIDGES, JEFFREY TODD	3513 Timberwood Court Raleigh North Carolina 27606 (US).
4	SARTORIUS, THOMAS ANDREW	1600 Olde Chimney Court Raleigh North Carolina 27614 (US).

PCT International Classification Number

G06F12/12

PCT International Application Number

PCT/US2006/032902

PCT International Filing date

2006-08-22

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	11/210,526	2006-08-23	U.S.A.