Title of Invention	"A METHOD OF VARYING THRESHOLD VOLTAGE IN MOSFETS"
Abstract	This invention relates to a method of varying threshold voltage in closely located MOSFETs comprising the steps of varying the spacing between the selective buried insulating layer disposed under the source and drain of the .MOSFET, where the insulating layer is such as silicon dioxide or any other appropriate insulator and there is provided a method of varying threshold voltage in closely located MOSFETs comprising steps of positioning of the MOSFETs on a chip with different spacing between the buried insulating layer disposed under the sources and drain of the MOSFET; and increasing or decreasing the difference in the threshold voltages between the different devices by biasing the well ve/+ve w.r.t the source of the MOSFET to obtain larger/smaller threshold voltages differences between the devices.

Title of Invention

"A METHOD OF VARYING THRESHOLD VOLTAGE IN MOSFETS"

Abstract

This invention relates to a method of varying threshold voltage in closely located MOSFETs comprising the steps of varying the spacing between the selective buried insulating layer disposed under the source and drain of the .MOSFET, where the insulating layer is such as silicon dioxide or any other appropriate insulator and there is provided a method of varying threshold voltage in closely located MOSFETs comprising steps of positioning of the MOSFETs on a chip with different spacing between the buried insulating layer disposed under the sources and drain of the MOSFET; and increasing or decreasing the difference in the threshold voltages between the different devices by biasing the well ve/+ve w.r.t the source of the MOSFET to obtain larger/smaller threshold voltages differences between the devices.

Full Text	FIELD OF INVENTION This invention relates to a method of varying threshold voltage in closely located MOSFETs. PRIOR ART Many of the novel application with electronics are possible because of integrated circuits where devices in a circuit are fabricated or. a single silicon wafer. One of the key advantages of this is that the characteristics of the devices are very close to each other which make the functionality of the circuit predictable. However, for some selected circuits, transistors are needed to have different threshold voltage. This may be needed to achieve different on currents (for higher speed) or off currents (for lower sub-threshold leakage) in selected transistors. This is often accomplished in the industry by allowing different gate oxide thickness and/or threshold adjust implant. Due to lithographic and implantation limits, it becomes difficult to place transistor devices with different threshold voltages next to each other sufficiently close to achieve compactness of circuits. This results in extra cost by way of chip real-estate. This real estate cost can become particularly significant in replicated circuits, such as SRAMS, where each unit may be replicated many tens of thousands of times. The present invention suggests a method of varying the 'hrcshok! of at least two transistors which can be located next to each otherlocated as close as the technology will allow any two transistors lo be located with no extra processing cost. OBJECTS OF THE INVENTION The primary object of the present invention is to propose a method of varying threshold voltage in MOSFETs located on the same chip. Another object of the present invention is to propose a method of varying threshold voltage in closely located MOSFETs. Still another object of the present invention is to propose a method of varying threshold voltage in closely located MOSFETs which is cost effective as compared to the prior art. Another object of the present invention is to propose a method of varying threshold voltage in closely located MOSFETs which involves less number of steps as compared to the known art. Further object of the present invention is to propose a method of varying threshold voltage in closely located MOSFETs which allows the transistors to be located close to each other. Still further object of the present invention is to propose a method of varying threshold voltage in closely located MOSFETs which allows compactness of circuits. STATEMENT OF THE INVNETION According to this invention there is provided a mot hod of varying threshold voltage in closely located MOSFETs comprising the steps of varying the spacing between the selective buried insulating layer disposed under the source and drain of the MOSFET, where the insulating layer is such as silicon dioxide or any other appropriate insulator. Further, according to this invention there is provided a method of varying threshold voltage in closely located MOSFETs comprising steps of positioning of the MOSFETs on a chip with different spacing between ?.heburied insulating layer disposed under the source and drain of *ho MOSFET; and increasing or decreasing the difference in the threshold voltages between the different devices by biasing the well ve/Jve V.MM the source of the MOSFET to obtain larger/smaller threshold volumes differences between the devices. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWING Further objects and advantages of this invention will be more apparent from the ensuing description when read in conjunction with the accompanying drawing and wherein: Figure . 1 shows the SELective Buried OXide (SELBOX) structure with buried oxide under the source and drain of the MOSFET. Figure .2 shows the plot showing threshold (Vt) variation in NMOSFET with different substrate bias. DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO ACCOMPANYING DRAWING. The proposed application provides a method of varying threshold voltage in closely located MOSFETs, which may be explained with the help of the following embodiments b} the scope of the invention to the same. First Embodiment The threshold of the transistor devices is a function of the spacing of the selective buried oxide (SELBOX). The threshold voltage increases or decreases as the SELBOX spacing increases or decreases respectively. Thus, when the device is being fabricated using the SELBOX technology of the present invention, the spacing in the buried oxide of the transistor may be increased to obtain a transistor with a larger threshold voltage. Second Embodiment It has also been observed that the effect of the body bias in the transistor is different for transistors with different spacing between the SELBOX. As the spacing is increased, there is larger and larger body effect. This allows the adjustment of the threshold in two ways: 1. When the devices are placed with the standard (minimum) spacing in a common doped well and the well is forward biased w.r.t. the device source, the threshold voltages of the devices which have larger SELBOX spacing will be incremented by a larger value compared to devices with smaller SELBOX spacing. 2. When the devices are placed with the standard (minimum) spacing in a common doped well and the well is forward biased w.r.t. the device source, then the threshold voltage of the devices which have larger SELBOX spacing will be decreased by a larger value compared to devices with smaller SELBOX spacing. Thus, by appropriate well biasing, different variation in threshold voltages can be achieved in devices which are located next to each other. For example: in the 65 nm technology, the targeted minimum spacing in the buried oxide is 65 nm. In the 90 nm technology, (he targeted minimum spacing in the buried oxide is 90 nm. The pitch of two transistors of the same type with different threshold voltage for a 65 nm technology is -65 + 200 nm wherein in the conventional methods, the spacing between two transistors is typically ~=65 + 200 + 200 nm; and in 90 nm technology is -90 + 270 nm wherein in the conventional methods, the spacing between two transistors is typically —90 + 270 + 270 nm. By making devices with different spacing in the SELBOX. different threshold voltages in MOSFETs can be achieved. The spacing between different threshold voltage MOSFETs can be much lower by this approach than the spacing allowed by threshold adjust implant process or multiple gate oxide processes know, as of today. The well bias may be used to change the nature of the circuit on the same chip by changing the relative threshold voltages in different threshold voltage devices. SOI, bulk and SELBOX device may all be fabricated on the same wafer with minimum spacing between each of them using any of the known SELBOX processing techniques in prior art and all of them will have different threshold voltage. In the existing processes, in order to get different threshold voltage for adjacent transistors, typically two approaches are taken: (i) use of different dose for the threshold adjust implant and/or (ii) use of different gate oxide thickness. The approaches known today need lithography to separate the transistors with different threshold adjust implant dose or to obtain varying oxide thickness. These lithography steps are low resolution (or they become too costly if one opts for high resolution lithography). Also, the very nature of implantation mandates a minimum distance between device that is getting the implant and the device that is not getting the implant. So, to achieve different threshold voltage transistors, the spacing between them has to be larger than the spacing achievable in the present invention. In the current invention, for a fabrication process where transistors are fabricated with selective buried oxide under them, multiple threshold transistors can be achieved with no extra processing steps. The threshold variation is achieved by varying the spacing between the selective buried oxide. The varying spacing is implemented by appropriate mask layou; and hence the processing steps are not modified in any way to achieve the multiple threshold transistors. The chief advantage of the current invention is the possibility of placing transistors of different threshold voltages in close proximity to each other. Moreover, for a fabrication process where transistors are fabricated with selective buried oxide under them, no extra steps will be needed to achieve different threshold voltage on neighbouring transistors. is to be noted that the present invention is susceptible to modifications, adaptations and changes by those skilled in the art. Such variant embodiments employing the concepts and features of this invention are intended to be within the scope of the presem invention, which is further set forth under the following WE CLAIM; 1. A method of varying threshold voltage in MOSFETs comprising the steps of: (a) varying the spacing between the SELective Buried Oxide (SELBOX), disposed under the source and drain of the MOSFET; (b) positioning of the MOSFETs on a chip with different spacing between the said SELBOX; and (c) increasing or decreasing the difference in the threshold voltages between the different devices by biasing the well positive or negative with respect to the source of the MOSFET to obtain larger or smaller threshold voltages differences between the devices. 2. A method as claimed in Claim 1 wherein insulating part of SEALBOX is formed either silicon dioxide or any other appropriate electrical insulator such as air, vacuum, sapphire, hafnium oxide, silicon nitride or as is available in that specific technology. 3. A method as claimed in Claim 1 or 2 wherein the spacing in the selective buried insulator is between O(zero) to the channel length which is 65 nm in the 65 nm technology, and greater than the size of the transistor device 4. A method as claimed in any of the preceding Claims wherein the transistors are located at minimum allowed pitch of 265 nm in case of a 65 nm technology and 365 nm in case of a 90 nm technology. 5. A method, as claimed in proceeding claims, used for varying threshold voltage in MOSFETs located on the same chip substantially as herein described with reference to accompanying drawing.

Full Text

FIELD OF INVENTION
This invention relates to a method of varying threshold voltage in
closely located MOSFETs.
PRIOR ART
Many of the novel application with electronics are possible because
of integrated circuits where devices in a circuit are fabricated or. a single
silicon wafer. One of the key advantages of this is that the characteristics
of the devices are very close to each other which make the functionality
of the circuit predictable.
However, for some selected circuits, transistors are needed to have
different threshold voltage. This may be needed to achieve different on
currents (for higher speed) or off currents (for lower sub-threshold
leakage) in selected transistors. This is often accomplished in the
industry by allowing different gate oxide thickness and/or threshold
adjust implant. Due to lithographic and implantation limits, it
becomes difficult to place transistor devices with different threshold
voltages next to each other sufficiently close to achieve compactness of
circuits. This results in extra cost by way of chip real-estate. This real
estate cost can become particularly significant in replicated circuits,
such as SRAMS, where each unit may be replicated many tens of
thousands of times.
The present invention suggests a method of varying the 'hrcshok!
of at least two transistors which can be located next to each otherlocated
as close as the technology will allow any two transistors lo be
located with no extra processing cost.
OBJECTS OF THE INVENTION
The primary object of the present invention is to propose a method
of varying threshold voltage in MOSFETs located on the same chip.
Another object of the present invention is to propose a method of
varying threshold voltage in closely located MOSFETs.
Still another object of the present invention is to propose a method
of varying threshold voltage in closely located MOSFETs which is cost
effective as compared to the prior art.
Another object of the present invention is to propose a method of
varying threshold voltage in closely located MOSFETs which involves less
number of steps as compared to the known art.
Further object of the present invention is to propose a method of
varying threshold voltage in closely located MOSFETs which allows the
transistors to be located close to each other.
Still further object of the present invention is to propose a method
of varying threshold voltage in closely located MOSFETs which allows
compactness of circuits.
STATEMENT OF THE INVNETION
According to this invention there is provided a mot hod of varying
threshold voltage in closely located MOSFETs comprising the steps of
varying the spacing between the selective buried insulating layer
disposed under the source and drain of the MOSFET, where the
insulating layer is such as silicon dioxide or any other appropriate
insulator.
Further, according to this invention there is provided a method of
varying threshold voltage in closely located MOSFETs comprising steps of
positioning of the MOSFETs on a chip with different spacing between ?.heburied
insulating layer disposed under the source and drain of *ho
MOSFET; and increasing or decreasing the difference in the threshold
voltages between the different devices by biasing the well ve/Jve V.MM
the source of the MOSFET to obtain larger/smaller threshold volumes
differences between the devices.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWING
Further objects and advantages of this invention will be more
apparent from the ensuing description when read in conjunction with the
accompanying drawing and wherein:
Figure . 1 shows the SELective Buried OXide (SELBOX) structure
with buried oxide under the source and drain of the MOSFET.
Figure .2 shows the plot showing threshold (Vt) variation in
NMOSFET with different substrate bias.
DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO
ACCOMPANYING DRAWING.
The proposed application provides a method of varying threshold
voltage in closely located MOSFETs, which may be explained with the
help of the following embodiments b} the scope of the invention to the same.
First Embodiment
The threshold of the transistor devices is a function of the spacing
of the selective buried oxide (SELBOX). The threshold voltage increases
or decreases as the SELBOX spacing increases or decreases respectively.
Thus, when the device is being fabricated using the SELBOX technology
of the present invention, the spacing in the buried oxide of the transistor
may be increased to obtain a transistor with a larger threshold voltage.
Second Embodiment
It has also been observed that the effect of the body bias in the
transistor is different for transistors with different spacing between the
SELBOX. As the spacing is increased, there is larger and larger body
effect. This allows the adjustment of the threshold in two ways:
1. When the devices are placed with the standard (minimum) spacing
in a common doped well and the well is forward biased w.r.t. the
device source, the threshold voltages of the devices which have
larger SELBOX spacing will be incremented by a larger value
compared to devices with smaller SELBOX spacing.
2. When the devices are placed with the standard (minimum) spacing
in a common doped well and the well is forward biased w.r.t. the
device source, then the threshold voltage of the devices which have
larger SELBOX spacing will be decreased by a larger value
compared to devices with smaller SELBOX spacing.
Thus, by appropriate well biasing, different variation in threshold
voltages can be achieved in devices which are located next to each other.
For example: in the 65 nm technology, the targeted minimum
spacing in the buried oxide is 65 nm. In the 90 nm technology, (he
targeted minimum spacing in the buried oxide is 90 nm.
The pitch of two transistors of the same type with different
threshold voltage for a 65 nm technology is -65 + 200 nm wherein in the
conventional methods, the spacing between two transistors is typically
~=65 + 200 + 200 nm; and in 90 nm technology is -90 + 270 nm wherein
in the conventional methods, the spacing between two transistors is
typically —90 + 270 + 270 nm.
By making devices with different spacing in the SELBOX. different
threshold voltages in MOSFETs can be achieved. The spacing
between different threshold voltage MOSFETs can be much lower
by this approach than the spacing allowed by threshold adjust
implant process or multiple gate oxide processes know, as of today.
The well bias may be used to change the nature of the circuit on
the same chip by changing the relative threshold voltages in
different threshold voltage devices.
SOI, bulk and SELBOX device may all be fabricated on the same
wafer with minimum spacing between each of them using any of the
known SELBOX processing techniques in prior art and all of them will
have different threshold voltage.
In the existing processes, in order to get different threshold voltage
for adjacent transistors, typically two approaches are taken: (i) use of
different dose for the threshold adjust implant and/or (ii) use of different
gate oxide thickness. The approaches known today need lithography to
separate the transistors with different threshold adjust implant dose or
to obtain varying oxide thickness. These lithography steps are low
resolution (or they become too costly if one opts for high resolution
lithography). Also, the very nature of implantation mandates a minimum
distance between device that is getting the implant and the device that is
not getting the implant. So, to achieve different threshold voltage
transistors, the spacing between them has to be larger than the spacing
achievable in the present invention.
In the current invention, for a fabrication process where transistors
are fabricated with selective buried oxide under them, multiple threshold
transistors can be achieved with no extra processing steps. The threshold
variation is achieved by varying the spacing between the selective buried
oxide. The varying spacing is implemented by appropriate mask layou;
and hence the processing steps are not modified in any way to achieve
the multiple threshold transistors.
The chief advantage of the current invention is the possibility of
placing transistors of different threshold voltages in close proximity to
each other. Moreover, for a fabrication process where transistors are
fabricated with selective buried oxide under them, no extra steps will be
needed to achieve different threshold voltage on neighbouring
transistors.
is to be noted that the present invention is susceptible to
modifications, adaptations and changes by those skilled in the art. Such
variant embodiments employing the concepts and features of this
invention are intended to be within the scope of the presem invention,
which is further set forth under the following

WE CLAIM;
1. A method of varying threshold voltage in MOSFETs comprising
the steps of:
(a) varying the spacing between the SELective Buried Oxide (SELBOX), disposed under the source and drain of the MOSFET;
(b) positioning of the MOSFETs on a chip with different spacing between the said SELBOX; and
(c) increasing or decreasing the difference in the threshold voltages between the different devices by biasing the well positive or negative with respect to the source of the MOSFET to obtain larger or smaller threshold voltages differences between the devices.

2. A method as claimed in Claim 1 wherein insulating part of SEALBOX is formed either silicon dioxide or any other appropriate electrical insulator such as air, vacuum, sapphire, hafnium oxide, silicon nitride or as is available in that specific technology.
3. A method as claimed in Claim 1 or 2 wherein the spacing in the selective buried insulator is between O(zero) to the channel length which is 65 nm in the 65 nm technology, and greater than the size of the transistor device

4. A method as claimed in any of the preceding Claims wherein
the transistors are located at minimum allowed pitch of 265
nm in case of a 65 nm technology and 365 nm in case of a 90
nm technology.
5. A method, as claimed in proceeding claims, used for varying threshold voltage in MOSFETs located on the same chip substantially as herein described with reference to accompanying drawing.

Documents:

2056-del-2005-abstract.pdf

2056-del-2005-Claims-(05-02-2014).pdf

2056-DEL-2005-Claims-(15-06-2012).pdf

2056-del-2005-claims.pdf

2056-del-2005-Correspondence Others-(05-02-2014).pdf

2056-del-2005-Correspondence Others-(12-12-2013).pdf

2056-DEL-2005-Correspondence Others-(15-06-2012).pdf

2056-del-2005-correspondence-others.pdf

2056-del-2005-description (complete).pdf

2056-del-2005-drawings.pdf

2056-del-2005-form-1.pdf

2056-del-2005-form-2.pdf

2056-del-2005-form-26.pdf

2056-DEL-2005-GPA-(15-06-2012).pdf

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Patent Number

258953

Indian Patent Application Number

2056/DEL/2005

PG Journal Number

08/2014

Publication Date

21-Feb-2014

Grant Date

18-Feb-2014

Date of Filing

02-Aug-2005

Name of Patentee

INDIAN INSTITUTE OF TECHNOLOGY

Applicant Address

KANPUR-208016, AN INDIAN INSTITUTE.

Inventors:

#	Inventor's Name	Inventor's Address
1	BAQUER MAZHARI	INDIAN INSTITUTE OF TECHNOLOGY, KANPUR-208016, INDIA.
2	S. SUNDAR KUMAR IYER	INDIAN INSTITUTE OF TECHNOLOGY, KANPUR-208016, INDIA.
3	CHANDER PAL	INDIAN INSTITUTE OF TECHNOLOGY, KANPUR-208016, INDIA.

PCT International Classification Number

H03F 003/16

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA