Title of Invention

A RECEIVER IN A DIGITAL COMMUNICATIONS SYSTEM COMPRISING A DATA LINK HANDLER WITH A TASK REGISTER, A SHADOW REGISTER AND HANDSHAKING MEANS

Abstract

A receiver comprising a data link handler is disclosed. The data link handler comprises a deinterleaver, a rate matcher and one or more decoders, wherein said deinterleaver is arranged to apply data via a buffer to said rate matcher and said rate matcher is arranged to apply data to said one or more decoders. The data link handler is characterized in that said deinterleaver, said rate matcher, and said one or more decoders each comprise a shadow register, a task register, and a handshaking means for managing data flow between them. A method of data link handling is also disclosed. The method comprises the processing steps of: deinterleaving data blocks; rate matching deinterleaved data blocks; and decoding rate matched data blocks, once the setting has been done by the CPU. Each of said processing steps comprises the steps of: reading data; indicating when data is read; shifting a task register comprising a list of transport channels; processing said data according to parameter values in a shadow register indicated by an output of said task register; and indicating when processed data is to be read. An effect is release of constraints in terms of latency for a device responsible for scheduling and control of the receiver.

Full Text

Transport channel decoding management in a UMTS Mobile Receiver Field of invention The present invention relates to a receiver comprising a data link handler in a digital communications system. The present invention also relates to a method of data link handling, and a data link handler in a digital communications system. Background of the invention Fig.l shows a conventional Universal Mobile Telecommunications System (UMTS) receiver 100 comprising a means 102 for transforming a radio-frequency signal 101 into a baseband signal 103, a demodulator 104 for demodulating the baseband signal 103, and a means 106 for deinterleaving, rate matching and decoding the demodulated signal 105. The means 106 for deinterleaving, rate matching and decoding the demodulated signal 105 work in the data link layer, which is a term used in the Open System Interconnection model which is known to a person skilled in the art, and is therefore referred to as a data link handler 106. The data link handler 106 output 107 is applied to further parts (not shown) of the UMTS receiver 100 for higher layer processing. Fig.2 shows a conventional data link handler 200 comprising a deinterleaver 202, a rate matcher 204 and one or more decoders 206. The one or more decoders 206 can be arranged in series or parallel, or any combination thereof. In the signal path 203 between the deinterleaver 202 and the rate matcher 204, a deinteleaver output buffer (not shown) is normally provided. Information about interleaving, rates, and codes is specified in 3GPP TS 25.212, which specifies multiplexing and channel coding for Frequency Division Duplexing (FDD) within UMTS, and a person skilled in the art is well aware of this specification. For every frame, the data link handler receives blocks of data from the demodulator. Processing of the data blocks corresponding to a frame in the data link handler is to start when data is ready in an output buffer of the demodulator, and has to be ready before data corresponding to a next frame is ready in the output buffer of the demodulator. Thus, on the one hand the processing in the data link handler is data iriven. On the other hand, the settings are controlled by a Central Processing Unit (CPU, not shown) of the receiver. US 2003/0037749-A1 discloses a method and user equipment for processing received data in user equipment connected to a communications network such that the bad on the receiver is decreased. The processing comprises receiving radio frames, identifying transport block sizes of the radio frame, and determining whether the radio frame includes transport blocks that are directed to the user equipment. Blocks associated to transport channels not directed to the user equipment are not processed. A problem of the prior art is the requirements in terms of latency and processing power for a device scheduling the data processing units, particularly in case this device is also used for other time-constrained tasks in the system. Summary of the invention An object of the present invention is to provide a solution with improved data ink layer processing. The above object is achieved according to a first aspect of the present invention 3y a receiver in a digital communications system, which system comprises a data link handler comprising a deinterleaver, a rate matcher and at least one decoder. The ieinterleaver is arranged to apply deinterleaved data comprising a plurality of transport channels via a buffer to the rate matcher, and the rate matcher is arranged to convey rate matched data to said at least one decoder. The receiver is characterized in that the ieinterleaver, the rate matcher, and said one or more decoders each comprise a shadow register, a task register, and a handshaking means for managing data flow between ;hem. The shadow register is arranged to hold parameter values representing characteristics of the transport channels for data link layer processing, and the task register is arranged to hold a list of transport channels to be processed. An effect is release of constraints in terms of latency for a device responsible for scheduling and control of the receiver. Generally, this device is a CPU or DSP coupled to the data link handler, and this CPU or DSP normally manages other subsystems. Thus, an advantage is that the proposed architecture allows scheduling flexibility for the part related to the data link handler. An advantage is that requirements on processing power are decreased since a CPU or a DSP of the receiver is relieved from handling data flow in the data link handler. This implies a low CPU requirement and low latency solution with maintained flexibility. An advantage of the task register is that the data link handler can be data driven more easily, i.e. once the CPU or DSP has programmed the shadow registers, processing can start as soon as corresponding data is present, since the data link handler knows in advance the transport channels that are to be processed. An advantage of the shadow register is that parameter values can be pre-programmed in the data link handler. In effect, this enables processing with reduced involvement of the receiver's CPU or DSP, since necessary parameter values for data link layer processing are programmed batch-wise. The task register may be arranged to shift said list according to a first in first out principle, where the output of said task register indicates the transport channel to be processed. An advantage of this is enabling of an efficient implementation where tasks in the form of identifiers of the traffic channels to be processed are loaded into the input of the first in first out register, and the identifier of the traffic channel to be processed is present on the output. The handshaking means may be arranged to signal an indication comprising information to a next processing unit that a data block is ready for reading and that a data block is read to indicate to a previous processing unit that space is free for a next data block. An advantage of this is provision of means for autonomous flow control between processing parts of the data link handler. Each deinterleaver, rate matcher, and said at least one decoder may further comprise a processing unit, wherein the processing unit is arranged to control shifting of the task register, selection from the shadow register, and signalling on the handshaking means. The processing unit may comprise a state machine, arranged to generate control signals for controlling the shifting of the task register, selection from the shadow register, and signalling on the handshaking means. The above object is obtained according to a second aspect of the present invention by a method of processing transport channel data in a data link handler in a digital communications system, comprising the processing steps of: deinterleaving data comprising a plurality of transport channels; rate matching deinterleaved data; and decoding rate matched data. Each of the processing steps comprises the steps of: reading data; providing an indication that contains information that data is read; shifting a task register that contains a list of transport channels, wherein the task register comprises a list of transport channels to be processed; processing the data according to parameter values that represent characteristics of the transport channel in a shadow register indicated by an output of said task register; and providing an indication that contains information that processed data is to be read. The step of shifting may be a first in first out shift. The method may further comprise the step of programming the shadow registers with the parameter values. Each processing step may comprise the steps of: controlling said reading, indication providing, shifting, and processing steps by a state machine. The advantages of the second aspect of the invention are similar to those of the first aspect. Brief description of the drawings The above, as well as additional objects, features and advantages of the present invention, will be better understood through the following illustrative and non-limiting detailed description of preferred embodiments of the present invention, with reference to the appended drawings, wherein: Fig.l shows a conventional UMTS receiver; Fig.2 shows a conventional data link handler for a UMTS receiver; Fig.3 shows a processing means comprising a means for controlling data flow in a data link handler according to an embodiment of the present invention; Fig.4 is a flow chart illustrating a method of processing data blocks in a data link layer according to an embodiment of the present invention; and Fig. 5 is a flow chart illustrating data block handling in a processing step according to an embodiment of the present invention. Detailed description of preferred embodiments The basic approach according to the present invention is to add features to existing processing blocks to allow data block processing with no extra latency, while improving the performance of data block handling and decreasing the processing power requirements, particularly on digital signal processors (DSP) and/or central processing units (CPU) of the receiver. The embodiments described below are described in relation to a UMTS receiver. However, the basic principle can be used in receivers adapted to other digital communications systems, such as CDMA2000, GSM, EDGE, NADC, GPRS, IS-95, cdmaOne, PDC, PHS, and short-link radio systems. Fig.3 shows a processing means 300 capable of controlling data block flow in a data link handler according to an embodiment of the present invention. The processing means can be a deinterleaver, rate matcher, or decoder. Data flow control is performed by a task register 302, a shadow register 304, and a processing unit 306. The task register 302 comprises a first in first out (FIFO) shift register which is loaded by a CPU of the receiver with transport channel (TrCH) numbers to be processed. Along with shifting the task register, a TrCH number is provided, which indicates the TrCH'to be processed. The shadow register 304 is loaded with parameter values for the processing of a TrCH. The output of the task register 302 gives the TrCH to be processed and the associated parameter values are collected from the shadow register 304. A state machine 308 of the processing unit 306 controls the shifting of the task register 302 and the collection of parameter values from the shadow register 304. The state machine 308 also generates indicator signals 310, 312. Indicator signal 310 indicates to a preceding processing means that data is read from the preceding processing means. Indicator signal 312 indicates to a subsequent processing means that data is ready for reading at an output. Similarly, the state machine receives corresponding indicator signals 314, 316 from preceding and subsequent processing means. This flow control is referred to as handshaking, and the mechanism is therefore referred to as a handshaking means. Selection of parameter values is illustrated as a selector 318 connected to the parallel output of the shadow register 304 controlled by the task register 302. The selection can be performed in a plurality of other ways, and the selector 318 should be interpreted in a functional way, rather than structural. The selected parameter values are stored in a processing unit register 320 of the processing unit 306. For the sake of clarity, the data flow per se and data processing means are omitted. Apart from the features described above, data processing and data flow per se are similar to a conventional data link handler. Pig.4 is a flow chart illustrating a method of processing data blocks in a data link layer according to an embodiment of the present invention. The method comprises a shadow register programming step 400 and a plurality of processing steps 402. The shadow register progamining step comprises loading parameter values to the shadow register of a processing means. The values are loaded by a controller of the receiver, e.g. a DSP or a CPU. The parameter values are to be used by a processing unit of the processing means for processing data according to an actual TrCH. The plurality of processing steps 402 comprise a data block deinterleaving step 404, a data block rate matching step 406, and a data block decoding step 408. Fig.5 is a flow chart illustrating data block handling in a processing step according to an embodiment of the present invention. The data block handling comprises a data block reading step 500, a data block read indication step 502, a task register shifting step 504, a data block processing step 506, and a data ready-to-read indicating step 508. These steps are performed in each of the plurality of processing steps 402 in Fig. 4. The data block reading step 500 reads a data block, which is a result from a preceding processing step. Once this is done, an indication is given to acknowledge reading of the data block in the data-block read indication step 502. The task register is shifted in the task-register shifting step 504 to output a next TrCH to be processed. This also involves pointing out and collecting parameter values from the shadow register. It should be noted that steps 502 and 504 can be performed in the reverse order, i.e. the handshake is ready for a while and then the processing is started by the writing in the task register. The parameter values are then used in the data block processing step 506, where the data associated to the TrCH is processed. The processing can comprise deinterleaving, rate matching, or decoding. Once the data associated to the TrCH is processed, a signal is generated in the data ready-to-read indicating step 508 to indicate that a processed data block is to be read at an output so as to be further processed by a subsequent processing step. CLAIMS 1. A receiver in a digital communications system, comprising a data link handler comprising a deinterleaver, a rate matcher and at least one decoder, wherein said deinterleaver is arranged to apply deinterleaved data comprising a plurality of transport channels via a buffer to said rate matcher, and said rate matcher is arranged to convey rate matched data to said at least one decoder, characterized in that said deinterleaver, said rate matcher, and said one or more decoders each comprises a shadow register, a task register, and a handshaking means for managing data flow between them, wherein said shadow register is arranged to hold parameter values representing characteristics of the transport channels for data link layer processing, and wherein said task register is arranged to hold a list of transport channels to be processed. 2. A receiver according to claim 1, wherein said task register is arranged to shift said list according to a first in first out principle, where the output of said task register indicates the transport channel to be processed. 3. A receiver according to claim 1 or 2, wherein said handshaking means are arranged to signal an indication comprising information that a data block is ready for reading and that a data block is read. 4. A receiver according to any one of claims 1 to 3, wherein said deinterleaver, said rate matcher and said at least one decoder each further comprises a processing unit, wherein said processing unit is arranged to control shifting of said task register, selection from said shadow register, and signalling on said handshaking means. 5. A receiver according to claim 4, wherein said processing unit comprises a state machine, arranged to generate control signals for controlling said shifting of said task register, selection from said shadow register, and signalling on said handshaking means. 6. A method of processing transport channel data in a data link handler in a digital communications system, comprising the processing steps of: deinterleaving data comprising a plurality of transport channels; rate matching deinterleaved data; and decoding rate matched data, wherein each of said processing steps comprises the steps of: reading data; providing an indication that contains information that data is read; shifting a task register that contains a list of transport channels, wherein said task register comprises a list of transport channels to be processed; processing said data according to parameter values that represent characteristics of the transport channel in a shadow register indicated by an output of said task register; and providing an indication that contains information that processed data is to be read. 7. A method according to claim 6, wherein said step of shifting is a first in first out shift. 8. A method according to any one of claims 6 or 7, further comprising the step of programming said shadow registers with said parameter values. 9. A method according to any one of claims 6 to 8, wherein each processing step comprises the step of controlling said reading, indication providing, shifting, and processing steps by a state machine. Dated this 17 day of November 2006

Documents:

4266-CHENP-2006 FORM-1 12-08-2013.pdf

4266-CHENP-2006 FORM-3 12-08-2013.pdf

4266-CHENP-2006 FORM-5 12-08-2013.pdf

4266-CHENP-2006 AMENDED CLAIMS 12-08-2013.pdf

4266-CHENP-2006 AMENDED PAGES OF SPECIFICATION 12-08-2013.pdf

4266-CHENP-2006 OTHER PATENT DOCUMENT 12-08-2013.pdf

4266-CHENP-2006 POWER OF ATTORNEY 12-08-2013.pdf

4266-CHENP-2006 CORRESPONDENCE OTHERS 01-08-2013.pdf

4266-CHENP-2006 CORRESPONDENCE OTHERS.pdf

4266-CHENP-2006 ENGLISH TRNSLATION 01-08-2013.pdf

4266-CHENP-2006 EXAMINATION REPORT REPLY RECEIVED 12-08-2013.pdf

4266-CHENP-2006 FORM-1.pdf

4266-CHENP-2006 FORM-18.pdf

4266-CHENP-2006 FORM-6.pdf

4266-CHENP-2006 POWER OF ATTORNEY.pdf

4266-CHENP-2006 FORM-13 16-04-2007.pdf

4266-CHENP-2006 FORM-6 17-01-2008.pdf

4266-CHENP-2006 AMENDED CLAIMS 16-12-2013.pdf

4266-CHENP-2006 EXAMINATION REPORT REPLY RECIEVED 16-12-2013.pdf

4266-CHENP-2006 FORM-3 16-12-2013.pdf

4266-chenp-2006-abstract.pdf

4266-chenp-2006-claims.pdf

4266-chenp-2006-correspondnece-others.pdf

4266-chenp-2006-description(complete).pdf

4266-chenp-2006-drawings.pdf

4266-chenp-2006-form 1.pdf

4266-chenp-2006-form 26.pdf

4266-chenp-2006-form 3.pdf

4266-chenp-2006-form 5.pdf

4266-chenp-2006-pct.pdf