Title of Invention

"A SYSTEM FOR REDUCING SIGNAL DISTORTION IN A RECEIVER"

Abstract

A system for reducing signal distortion in a receiver, comprising channel matched filter 9 which generates a sequence of chips from a received signal; decision feedback equalizer DFE 16 which generates postcursor- inter-symbol interference (ISI) cancellation terms from a previously detected complementary code keying (CCK) chip sequence used to form a previous CCK codeword and cancels postcursor-ISI from the chip sequence to produce a chip metric; and a CCK correlation-decision block 92which generates a current CCK codeword based on the chip metric, wherein the DFE 16 generates precursor-ISI cancellation terms from a conjugate value of a chip value of a next symbol and cancels precursor-ISI from the previous CCK codeword based on a chip-time reversed estimate value of the current CCK codeword.

Full Text

BIDIRECTIONAL TURBO ISi CANCELLER-BASED DSSS RECEIVER FOR HIGH-SPEED WIRELESS LAN BACKGROUND OF THE INVENTION 1. Field of the Invention. The present invention generally relates to wireless communications, and more particularly to a direct-sequence spread-spectrum (DSSS) packet receiver that iteratively removes precursor inter-symbol interference (ISI) as well as postcursor ISI in wireless multipath channels by employing a bidirectional turbo ISI canceller. 2. Description of the Rejated Art. DSSS techniques have widely been applied to major wireless communications standards such as IS-95, CDMA 2000, W-CDMA, IEEE 802.11 wireless local area networks (WLAN) as well as others. These DSSS systems have in common transmitting information bits in fie form of wideband chip sequences, but they have noticeable differences in terms of embedded data modulation methods, i.e.,-from the most popular BPSK and QPSK to the higher-order QAM and the codeword selection modulations. The code complementary keying (CCK)-based DSSS system has recently been adopted as a 5.5Mbps/11Mbps rate 802.11b standard for higher speed extension of the original 1 Mbps/2 Mbps rate 802.11 WLAN. The 802.11 b DSSS/CCK is a codeword selection modulation based spread spectrum method which can transmit 4 or 8 information bits per symbol using an 8-long quaternary complementary codeword set of size 256. Because CCK codewords have good auto- and cross-correlation properties, a typical maximal ratio combining (MRC) RAKE receiver and codeword correlator bank can achieve satisfactory decoding performance in additive Gaussian or moderate multipath channels. However, as. tie multipath delay spread becomes larger than 100 ns, the simple RAKE-based correlator bank cannot sustain this performance any longer and thus it is necessary to complement the receiver with complex signal processing such as equalization of ISI or inter-chip interference (ICI). To perform MRC processing and equalization, the receiver needs to know accurate multipath channel coefficients. In a typical wireless LAN environment where the multipath channel changes very slowly and its profile is closely spaced, the channel coefficients are usually estimated in advance using a wideband preamble sequence part and the estimates are used to decode a data symbol part in the same packet. In this case, the MRC RAKE receiver can be implemented in the form of a channel matched filter (CMF) whose taps are the conjugate of the time-reversed channel estimates, and it is usually placed in front of the correlator bank in order to minimize the receiver implementation complexity by completing the muitipath combining before codeword correlation. The CMF not only provides a muitipath diversity advantage but also warrants robust time-tracking during the data symbol detection, as the signal has a symmetrical shape around a real-valued central peak after passing through the CMF. On the other hand, i! a decision feedback equalizer (DFE) is employed between the CMF and the codeword ^correlator bank to improve the detection performance, the associated DFE coefficients should also be estimated using the preamble part. In the case that only a feedback filter is employed that cancels a postcursor-ISI, the DFE coefficients can be directly calculated through a simple auto-correlation of the CMF coefficients. However, if a feedforward filter is incorporated to further improve performance by suppressing precursor-lSI, receiver complexity significantly increases because one or more of a complex matrix inversion, spectral factorization, or adaptive equalizer training must also be applied. A feedforward filter requires complex multiplication operations in data detection processing, while a feedback filter needs only addition operations. Thus, in practical highspeed WLAN packet transmissions, the DFE is usually composed of only a feedback filter without the capability of precursor-ISI suppression. When the muitipath delay spread becomes long, the remaining precursor-ISI critically affects the packet decoding performance. In view of the foregoing, a need exists for a practically feasible precursor-ISI cancellation system and method, and more particularly one which may be used in a variety of communications systems including but not limited to a DSSS packet receiver. SUMMARY OF THE INVENTION An object of the present invention is to provide a practically feasible precursor-ISI cancellation system and method which may be used in a variety of communications systems including but not limited to a DSSS packet receiver. Another object of the present invention is to provide an improved precursor-lS! cancellation system and method which is implemented in a DSSS/CCK communications system. Another object of the present invention is to provide an improved DSSS/CCK RAKE receiver which is robust in the muitipath channel, which robustness is achieved by incorporating a novel, iterative IS1 cancellation method and apparatus which cancels precursor-lSi interference and which is suitable for use in a system which performs DSSS/CCK communications. Another object of the present invention is to provide a DSSS/CCK receiver which performs at least precursor and preferably both precursor and postcursor ISI cancellation with reduced computational complexity and delay time. These and other objects and advantages are achieved by providing a bidirectional turbo ISI canceller (BT1C) which cancels precursor-ISI as well as postcursor-iSI without incorporating a multiplicative feedforward equalization filter. The iterative precursor-ISI and postcursor-lSI cancellation approach'has been applied to a simple BPSK modulation case and the M-ary pulse amplitude modulation case. However, the BT1C of the present invention takes an integrated approach of a time-reversed signal processing, a tentative decision based precursor cancellation, and an iterative (turbo) signal processing after tailoring them for DSSS/CCK codeword detection. To improve detection performance systematically, at least one embodiment of the present invention takes a three-step receiver design approach. The first step includes designing an optimal single-symbol RAKE receiver comprising a CMF, a codeword correlator bank, and an energy bias (E3) canceller under the assumption that no ISI is generated by preceding or trailing symbols. For a more realistic muitipath channel case, a second step incorporates a DFE for suppressing postcursor-ISI caused by a preceding symbol. Finally, a unique precursor ISI canceller is used to remove the remaining ISI caused by a trailing symbd. All three components may then integrated into a BTIC-based receiver applying turbo-iteration processing. In detecting each CCK symbol, a DFE and a codeword correlator bank is employed twice per iteration to cancel both the postcursor-IS! and the precursor-ISI. Because the DFE coefficients used in the precursor-ISI cancellation take the same coefficients as in the postcursor-ISI cancellation, no additional hardware or new coefficient caiculation is needed to realize the BT1C. As the performance improvement through the precursor-ISI cancellation becomes more and more significant as multipath delay spread increases, the BTIC is greatly useful to sustain the DSSS/CCK system performance in heavy-tailed muitipath channels. While a preferred embodiment contemplates applying the receiver design to a high-speed 802.11 b wireless LAN system to improve receiver decoding performance in multipath channel environments, other embodiments may be applied to a variety of DSSS communication systems with siight modification to improve decoding performance in static or slowly fading muitipaih channels. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1(a) and 1(b) are diagrams respectively showing preferred embodiments of a transmitter and receiver in accordance with the present invention which, for example, may be used for DSSS/CCK communications in an IEEE 802.11b wireless LAN application. Fig. 2 is a diagram showing a DSSS/CCK data packet structure including a preamble, header, and paytead for use in a wireless LAN application. Fig. 3 is a flow chart showing steps which may be used to perform filter coefficient estimation in accordance with one embodiment of the present invention, Fig. 4 is a flow chart showing steps which may be used to perform a CCK correlation-decision block:operation in accordance with one embodiment of the present invention. Fig. 5 is a diagram showing an internal structure and associated operation of one type of decision feedback equalizer (DFE) which may be used to cancel pcstcursor-ISI arising in multipath channels of a DSSS/CCK receiver in accordance with the present invention. Fig, 6 is a flow chart showing steps which, may be performed by the DFE of Fig. 5 to cancel postcursor-ISI and to perform current CCK codeword estimation. Fig. 7 is a diagram showing a structure and associated operation of one type of chip-time reversed decision feedback equalizer for a DSSS/CCK receiver that cancels precursor-ISI arsing in miiltipath channels in accordance with the present invention, which equalizer may be the same DFE shown in Fig. 5 in accordance with a preferred embodiment Fig. 8 is a flow chart showing steps which the DFE of Fig. 7 performs to cancel precursor-ISI and to perform previous CCK codeword estimation. Fig. 9 is a diagram of a bidirectional turbo ISI canceller-based DSSS/CCK receiver that cancels both the postcursor-ISI and the precursor-ISI in accordance with one embodiment of the present invention, where the postcursor and precursor IS! is estimated and cancelled more accurately by .iterative (or, turbo) processing. Fig. 10 is a flow chart showing steps which the bidirectional turbo ISI canceller of Fig. 9 performs based on estimates of current and previous CCK codewords. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figs. 1(a) and 1(b) are block diagrams of a DSSS/CCK communication system which, for example, may be employed in an IEEE 802.1 1b wireless LAN. As shown in Fig. 1(a), source bits in a data packet are first scrambled by a scrambler 1 and grouped into the Mh 8-bit block 2 (b(k)= {kjfy, bi(*),...Jb7(Jr)}) at time k(k = 0,1 ..... K-1). Then, the first bit pair (Jbo(/(), b\(k)) is mapped to a differentially encoded phase angle ^(fc) based on a DQPSK encoder 3i and the other bit pairs (b$), b3(k)), (b4(k), bsf/cjj, and (b6(k), b7(k)) are respectively mapped to $,(£), 03(fc)5 and ^4 based on a natural QPSK encoding in encoders 82, 3s, and 34. Note, that each of the four angles can take a value in the set of {0, n 12, 7r,3/T/2}. Among the four angles, the naturally encoded angles 0,(fc),^3,-and 04 are used to generate one of 64 base CCK codewords c(/cj = (co(/c), ci(fr), ..., cj(k)) in selector 4 according to the following equation: The differentially encoded angle fa(k)\s used by phase modulator 5 to modulate the envelop of the resulting base CCK codeword which ultimately determines one of 256 complete CCK codewords: The transmitted codewordsjre convolved 6 with a multipath fading channel 7 (h = (, 0,0,0, A(0),A(l),—,A(i-l),0,0,0,—)) and corrupted by additive white Gaussian background noise in adder 8. As shown in Fig. 1(b), the CCK receiver receives the signal and in effect provides deformed signal samples as follows: rC/) = Z E «,(^a-t-8fc) + »C/), 1 = 0,1,2,... (3) t=0 i-O at the receiver front-end, where "^ is a zero-mean circularly-symmetric complex white Guassian noice process of variance °. We assume that the multipath channel coefficients take exponentially decaying complex Gaussian random variables according to the IEEE 802.11b channel model. Moreover, we assume a quasi-static fading channel in the description of the invention, where the channel coefficients are fixed for each packet transmission and change independently in every packet. The received signal is first convolved with the channel matched filter (CMF) 9, which corresponds to the conjugate of the time-reversed multipath channel impulse response h=(h*(L-ty,h*(L-2),---h*(Qy) y'e'd'n9 8 soft chip values in every CCK symbol interval. The CMF coefficients are estimated in advance using the preamble part of each packet. As shown in Fig. 2, in a typical WLAN packet transmission the data packet is formed by juxtaposition of preamble, header, and payload parts, where the preamble part is a known or easily detected sequence transmitted to help the receiver perform packet detection, carrier and timing synchronization, channel estimation, as well as to perform other functions. Returning to Fig. 1(b), CCK codeword correlator 10 correlates the soft chips with 64 possible base CCK codewords to yield 64 complex soft metrics, each of which is rotated by four possible angles in rotators 11 to resolve the uncertainty of An optimal DSSS/CCK detector design procedure using the received signal sample sequence rfj) in Equation (3) will now be described in accordance with one embodiment of the present invention. In this description, N denotes the number of chips in a CCK symbol. For illustrative purposes, the case where N = 8 is specifically discussed, however those skilled in the art can appreciate that N may be another number if desired. Because the multipath delay spread in typical wireless LAN environments is longer than the UUK cnip period Tc and shorter than the entire CCK symbol period NTe, it can be assumed, in designing the CCK detector, that the kth CCK symbol is in effect determined by the received samples of only three symbols, e.g., the (/c-1)th, the ton, and the (/f+1)th ones. Therefore, Equation (3) may be rewritten into a truncated sample sequence of length 4N-1 when the kth symbol detection is concerned. Note that h(i)» 0 when i N, under the above assumption. Though the maximum channel length to the CCK symbol length may be restricted in this section to facilitate description of the receiver design, the design procedure can be extended to longer channel cases in a straightforward manner. A. Optimal Single-Symbol Detector As a first step in the detector design, /a/f/f -1)} and {ai(k + 1)} may be temporarily set to all-zero chip sequences, which means no postcursor-ISI nor precursor-ISI is involved in the detection processing. Note that this assumption warrants an ISI-free condition between neighboring symbols, but the 1C! between the chips in a CCK symbol may still causes a performance degradation. Then, at time Jc the maximum likelihood (ML) single-symbol detector selects the m-th (m 0,1, 255) hypothetical symbol aM that maximizes the logarithmic likelihood probability: which is equivalent to nlm] &(al"],a[™],---,al£l}) that maximizes where 5R{^},3{^4}, and A* respectively denote the real part, the imaginary part, and the conjugate of a complex number A. Now noting that /?(/) is zero when i N , we can determine how to implement the optical canonical detector when no precursor-lSI or postcursor-ISI exists. For the correlation part (i.e., the first term of Equation (6)), the received chip sample sequence {r(k)(kN + j}} is convolved with the CMF h , and then the consecutive N CMF output samples are correlated with the conjugates of 256 codewords. On the other hand, for the EB cancellation part (i.e., the second term of Equation (6)), a look-up table composed of 64 entries may be used, where each entry can be calculated and stored during the preamble reception period when estimation of the CMF coefficients is completed. Note that the phase uncertainty of ^(£) does not affect the energy bias term in Equation (6). Also note that the E3 cancellation need not be considered in fiat fading or AWGN channels as the energy of all CCK symbols is equal if a frequency-selective signal distortion does not occur during the transmission. However, in typical frequency-selective multipath wireless channels, the 1CI components cause each codeword to have different signal energy at the receiver front-end , and thus the E3 cancellation is essential for optimal detection. The computational cost of the E3 bok-up table construction can be significantly reduced by further manipulating the second term of Equation (6). By expanding and manipulating the second term EB(m),m = 0,l---,63, we can get _ respectively represent the aperiodic correlation coefficients of the multipath channel and the mth codeword. The second term in Equation (7) may be neglected, aspa(m;0) takes the same value for all CCK codewords. (Without loss of generality, the four different codewords generated by the multiplication of four ^ values and the mth base CCK codeword (m = 0,l,---,63) are denoted by aM, zim**\ at"7*128', and ai"1*192!.) Therefore, in order to realize the E3 cancellation, 64(N-1) CCK codeword coefficients pa(m\i), m = 0,1,• • • ,63, i = i,2.• • • ,N -1 are preferably stored in advance and then (AM) channel coefficients ph(i),i = 1.2,---,N-l are calculated and 64 EB values EB(m), m = 0,1,—,63 are obtained according to the above equations when the CMF estimation is completed during the preamble reception. In Fig. 1(b), a concatenated structure of the CMF and the CCK correlation-decision block incorporating the EB canceller is depicted, which determines the transmitted codeword based on the optimal signal-symbol processing of Eq. (6). If desired, the EB canceller may be omitted for simple implementation at the cost of a small degradation of decoding performance. For the implementation of the receiver depicted in Fig. 1(b), we need to estimate three sets of coefficients, i.e., CMF coefficients, DFE coefficients, and E3 coefficients. Fig. 3 describes the procedure to estimate these coefficients. First, when the receiver detects the arrival of a packet preamble by using energy measurement or other methods (Block 30), the receiver correlates the known preamble code with the incoming received signal (Block 31). By accumulating the correlation results for each chip time (or half-chip time) offset over multiple preamble symbols, the CMF coefficients {/?(/)} can be determined and output. (Blocks 32 and 33). The DFE coefficients {/^(i)} are then calculated via the aperiodic correlation of the CMF coefficients as is formulated in Equation (8). The DFE coefficients may also be measured for each chip time (of half-chip time) offset by correlating the incoming receive signal with the estimated CMF coefficients over multiple preamble symbols. (Block 34). Finally, the EB coefficients are calculated by applying the inner-product between the DFE coefficients {jj,,(0} 35 and the CCK codeword correlation coefficients [pa(m;i)} as is formulated in Equation 7 (Blocks 36 and 37), where [pa(m:i)} is calculated in advance via the aperiodic correlation of the /nth CCK codeword {a{m]} in Equation 9 (Blocks 38 and 39). Fig. 4 describes the operation of the correlation-decision block embedded in the receiver in Fig. 1(b). First, the 8-long input sample sequence corresponding to the noisy chips of a CCK symbol is stored as the soft estimate of the received CCK codeword. (Block 40). Then, the input sample sequence is correlated (inner-producted) with each of 256 CCK codewords (Block 41) and, optionally, the energy bias terms for each CCK codewords are subtracted from the corresponding correlation results (Block 42). Then the CCK codeword yielding the largest output value is selected as the hard estimate of the received CCK codeword. (Blocks 43 and 44). The 256 correlations and the maximum selection processing may be implemented in an efficient form by grouping them into 64 sets of 4 elements which have the same base CCK codeword: First, 64 correlations between the input sample and 64 base CCK codewords are performed, each correlation results are multiplied by 4 possible values of the envelop symbol, and real parts of the multiplication results are taken. The maximum of the 4 real parts in each group is selected as the survivor of the group and the corresponding energy bias is subtracted. Finally, the 64 survivors are compared and .the CCK codeword producing the maximum survivor value is selected as the hard estimate of the received CCK codeword. 6. Incorporation of Postcursor-ISI Canceller The optimal single-symbol detector described in the previous section is not optimal any longer in practical multiple-symbol transmission applications, as the ISI components between neighboring symbols have not been considered in designing the detector. Both the postcursor-lSI caused by the previous symbol and the precursor-ISI caused by the orthcoming symbol degrade system performance. The postcursor- ISI cancellation is first addressed in this section by modifying the previous ISl-free assumption, such that only the forthcoming symbol { mitigation method of the precursor-ISI, which is more difficult to resolve in the context of DSSS/CCK communications and which is a key proposal of the present invention, will be separately discussed in the next section. In order to quantify the non-zero postcursor-IS! associated component resulting from the detection processing in Equation (6), the first term of Equation (6) is expanded by replacing r(k}(kN+j") with Equation (4), where the current symbol {a,(k)}, the forthcoming symbol {a,(ki-1}}, and the additive noise n(/) are set to all-zero sequences. Then, the expansion result is represented by: for the channel correlation coefficients (ph(n)} defined in Equation (8). In the above equation, we observe that the postcursor-ISI can be perfectly cancelled in front of the CCK correlator by employing a feedback filter and a previously detected CCK chip sequence {aX/c-1)}. Fig. 1(b) shows the DFE that subtracts a corresponding postcursor-ISI term: -i Xv-H-fl(*-l)P;,("), i =0,1,..., N-2, i+i U') [0, i = N~l from each soft chip value y$) to provide the CCK correlator with an improved (or, postcursor-ISI cancelled) chip metric: *,(*) = :x,(*)-«r(*). t = 0,1,- ,N (12) Fig. 5 illustrates the internal structure and operation of the DFE. When the (Jc-1)th symbol decision is completed, the last AM chips (§N.i(Jc-1), aw^/c-l),---, ai(/c-1) are used to initialize the AM storages of the DFE whose coefficients are set to (ph(l'),p,t(2),--',ph(N-l'). Then, the stored chips are shifted N times (i = 0,l,---,JV-l) from left to right at every chip clock, outputting the corresponding postcursor-ISI ofos'(k) to be subtracted from the input soft chip value y/(lc). The refined soft metrics resulting from the subtraction z,(Ar),i = 0,1,---,JV-1, are used to determine the Wh symbol decision. Fig. 6 summarizes the procedure of the postcursor-ISI cancellation and current CCK codeword estimation. At the beginning, the chip time index / is set to 0 (Block 30) and the hard estimate of the previous CCK codeword is loaded to the DFE in Fig. 3 (Block 61). (For the hard and soft estimates of a CCK codeword, refer to Fig. 4.) The current output of the DFE is then subtracted from the /th input sample, which corresponds to the fth noisy CMF output value (Block 62), and the result is stored as the /th input sample of the correlation-decision block (Block 63). Next, the DFE is shifted by one sample and 0 is fed as the new input sample of the DFE. (Block 64). The chip time index / is incremented by 1 (Block 65), and if / is smaller than 8 the process returns to 62 (Block 66). Otherwise, soft and hard estimates of the current CCK codeword are determined via the correlation-decision block operation described in Fig. 4 and the operation is finished. (Block 67). C. Time-Reversed Precursor-ISI Cancellation As a next step of the optimal detector design of the present invention, the precursor-free assumption of the previous sections is removed and all the symbols {a/f/w)}, fa/(kj}, and {a/(/c + 1)} are set to be nonzero chip sequences. Because a reliable estimate of the precursor-ISI is not available when the current symbol is to be determined, hypothetical detection methods that rank the decision statistics associated with all possible forthcoming symbols {a\ml (k +1) :m = $,!,••-,256} could be applied for optimal detection. However, the hypothetical detection methods request 65,536 (or, 256 x 256) decision statistics, making them practically infeasible in the CCK codeword detection. As an alternative, a sub-optimal precursor filtering that suppresses the precursor-ISI may be employed between the CMF and the CCK correlator. However, the introduction of the precursor filtering devastates the optimal CCK single-symbol detection scheme that necessitates a concatenation of the CMF, the CCK correlator, and the EB canceller. Furthermore, the precursor filtering often causes noise enhancement without an extremely complex spectral factorization or a coefficient adaptation approach, and degrades time-tracking performance by deforming the symmetric CMF output sample sequence. Therefore, the traditional precursor-ISI mitigation approaches are not applicable to the DSSS/CCK-based packet communication systems, and we demand a new method that can efficiently cancel the precursor-ISI without affecting the structure of the optimal CCK single-symbol detector. In order to devise a precursor cancellation scheme, the present invention quantifies the precursor-ISI; generated during the /cth symbol detection in the similar way as was done in the last section. By expanding the first term of Eq. (6) under the assumption that both (a/(/c-/)} and { a/(fr)} are all-zero chip sequences and no AWGN is added in the channel, we obtain the preeursor-ISI associated component: V «(13) Now, by carefully comparing Eq. (13) with Eq. (10), we find out that the precursor-ISI and the postcursor-ISI have symmetric relations each other, and thus the precursor-ISI can also be cancelled by tie same DFE that was employed for postcursor-ISI cancellation. More specifically, if we load the postcursor-ISI DFE with the conjugates of the chips of the re symbol and take a time-reversed sequence processing, precursor ISI cancellation 12 instead of postcursor ISI cancellation may be realized in accordance with the present invention. Fig. 7 illustrates the associated DFE structure and the detailed processing, where the symbol time and chip time progress in the order of and [JV-1 •••,; + l,z,z-l)---,0], respectively. When the (/c+1)th symbol detection is completed, the conjugates of the AM chips of the determined symbol (ao(/c+1)*, ai(/f+1)*), ...aN-2(lf+1)*) are used to initialize the AM storages of the DFE whose coefficients are set to (p,1(l),p/l(2),---)pA(JV-l)). Then, the stored chips are shifted A/ times (i = N-l,N-2,---,Q) from left to right at every chip clock and the conjugate of the corresponding output is taken as the precursor-ISI term: which is subtracted from the input soft chip value y/(/c). The refined soft metrics resulting from the subtraction w((K),i = N-l,N-2,---,Q are time-reversed and fed to the CCK correlator to determine the Irth symbol decision. While the EB cancellation and the postcursor-lSI cancellation have been tried in the legacy WLAN systems, it is unique in this invention to incorporate the precursor-ISI cancellation in the context of the DSSS/CCK wireless communications. Fig. 8 summarizes fie procedure of the precursor-ISI cancellation and previous CCK codeword estimation. At the beginning, the chip time index / is set to a predetermined value such as 8 (Block 80) and the conjugate of the hard estimate of the current CCK codeword is loaded to the DFE in Fig. 7 (Block 81). (For the hard and soft estimates of a CCK codeword, refer to Fig. 4.) Next, the chip time index /is decremented by 1. (Block 82). Then, the conjugate of the current output of the DFE is subtracted from the ith input sample, which corresponds to the ith noisy chip of the soft estimate of the previous CCK codeword (Block 83), and the result is stored as the ith input sample of the correlation-decision block (Block 84). Continuing, the DFE is shifted by one sample and 0 is fed as the new input sample of the DFE. (Block 85). If / is greater than 0, the process returns to Block 82. (Block 86). Otherwise, the refined soft and hard estimates of the previous CCK codeword are determined via correlation-decision block operation described in Fig. 4 and the process is finished. (Block 87). In this procedure, note that the chip time reversal of the 8-long input sample sequence is needed before the correlation-decision block operation. D. Bidirectional Turbo ISI Canceller Up to now we have investigated all the component blocks needed to construct an optimal DSSS/CCK detector in accordance with the present invention, namely the optimal single-symbol detector with E3 canceller, the postcursor-ISI canceller, and the time-reversed precursor-ISI canceller. The manner in which an entire system can be synthesized to effectively utilize all the component blocks will now be discussed. In synthesizing these components, an integration solution is found using a tentative-decision based precursor ISI cancellation approach and iterative (or turbo) signal processing. Fig. 9 is a block diagram of a BTIC-based DSSS/CCK detector. At time k, the postcursor-ISI values (of (jfc), of (*),-•• ,u£J(Jt)) in Equation (11) are generated by the postcursor-ISI DFE 90 and subtracted from the A/ soft chips in the CMF output (Jo (£). 7i (£)»•••. 7 J\M(&)) 'n subtracter 91 to yield the soft metrics (z^k^z^k^-^zy^kyy. (Refer to Fig. 5.) The soft metrics are fed to the CCK correlation-decision block 92 in Fig. 1(b), which tentatively determines the Wh CCK codeword (§o(/f), ai(/c),--v §N-I(/C)) 83. Then, the conjugates of the tentative codeword chips are stored in the precursor-ISI values of the (/c-1)th CCK symbol (o£i (k - 1), u£" (k - 1), • • • , of (k - 1)) . (Refer to Fig. 7.) Finally, the precursor-ISI values are subtracted in subtracter 95 from the time-reversed soft metrics that were stored at time /f-1, z1f_l(k-l\z:]f_2(k-iy,--,z0(k-\y), to yield the time-reversed sequence of the refined soft metrics: Next, the metric sequence (uN_l(k-l),uN,2(k-l\---,u0(k-iy) is time- reversed in Block 96 and fed to the CCK correlation-decision block once again to produce the (Jr-1)th refined CCK codeword (ao{/c-1}, ai(/c-1), ••-, M/r-1)). Note that the refined soft metric sequence is free from the precursor-ISI as well as the postcursor-ISI at the cost of one symbol-time delay unless the tentative decision is erroneous. (Refer to Equation (12) and Equation (15).) In order to improve detection performance, we can iterate the entire processing at each symbol detection-time by reloading the postcursor-!S! DFE with the refined CCK codeword chips and restarting the postcursor-ISl cancellation and then the precursor-lSI cancellation. After completing the pre-determined number of iterations at time k, the final sequences of the soft metrics (zt)(k\zl(k),---,zff_l(k)') and the tentative-decision codeword chips (ao(/c), ai(A),---s; aw-i(k)) are stored in the memory for use at time k + 1. The entire turbo processing is continued until ail the payioad CCK symbols are decoded. Rg. 10 summarizes the operation of the BTIC between the estimates of the current and previous CCK codewords. At the beginning, 8 noisy chips corresponding to the current CCK codeword are obtained via the correlation between the received payioad signal and the CMF. (Block 100). The postGursor-ISI is canceled from the noisy chip sequence via the procedure in Rg. 6 using the DFE output of the hard estimate of the previous CCK codeword. (Block 110).Jhe results are stored as the hard and soft estimates of the current CCK codeword, which are ideally postcursor-!SI free. (Block 120). The precursor-IS I is canceled from the soft estimate of the previous CCK codeword via the procedure in Fig. 8 using the DFE output of the chip-time reversed hard estimate of the current CCK codeword which was obtained in 120. (Blocks 130,140,150). The results are stored as the refined hard and soft estimates of the previous CCK codeword, which are ideally both postcursor-iSI free and precursor-lSI free. (Block 160). If the number of iterations is equal to a predetermined value (Block 170), a final decision of the previous CCK codeword is made by taking the hard estimate of the previous CCK codeword obtained in Blocks 120-160. (Block 180). The hard and soft, estimates of the previous codeword are then set to the current CCK codeword. (Block 185). Otherwise, the hard estimate of the previous CCK codeword is updated with the refined one (Block 190) and the process continues to Block 200. Finally, the CCK symbol time index k is incremented by 1, and the hard and soft estimates of the previous CCK codeword are set to those of the current CCK codeword, which is a preliminary step for the next CCK codeword decision. Other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention. WE CLAIM: 1. A system for reducing signal distortion in a receiver, comprising: channel matched filter (9) which generates a sequence of chips from a received signal; decision feedback equalizer DFE 16 which generates postcursor-inter-symbol interference (ISI) cancellation terms from a previously detected complementary code keying (CCK) chip sequence used to form a previous CCK codeword and cancels postcursor-ISI from the chip sequence to produce a chip metric; and a CCK correlation-decision block (92) which generates a current CCK codeword based on the chip metric, wherein the DFE (16) generates precursor-ISI cancellation terms from a conjugate value of a chip value of a next symbol and cancels precursor-ISI from the previous CCK codeword based on a chip-time reversed estimate value of the current CCK codeword. 2. The system as claimed in claim 1, wherein the DFE 16 cancels postcursor-ISI by generating postcursor-ISI correction terms from a previously detected CCK chip sequence used to form the previous CCK codeword and subtracting the postcurstor-ISI correction terms from the chip sequence to produce the chip metric. 3. The system as claimed in claim 1, wherein the DFE (16) cancels postcursor-ISI by setting DFE coefficients based on a previously detected CCK chip sequence, generating postcursor-ISI terms by shifting the DFE coefficients a predetermined number of times per chip clock, and subtracting the postcursor-ISI terms from the chip sequence to produce the chip metric. 4. The system as claimed in claim 1, wherein the DFE (16) cancels the precursor-ISI by computing conjugates of chip values of a future symbol, setting DFE coefficients based on the conjugates, generating precursor-ISI terms by shifting the DFE coefficients a predetermined number of times per chip clock, and subtracting the precursor-ISI terms from chip metrics corresponding to the previous CCK codeword. 5. The system as claimed in claim 1, wherein the receiver is a direct sequence spread spectrum/complementary code keying (DSSS/CCK) wireless communications receiver. 6. The system as claimed in claim 1, comprising: an energy bias canceler which equalizes signal energy in the codeword correlator bank. 7. The system as claimed in claim 1 comprising a bidirectional turbo ISI canceler, having: a single-symbol detector which generates the sequence of chips; a postcursor-ISI canceler (90) to generate the postcursor-ISI cancellation terms from a previously detected chip sequence used to form the previous CCK codeword and to cancel postcursor-ISI from the chip sequence to produce the chip metric; and a precursor-ISI canceler (94) to generate the precursor-ISI cancellation terms based on a chip-time reversed estimate of the current CCK codeword generated from the chip metric to cancel the precursor-ISI from the previous CCK codeword. 8. The system as claimed in claim 1 wherein the single-symbol detector has a RAKE receiver. 9. The system as claimed in claim 8, comprising: a codeword correlator bank which generates the current CCK codeword from the chip metric. 10. The system as claimed in claim 9, wherein the single-symbol detector has an energy bias canceler to equalize signal energy in the codeword correlator bank.

Documents:

2196-DELNP-2005-Abstract-(09-02-2009).pdf

2196-DELNP-2005-Abstract-(31-07-2009).pdf

2196-delnp-2005-abstract.pdf

2196-DELNP-2005-Claims-(06-02-2009).pdf

2196-DELNP-2005-Claims-(09-02-2009).pdf

2196-DELNP-2005-Claims-(30-01-2009).pdf

2196-DELNP-2005-Claims-(31-07-2009).pdf

2196-delnp-2005-claims.pdf

2196-DELNP-2005-Correspondence-Others-(04-02-2009).pdf

2196-DELNP-2005-Correspondence-Others-(06-02-2009).pdf

2196-DELNP-2005-Correspondence-Others-(09-02-2009).pdf

2196-delnp-2005-Correspondence-Others-(11-08-2009).pdf

2196-DELNP-2005-Correspondence-Others-(27-01-2009).pdf

2196-DELNP-2005-Correspondence-Others-(30-01-2009).pdf

2196-DELNP-2005-Correspondence-Others-(30-07-2009).pdf

2196-DELNP-2005-Correspondence-Others-(31-07-2009).pdf

2196-delnp-2005-correspondence-others.pdf

2196-delnp-2005-description (complete).pdf

2196-DELNP-2005-Drawings-(04-02-2009).pdf

2196-DELNP-2005-Drawings-(30-07-2009).pdf

2196-delnp-2005-drawings.pdf

2196-DELNP-2005-Form-1-(09-02-2009).pdf

2196-delnp-2005-form-1.pdf

2196-delnp-2005-form-13-(11-08-2009).pdf

2196-delnp-2005-form-13.pdf

2196-delnp-2005-form-18.pdf

2196-DELNP-2005-Form-2-(09-02-2009).pdf

2196-delnp-2005-form-2.pdf

2196-DELNP-2005-Form-3-(04-02-2009).pdf

2196-DELNP-2005-Form-3-(31-07-2009).pdf

2196-delnp-2005-form-3.pdf

2196-delnp-2005-form-5.pdf

2196-DELNP-2005-GPA-(09-02-2009).pdf

2196-DELNP-2005-GPA-(30-01-2009).pdf

2196-delnp-2005-pct-101.pdf

2196-delnp-2005-pct-105.pdf

2196-delnp-2005-pct-110.pdf

2196-delnp-2005-pct-111.pdf

2196-delnp-2005-pct-210.pdf

2196-delnp-2005-pct-304.pdf

2196-delnp-2005-pct-318.pdf

2196-DELNP-2005-Petition-137-(06-02-2009).pdf