Title of Invention

A METHOD OF PRODUCING SILICON POWER SEMICONDUCTOR THYRISTORS WITH NARROW REVERSE RECOVERY PARAMETERS

Abstract The present invention relates to provides a method of controlling reverse recovery parameters of silicon power semiconductor thyristors through a two-step method comprising an initial coarse-correction using gold diffusion at wafer-processing stage followed by exposure of fully fabricated chips to gamma rays for fine tuning. As the second step of irradiation reversible and incremental dosages suffice. The above helps in lowering the manufacturing cycle time. This is proven to be a versatile method especially to meet stringent custom-specific requirements and has been adapted for industrial manufacturing.
Full Text


FIELD OF INVENTION
The present invention relates to a method of fine-tuning reverse recovery
parameters of silicon power semiconductor thyristors to improve manufacturing
yield and cycle time during industrial manufacturing.
BACKGROUND OF INVENTION
Reverse recovery parameters of semiconductor devices such as diodes and
thyristors depend strongly on the rate of recombination of electrons and holes.
During switching from ON to OFF state, a finite time known as reverse recovery
time [tRR] elapses before carriers recombine and are completely depleted from
the base layer of semiconductor device. The charge and current during this
period are termed as reverse recovery charge [QRR] and reverse recovery current
[IRR] respectively. These recovery parameters are important especially in circuits
where the devices are series connected as an stack. The series connection
demands that the thyristors are within a narrow band with both upper and lower
specification limits so as to enable them switch-off concurrently and share the
stack voltage equally. Unequal sharing results in reverse voltage in excess of the
rated values when the thyristors become electrically damaged.


Generally, two alternative approaches are employed for control of minority
carrier lifetime. One method uses diffusion of heavy metal atoms such as gold or
platinum into silicon [1-3]. These create energy levels within band gap, which act
as recombination centers that determine the reverse recovery charge and
current. The carrier lifetime can be controlled by the concentration of gold
solution, process temperature and rate of cooling.
The other method creates recombination centers through lattice damages arising
out of exposure to high-energy beam of neutron; portion electron or gamma
particles [3,4]. The carrier lifetime,..in this case, is determined by the energy and
dosage of radiation.
Heavy metal diffusion using gold or platinum is essentially a high-temperature
process (800-900 °C) that is carried out on silicon wafer during wafer processing
stage. Thereafter, the wafer is processed through a series of relatively lower
temperature process such as deposition of electrode layers, application of
silicone-rubber, etc. to complete the chip fabrication. Hence, reprocessing
through metal diffusion for any further tuning of recovery parameters is not
possible, once the chip is fabricated and measured. Also the effect cannot be
reversed by any other means. These limitations hamper realization of recovery
parameters in a close band and with a reasonable manufacturing yield.


OBJECTS OF INVENTION
An object of present invention is to propose a method of fine-tuning the recovery
parameters of fully fabricated chips, which eliminates the limitations of prior art
method of single-step heavy metal diffusion.
Another object of present invention is to propose a method of fine-tuning the
recovery parameters of fully fabricated chips, which meets the narrow band
specifications of reverse recovery parameters.
A further object of present invention is to propose a method of fine-tuning the
recovery parameters of fully fabricated chips, which is easily adaptable to an
industrial manufacturing process.
SUMMARY OF INVENTION
Accordingly, there is provided a method of producing silicon power
semiconductor thyristors with narrow reverse recovery parameters, the method
comprising the steps of: (a) forming a convention p+ -n-p-n-n+ thyristors
structure by diffusing silicon wafers with impurities; (b) subjecting the diffused
wafers to a gold diffusion process; (c) joining the wafers to molybdenum plates
by adapting an eutectic alloying process followed by beveling and passivation of
p-n junctions terminating at the cylindrical edge; (d) subjecting the fully
fabricated chips produced by step (c), to a plurality of electrical measurements
that include forward voltage drop, and reverse recovery parameters, the forward
conduction and reverse recovery parameters having an opposed relationship,


thereby restricting the recovery parameters to a narrow band; (e) exposing the
gold-diffused thyristors chips produced by step (c) to gamma rays for a duration
that establishes a prescribed dose of gamma rays at calculated dose rate; and
(f) subjecting the gamma-irradiated thyristor chips produced under step step
(e) to a stabilization-annealing process in which the chips being annealed
for about 12.00 hours at a temperature around 200°C to ensure stabilizing
of the lattice damages, wherein the gold diffusion process is carried-out at
a temperature of 800-830°C and soak time of 2-3 hrs followed by cooling
to room temperature.
The invention discloses a two-step method to employ gold diffusion as an initial
coarse-correction process at wafer processing stage followed by a step of
exposing the chips to gamma rays. The gamma ray is administered based on


coarsely adjusted values of recovery parameters for fine-tuning. In case of
inadequate correction, gamma irradiation is repeated in incremental steps. A
suitable annealing process is employed to partially or totally reverse excessive
radiation damages. The present invention aims at improving manufacturing yield
and cycle-time in an industrial environment.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Fig. 1 Schematic diagram of reverse recovery characteristics of thyristor showing
parameters VT, QRR, IRR, tRR and tq.
Fig. 2 Histograms of reverse recovery charge [QRR] as obtained using gold
diffusion and as shifted by gamma irradiation. QRR measured at ITRM=500A,
di/dt=-0.5A/µs, Tj=90°C; Specification:0.6-0.9 mC.
Fig. 3 Trade-off curve - Forward voltage drop [VT] versus reverse recovery
charge [QRR] for a 3200V/1000A phase control thyristor used in High Voltage
Direct Current (HVDC) power stations. QRR measured at ITRM=500A, di/dt=-
0.5A/µs, Tj=90°C; Specification:0.6-0.9 mC.


VT measured at IT=1200A, Tj=25 °C. Specification Fig. 4 Histograms of reverse recovery current [IRR] as obtained using gold
diffusion and as shifted by gamma irradiation. IRR measured at ITRM=1000A,
di/dt=-1.5A/µs, Tj=120°C; Specification: 34-42 A.
Table-1 Incremental correction of reverse recovery charge [QRR] using repeated
gamma-irradiation steps. QRR measured at ITRM=500A, di/dt=-0.5A/us, Tj=90°C.
Table-2 Reversal of gamma irradiation effect by annealing. QRR measured at
ITRM=650A, di/dt=-5A/us, Tj=12u°C.
DETAILED DESCRIPTION OF THE INVENTION
Chip fabrication with single-step gold diffusion:
Silicon wafers (Float zone, n-type, ϕ54-mm) of 140 Ohm-cm resistivity and 800-
microns thick are diffused with p-type (Aluminium, Boron) and n-type
(Phosphorus) impurities to form a conventional p+-n-p-n-n+ thyristor structure.


The diffused wafers are subjected to gold diffusion process carried out at a
temperature range of 800-830 °C and soak time of 2 to 3 hours followed by
cooling to room temperature. Gold tetrachloride solution is used as dopant
source.
The wafers are joined to 1.5 to 2.5 mm thick molybdenum by means of a
eutectic alloying process. Aluminium (20-microns thick) and silver (2-microns
thick) layers are deposited using physical vapour deposition to form anode,
cathode and gate electrode. P-n junctions terminating at the cylindrical edge are
beveled and passivated to complete chip fabrication.
The fully fabricated chips are subjected to various electrical measurements that
include forward voltage drop (VT) and reverse recovery parameters QRR, IRR, trr
and tq. These forward and reverse parameters have trade-off relationship with
one-another. The recovery parameters need to be brought to a narrow custom-
specified band. The forward voltage drop increases as the correction is applied to
decrease the recovery parameters. The process control becomes a critical
exercise, as the drop has an upper specification limit.
Limitations of gold diffusions as a single-step control process:
Non-conforming parameters cannot be corrected at this stage through re-


diffusion of gold since wafers are now fully fabricated into chips. Also, the partial
or complete reversal of gold recombination centers is not possible. These
limitations of gold diffusion demand stringent process control measures to
achieve minimum non-conformities.
Gamma irradiation as secondary control process:
After realizing the coarsely corrected values of the recovery parameters using
gold diffusion, the secondary fine-correction is achieved by using gamma
irradiation process to further lower and bring the values within the acceptable
limits.
Gold-diffused thyristor chips are exposed to gamma rays using BARC-make
GC900 gamma chamber that uses 60Co isotope (half-life = 5.2714 years) as
radioactive source. The dose administered is in terms of Mega-rads and is based
on correlation data pre-constructed for a given type of semiconductor chip. Dose
rate as applicable for the source at the date and time of irradiation is computed
in Mega-rads/hour using the decay rate and original radioactivity (in Curies). The
chips are exposed for a duration (hours) that establishes the prescribed dose at
the calculated dose rate. Gamma irradiation is relatively inexpensive and dosage
accurately controllable.
Gamma chamber uses Cobalt isotope as radioactive source having certain half
life. Using decay rate and original radioactivity for Cobalt isotope, chips are
exposed to radiation. With different experimental settings and test results, we
establish the dose rate.


Stablilization-annealing process:
The gamma irradiated thyristor chips are annealed for duration of 12 hours at
200 °C which is well above the maximum continuous operating junction
temperature of 125 °C for thyristor in order to ensure that the lattice damages
are stabilized and no changes in thyristor characteristics take place during testing
and in real-time operation.
Reversal-annealing process :
An annealing method in the temperature range of 360-400 °C for duration of 60-
150 minutes is employed for reversing the recovery parameters in cases of
excessive gamma-irradiation. Subsequent to reversal, re-irradiation is carried out
to achieve the values within acceptable limits.
EXAMPLES
The above invention has been verified in two specific cases of manufacture of a
capsule-type control thyristor of rating 3200V/1000A. In either case, the end-
application uses series-connected thyristor to build stacks designed to support
high voltage (several kilovolts).


In the first example, the thyristors were manufactured against a customer
specification for a narrow band of reverse recovery charge [QRR] for use in
converter and inverter stations of High Voltage Direct Current [HVDC]. The
target specification was QRR = 0.6 to 0.9 mC and VT≤ 1.70V. Fig-2 shows the
histograms of QRR where the values are contained in the required specification
band by applying a combination of both gold diffusion and gamma irradiation
processes. Fig-3 shows the QRR-VT trade-off curve with the data realized in the
specification window.
The second case illustrates data on thyristors manufactured for VFD-application
[Variable Frequency Drive] with a narrow band specification of reverse recovery
current [IRR] in the range 34-42 A. Fig. 4 shows the histograms of IRR.
The initial correction to a coarse level helps in cutting down manufacturing cycle
time through relatively short fine-tuning steps. Manufacturing yield is improved
compared to single-step gold diffusion process, which is neither correctible nor
reversible.
The data on incremental correction of QRR on fully fabricated thyristor chips is
presented in Table-1. In this case, thyristors were subject to repeated gamma
irradiation to realize the specified values.
Fig.1: It describe the reverse recovery characteristic of thyristor showing
parameters Vt, Irr, Qrr, trr and tq.
The thyristor is turned off from conduction to blocking mode by withdrawal of
anode current. As the response is not instantaneous, it is controlled by
inductance in the load circuit. The current starts reducing by rate of di/dt and
passes through zero but withdrawal continues at the same di/dt rate due to


inductive effect and current reaches its peak (Irr). Further thyristor starts
supporting reverse voltage. Now onwards, reverse current reduces exponentially
and get influenced by recombination of carriers (holes & electrons).
trr is defined as the time between when current passes through zero and the time
where the current has dropped to 20% of Irr.
When the thyristor is turned off, as the response is not instantaneous, a finite
time is elapsed before switch is sufficiently off, that response time is called
turned off (tq) time.
Fig 2: It shows histograms of reverse recovery charge (Qrr). Our target for Qrr is
0.6-0.9 mC for a particular type of thyristor 3200 V/1000 A. Without gold
diffusion & gamma irradiation we get Qrr in range of 1.8-2.2 mC. With the gold
diffusion process a coarse correction is done so that we are getting Qrr in range
of 1.0-1.90 mC. Further a fine correction is done by gamma irradiation so that
we are getting Qrr in range of 0.6-0.9 mC which is our required range.
Fig. 3: It is trade off curve for Forward voltage drop Vt versus reverse recovery
charge. As we reduce the reverse recovery charge Qrr with the help of processes
like gold diffusion and gamma irradiation, correspondingly forward voltage drop
Vt is increased. For a particular type of phase control thyristor-3200 V/1000 A,
without gold diffusion and gamma irradiation, the obtained window of Qrr & Vt is
1.2-1.8 mC and 1.40-1.50 V, with the process of gold diffusion and gamma
irradiation, the available window is 0.6-0.9 mC and 1.50-1.70 V which is the
required range.


Table-2 shows reversal of QRR using an annealing procedure [360-400 °C, 60-150
minutes]. The annealed chips are re-irradiated, wherever necessary, so as to
realize the target values.
REFERENCES:
1. BJ.Baliga, Modren Power Devices, John Wiley & sons, 1987, pp.36-58,
380-387 and 410-413.
2. A.G.MILNES, Deep Impurities in Semiconductors, Wiley, New York, 1973.
3. BJ.Baliga and E.Sun, "comparison of gold, platinum and electron
irradiation for controlling lifetime in power rectifiers', IEEE Transactions on
Electron Devices, ED-24, 685-688 (1977).
4. R.O. Carlson, Y.S.Sun, and H.B. Assalit, "Lifetime control is silicon power
devices by electron or gamma irradiation", IEEE Transactions on Electron
Devices, ED-24, 1103-1108 (1977).
5. 'Method of controlling leakage currents and reverse recovery time of
rectifiers by hot electron irradiation and post-annealing treatments,' US
patent No. 4,137,099.

6. 'Non-uniform minority carrier lifetime distribution in high performance
silicon power devices', US Patent No. 6,828,690.
7. 'Semiconductor switching device and method of controlling a carrier
lifetime in a semiconductor switching device', US patent No. 6,465,871.
8. 'Semiconductor switching device having different carrier lifetimes between
a first portion serving as a main current path and the remaining portion of
the device,' US patent No. 6,100,575.
9. Thyristor manufacturing method and thyristor,' US patent No. 6,163,040.
10.'Multilayer semiconductor element', US patent No. 4,298,882.
11.'Method for producing large-area power semiconductor components', US
patent No. 4,806,497.
12.'Method of annealing fully-fabricated, radiation damaged semiconductor
devices,' US patent No. 5,017,508.








a) Technical description on table 1: This table shows correction in Qrr in
different stages so that target value of Qrr can be achieved-which has
been shown in table. For 2 chips at sl no. 15 & 16, targetted value has
been achieved in three stages of irradiation.
b) Technical description on table 2: This table describes the reversal of
gamma irradiation effect by annealing the chip at temp 360-400 deg C for
duration of 60-150 min. Table shows that by combination of annealing
temp & time, the gamma irradiation effect can be reversed by 33%-88%.

WE CLAIM:
1. A method of producing silicon power semiconductor thyristors with
narrow reverse recovery parameters, the method comprising the
steps of:
(a) forming a convention p+ -n-p-n-n+ thyristors structure by diffusing
silicon wafers with impurities;
(b) subjecting the diffused wafers to a gold diffusion process;
(c) joining the wafers to molybdenum plates by adapting an eutectic
alloying process followed by beveling and passivation of p-n junctions
terminating at the cylindrical edge;
(d) subjecting the fully-fabricated chips produced by step (c), to a
plurality of electrical measurements that include forward voltage
drop, and reverse recovery parameters, the forward conduction and
reverse recovery parameters having an opposed relationship, thereby
restricting the recovery parameters to a narrow band;
(e) exposing the gold-diffused thyristors chips produced by step (c) to
gamma rays for a duration that establishes a prescribed dose of
gamma rays at calculated dose rate; and

(f) subjecting the gamma-irradiated thyristor chips produced under step
step (e) to a stabilization-annealing process in which the chips being
annealed for about 12.00 hours at a temperature around 200°C to
ensure stabilizing of the lattice damages,
wherein the gold diffusion process is carried-out at a temperature of
800-830°C and soak time of 2-3 hrs followed by cooling to room
temperature.
2. The method as claimed in claim 1, wherein the silicon
wafers are n-type, 054mm of 140 ohm-cm resistivity and 800
microns thickness.
3. The method as claimed in claim 1 or 2, wherein the silicon wafers
diffused with p-type and n-type impurities.
4. The method as claimed in claim 1, wherein the molybdenum plate
is of thickness between 1.5 to 2.5 mm, and wherein the eutectic
alloying step comprises depositing aluminium of 20-microns thick
and silver of 2-microns thick layers using physical vapor deposition
process to form anode, cathode and gate electrodes.
5. The method as claimed in claim 1, wherein the gamma rays are
generated by using a gamma chamber that uses 60Co isotope, and
wherein the prescribed dose administrated is selected in terms of
Megarads and is based on correlation data pre-constructed for a
given type of semiconductor chip.

6. The method as claimed in claim 1, comprising the step of reversing
the recovery parameters in cases of excessive gamma-irradiation,
wherein a temperature range of 360°C to 400°C for duration of 60-150
minutes is employed for reversing.



ABSTRACT


TITLE" A METHOD OF PRODUCING SILICON POWER
SEMICONDUCTOR THYRISTORS WITH NARROW
REVERSE RECOVERY PARAMETERS"

The present invention relates to provides a method of controlling reverse recovery
parameters of silicon power semiconductor thyristors through a two-step method
comprising an initial coarse-correction using gold diffusion at wafer-processing stage
followed by exposure of fully fabricated chips to gamma rays for fine tuning. As the
second step of irradiation reversible and incremental dosages suffice. The above helps
in lowering the manufacturing cycle time. This is proven to be a versatile method
especially to meet stringent custom-specific requirements and has been adapted for
industrial manufacturing.

Documents:

00279-kol-2007 correspondence-1.1.pdf

00279-kol-2007 form-18.pdf

0279-kol-2007-abstract.pdf

0279-kol-2007-assignment.pdf

0279-kol-2007-claims.pdf

0279-kol-2007-correspondence others.pdf

0279-kol-2007-description (complete).pdf

0279-kol-2007-drawings.pdf

0279-kol-2007-form1.pdf

0279-kol-2007-form2.pdf

0279-kol-2007-form3.pdf

279-KOL-2007-(02-05-2012)-CORRESPONDENCE.pdf

279-KOL-2007-(24-08-2012)-AMANDED CLAIMS.pdf

279-KOL-2007-(24-08-2012)-AMANDED PAGES OF SPECIFICATION.pdf

279-KOL-2007-(24-08-2012)-CORRESPONDENCE.pdf

279-KOL-2007-(24-08-2012)-FORM-13.pdf

279-KOL-2007-(30-12-2011)-ABSTRACT.pdf

279-KOL-2007-(30-12-2011)-AMANDED CLAIMS.pdf

279-KOL-2007-(30-12-2011)-DESCRIPTION (COMPLETE).pdf

279-KOL-2007-(30-12-2011)-DRAWINGS.pdf

279-KOL-2007-(30-12-2011)-EXAMINATION REPORT REPLY RECIEVED.PDF

279-KOL-2007-(30-12-2011)-FORM-2.pdf

279-KOL-2007-(30-12-2011)-FORM-5.pdf

279-KOL-2007-(30-12-2011)-OTHERS.pdf

279-KOL-2007-CANCELLED PAGES.pdf

279-KOL-2007-CORRESPONDENCE 1.1.pdf

279-KOL-2007-CORRESPONDENCE.pdf

279-KOL-2007-EXAMINATION REPORT.pdf

279-KOL-2007-FORM 13.pdf

279-KOL-2007-FORM 18.pdf

279-KOL-2007-GPA.pdf

279-KOL-2007-GRANTED-ABSTRACT.pdf

279-KOL-2007-GRANTED-CLAIMS.pdf

279-KOL-2007-GRANTED-DESCRIPTION (COMPLETE).pdf

279-KOL-2007-GRANTED-DRAWINGS.pdf

279-KOL-2007-GRANTED-FORM 1.pdf

279-KOL-2007-GRANTED-FORM 2.pdf

279-KOL-2007-GRANTED-FORM 3.pdf

279-KOL-2007-GRANTED-FORM 5.pdf

279-KOL-2007-GRANTED-SPECIFICATION-COMPLETE.pdf

279-KOL-2007-REPLY TO EXAMINATION REPORT.pdf


Patent Number 256705
Indian Patent Application Number 279/KOL/2007
PG Journal Number 30/2013
Publication Date 26-Jul-2013
Grant Date 19-Jul-2013
Date of Filing 26-Feb-2007
Name of Patentee BHARAT HEAVY ELECTRICALS LIMITED
Applicant Address REGIONAL OFFICE: REGIONAL OPERATIONS DIVISION (ROD) PLOT NO:9/1,DJBLOCK 3RD FLOOR,KARUNAMOYEE, SALT LAKE CITY,KOLKATA-700091 REGISTERED OFFICE: BHEL HOUSE,SIRI FORT NEW DELHI-110049, INDIA
Inventors:
# Inventor's Name Inventor's Address
1 GOVINDARAJ, S C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
2 MAHESHWAR DEHURY C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
3 VIKRAM KUMAR YADAV C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
4 ANANDARAO, N C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
5 PAWAN C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
6 SETHURAMAN, A C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
7 HARIHARA KRISHNAN N. C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
8 GOVINDDARAJ,S; BHARAT HEAVY ELECTRICALS LIMITED,ELECTRONICS DIVISION,SEMICONDUCTORS AND PHOTOVOLTAICS DEPT,MYSORE ROAD,BANGALORE-560-026,
9 JAYARAMAN, K,N C/O BHARAT HEAVY ELECTRICALS LIMITED, ELECTRONICS DIVISION, SEMICONDUCTORS AND PHOTOVOLTAICS DEPT, MYSORE ROAD, BANGALORE-560 026,KARNATAKA INDIA
PCT International Classification Number H01L21/00
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA