Title of Invention	"SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT"
Abstract	The present invention is related to a system and method for improving the signal-to-noise ratio of frequency genefator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed to entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be improved while simultaneously achieving faster lock times.

Title of Invention

"SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT"

Abstract

The present invention is related to a system and method for improving the signal-to-noise ratio of frequency genefator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed to entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be improved while simultaneously achieving faster lock times.

Full Text	SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention. This invention relates to generating frequency signals in a signal processing system. 2. Description of the Related Art. Phase-Locked Loop (PLL) circuits have been used in many wireline and wireless applications for generating carrier frequencies and timing reference signals. Fig. 1(a) shows a PLL which is commonly used in a communications transceiver. This circuit includes a phase and frequency detector 1, a loop filter 2, and a voltage-controUed oscillator 3 which outputs a signal f^, at a desired frequency. A feedback loop connecting the oscillator to an input of the phase and frequency detector includes a divider 4 which divides the output of the oscillator by a value of (N + 1)/N. A modulus control circuit outputs a signal to the divider for controlling the value of N. In a PLL of the aforementioned type, it is well known that a trade-off exists between loop bandwidth and channel spacing. It is also known that channel spacing is the same as the comparison frequency. Given this relationship, it is often desirable to set the loop bandwidth of the PLL to be smaller than the comparison frequency by a factor of ten. Reducing the loop bandwidth to this value, however, produces a number of drawbacks. For example, loop bandwidth not only affects channel spacing, it also affects the lock time and amount of phase noise in a PLL. In fact, loop bandwidth is inversely proportional to both of these values. Therefore, reducing the loop bandwidth to a value smaller than the comparison frequency by a factor of ten wHI produce a commensurate increase in phase noise and lock time, which has found to be undesirable for many applications. Another drawback of the aforementioned PLL relates to a second type of noise. This noise appears in the form of spurious signals generated from mismatches that occur, for example, from the charge pump and the phase and frequency detector. More specifically, as shown in Fig. 1 (b), one mismatch occurs between the UP and DOWN current (ormore accurately the current sources) of the charge pump. Another mismatch occurs between the UP and DOWN signal paths in the phase and frequency detector, where ideally no mismatch should exist. These mismatches generate spurious signals which propagate throughout the host system to degrade performance and therefore, like phase noise, are also considered to be undesirable. Fig. 2 shows the manner in which these spurious signals are formed. In this diagram, fout corresponds to the output frequency of the phase-locked loop and fcutoff corresponds to the cutoff frequency of the PLL loop filter. The difference between fout and fcutoff defines the loop bandwidth of the circuit. In operation, mismatches along the signal path of the loop generate one or more spurious signals fsp that are located very dose to the output frequency fout in fact the spurious signals are so close to the output frequency (Af is very small) that they lie within the loop bandwidth of the circuit and therefore cannot be removed by the loop filter. These unsuppressed spurious signals further contribute to the degradation of signal quality and performance of the host system. In view of the foregoing discussion, it is evident that there is a need for a system and method for effectively suppressing noise in phase-locked loop circuits and especially loop circuits that are used in host systems having low noise and lock-time requirements. SUMMARY OF THE INVENTION An object of the present invention to provide a system and method for effectively suppressing noise in a phase-locked loop circuit. Another object of the present invention is to provide a system and method for suppressing at least two types of noise in a phase-locked loop, namely phase noise and spurious noise generated from mismatches that exist along the loop circuit signal path. Another object of the present invention is to provide a system and method which achieves one or more of the aforementioned objects without placing any restrictions on loop bandwidth, operating frequency, or any other functional parameter of the phase-locked loop. Another object of the present invention is to provide a system and method which achieves one or more of the aforementioned objects while simultaneously reducing the lock time of the phase-locked loop. Another object of the present invention is to suppress at least one of the aforementioned types of noise using a loop filter of the phase-locked loop. Another object of the present invention is to achieve one or more of the aforementioned objects for a phase-locked loop controlled by a Sigma-Delta modulator. Another object of the present invention is to provide a control system which achieves one or more of the aforementioned objects and also modulates a reference signal for the phase-locked loop in a way that finely adjusts the resolution of spurious noise suppression. These and other objects and advantages of the present invention are achieved by providing a system and method which suppress noise from the output of a frequency generator such as a phase-locked loop. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a standard filter located along the signal path of the generator. As a result, the signal-to-noise ratio of the generator is substantially improved, loop bandwidth may be increasd, and faster lock times may be realized. In accordance with one embodiment, the present invention provides a noise supression method that generates a frequency signal from a phase-locked loop based on a reference signal and then removes noise from the frequency signal by shifting a spurious signal of a predetermined order outside a loop bandwidth of ttie PLL. The loop bandwidth may be defined by a cutoff frequency of a loop filter, or alternatively by a frequency range lying between an output frequency and cutoff frequency of the filter. To achieve complete noise suppression, first-order spurious signals are shifted outside the loop bandwidth. However, suppression of only higher-order signals may be performed if application requirements so require or if otherwise desired. The spurious noise signals are shifted by controlling the value of a pulse-swallow divider situated along a feedback path of the phase-locked loop. The value of this divider may be controlled by a Sigma-Delta modulator and more specifically the modulation ratio set within this circuit. The noise being suppressed includes at least one of phase noise and noise generated by mismatches that occur in the phase and frequency detector and/or the charge pump of the PLL. In accordance with another embodiment, the present invention provides a method for suppressing noise by modulating a reference signal and then generating a frequency signal from a phase-locked loop based on the modulated reference signal. The modulation is performed to ensure mat harmonics of the original reference signal and the modulated reference signal are not coincident, at least throughout a significant range of frequencies. Preferably, the modulated reference signal is used to generate tie PLL frequency signal only during times when the harmonics are not coincident. This method may be used to provide fine adjustments to the spurious noise suppression performed by the Sigma-Deita modulator discussed herein. In accordance with another embodiment, the present invention provides a frequency generator which includes a phase-locked loop that generates a frequency signal based on a reference signal and a noise suppressor which shifts a spurious signal of a predetermined order outside a loop bandwidth of the PLL. The phase-locked loop includes a loop filter, and the loop bandwidth is defined by a cutoff frequency of the loop filter or corresponds to a frequency range that lies between the frequency signal generated from the PLL and a cutoff frequency of the filter. The noise suppressor preferably includes a frequency divider in a feedback loop of the PLL and a controller which sets the frequency divider to a value which performs the spurious signal shift. The frequency divider may be a pulse-swallow divider and the controller may include a Sigma-Delta modulator. In addition to these features, the noise suppressor may include a reference signal modulator for fine tuning suppression of the spurious signals. In accordance with another embodiment, the present invention provides a system for controlling a phase-locked loop comprising a divider which divides a frequency signal output from the PLL and a controller which sets the divider to a value which shifts a spurious noise signal of a predetermined order outside the loop bandwidth of the PLL. The loop bandwidth may be defined based on the cutoff frequency of a loop fitter and the divider value may be controlled to suppress virtually any order of spurious noise signals desired. The controller may also include a modulator for generating a modulated reference signal for fine tuning supression of the spurious signals. BRIEF DESCWPTKW OF THE DRAWINGS Fig. 1(a) is a diagram showing a related-art phase-locked loop circuit, and Fig. 1(b) is a diagram showing different types of mismatches that may occur in the phase and frequency detector and/or charge pump of the related-art phase-locked loop, which mismatches lead to the generation of spurious signals that degrade system performance. Fig. 2 is a diagram showing the generation of a spurious noise signal in the related-art circuit of FIG. 1(a). Fig. 3 is a diagram showing one embodiment of a phase-locked loop circuit in accordance with the present invention. Rg. 4 is a diagram showing an example of how the system and method of the present invention may be implemented to shift spurious noise signals outside the loop bandwidth of a PLL to thereby enable them to be removed by a loop fitter. Figs. 5(a) and 5(b) are graphs showing harmonics of an original reference frequency and a modulated reference frequency generated in accordance with one example of the present invention. Fig. 6 is a diagram showing one embodiment of the reference modulator of the present invention. Fig. 7 is a diagram showing another embodiment of the reference modulator of the present invention. Figs. 8(a) - 8(g) are diagrams showing the manner in which signals are processed by each of the elements of the reference modulator shown in Fig. 7. Fig. 9 is a diagram showing one embodiment of the reference modulator of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention includes various embodiments of a system and method for suppressing noise in a phase-locked loop circuit. In accordance with one embodiment, the system and method suppresses noise that results from mismatches relating to the charge pump and phase and frequency detector. This is accomplished using a Sigma-Delta modulator which controls a divider in a feedback path of the PLL so that spurious noise components are shifted outside the operating loop bandwidth of the circuit Other embodiments suppress noise by modulating a reference frequency signal input into the phase and frequency and detector. Still other embodiments suppress noise using a combination of the foregoing techniques. Through these embodiments, spurious noise components are shifted far away from the desired output frequency of the PLL so that they can be eliminated by a loop filter. As a result, a substantial improvement in signal-to-noise ratio and loop bandwidth may be realized along with a proportional reduction in phase noise and lock time. Referring to Fig. 3, one embodiment of the system and method of the present invention includes a reference modulator 20 and a Sigma-Delta modulator 30 for controlling the output frequency of a phase-locked loop. The phase-locked loop is formed from a phase and frequency detector 22, a loop filter (e.g., a low-pass or bandpass filter) 23, a pulse-swallow frequency divider 24, and a voltage-controlled oscillator 25 for outputting a signal at a desired frequency fvco The pulse-swallow frequency divider includes a program counter 27 and swallow counter 28 which respectively assume values P and S under control of the Sigma-Delta modulator. The Sigma-Defta modulator sets the values of the program and swallow counters based on parameters, NΣ and DΣ, in order to generate the desired output frequency fm. This output signal may be used to modulate or demodulate signals in a communication transceiver or to perform any one of a variety of other purposes. The values of P, S, NΣ and DΣ may be determined from the specific prescaler being used. Various prescalers and the manner in which they may be used to set the values of the counters are generally known to those skilled in the art. See, for example, the text RF MICROELECTRONICS, Chapter 8, by Behzad Razavi. If left unconnected, the output frequency of the voltage-controlled oscillator will contain various types of noise, including spurious signals generated from mismatches relating to the phase and frequency detector and the charge pump. This situation is depicted in Fig. 2 where the frequency separation Af is so small that the spurious signals cannot be removed by the loop filter. The present invention removes this and other types of noise (including phase noise) by shifting the spurious signals far away from the output frequency f^ of the PLL. This is accomplished through adjustments made by the Sigma-Defta modulator, which adjustments are preferably performed in combination with a modulation of the reference signal of the PLL. First, the reference modulator modulates the input reference signal fre,by an amount which causes this signal to be multiplied by the value Had. . This results in the formation of a modulated reference signal, (Equation Removed) , which is input into the phase and frequency detector. To effect this modulation, the values of NΣ, and DΣ are preferably selected to be integers by observing one or more of the following considerations: 1) The frequency range of the system. If the required frequency range is very narrow and only a few channels exist hi the range, only one reference modulator may be used. However, if the range is very wide, one reference modulator may not be sufficient to achieve a desired degree of spurious signal suppression. In this case, multiple reference modulators may be included and selectively chosen to achieve an optimal degree of suppression. Tables 2 and 3 (discussed in greater detail infra) include non-limiting example of the values of N^ and D^ which may be used to perform the reference signal modulation of the present invention. If the required frequency range does not include the frequency of 944.65 MHz or 1102.1 MHz, 8/9 modulation may be enough for suppression. But, if that frequency is included another modulation such as 5/6 may be used for the applicable channel. This multiple reference-modulator embodiment is discussed in greater detail below. 2) The desired spur level for the system. 3) The loop filter bandwidth, which may be explained as follows. The parameters of the loop filter depend on the reference frequency. As the reference modulation changes the reference dock, the loop filter parameters should be changed. If the difference between the original reference clock and the modulated reference clock is small, the loop filter can be shared for both the original clock and the modulated dock as long as system specifications such as phase noise, spurious signal suppression, and lock time allows it. For example, if 8/9 modulation and 2/3 modulation for a channel shows the same spurious signal suppression, the 8/9 modulation may be preferred because the 8/9 modulated reference signal is closer to the original reference frequency than the 2/3 modulated reference signal. 4) The hardware complexity of the system. For example, while multiple modulation ratios (3/4, 5/6,7/8, 8/9, etc.) may be acceptable for purposes of achieving a desired level of spurious signal suppression, it may not be possible to achieve all the ratios given the hardware in use. Thus, hardware may be one factor to consider when selecting a modulation ratio in accordance with the present invention. During the time the reference signal is modulated or some predetermined time before, the values defining the modulation ratio of the Stgma-Delta modulator, NΣ and DΣ are computed along with P and S which correspond to the values of the program and swallow counters. Together, these parameters along with parameter K of prescaier 29 determine the value the pulse-swallow frequency divider uses to divide the output frequency of the VCO. One way in which parameters NΣ, DΣ, P, and S may be calculated will now be discussed in greater detail. The values of fico, R, K, and k are preferably determined at the system or architecture level to meet, for example, the requirements of a desired application. (The R value may be related to the design specification of the PLL (e.g., R = 1 if k = 19.2 MHz) and the K value may be related to the design of the prescaier.) The only unknown values therefore are P, S, NΣ, and DΣ DΣ. This parameter may be determined in various ways. First, DΣ may be determined as a simple power of two, e.g., 210/212/213... In this case, as the denominator increases, hardware complexity also increases and the frequency resolution of the PLL increases. Thus, there is a trade off between precision and hardware complexity. Second, if the frequency resolution (or channel spacing) of the system is known, DΣ may be determined by the following equation: DΣ = (fref R) / fch. For example, in the Korean CDMA system, fref= 19.2 MHz, R = 1, and fch = 10 kHz. Given these values, DΣ = 1920. P. S.andNΣ. These parameters are integer values which satisfy the following relation: fvco = (fre R) * (K P + S + NΣ DΣ). If two or more consfrainte are added to this relation, the solution is unique. The first constraint is that 0 ≤S Second, the pulse-swallow frequency divider divides the output of the voltage-controlled oscillator f.xo by the value in Equation (1), so that the comparison frequency input into the phase (Equation Removed) Since the modulated reference frequency fΣ is different from the unmodulated reference frequency fΣ, the parameters of the pulse-swallow frequency divider must be changed so that the signal input into the phase and frequency detector from the feedback loop matches the modulated reference frequency output from the reference modulator. Before being input into the phase and frequency detector, the modulated reference frequency f^ may be divided by the value R corresponding to an optional reference divider 31. From Equation (1), it is dear that in order to achieve a desired output frequency signal (m (which, for example, may be a local osciator signal used in baseband signal recovery circuit of a communications transceiver), the output of the voltage-controiled oscillator must be divided by a value given by Equation (1) in the feedback loop. If the reference divider and prescaler counter values R and K are known for a given application, the remaining parameters (P, S, N) can be determined as explained above and in view of Equation (1) for a given input frequency and the VCO output frequency. The output frequency of the PU_ may be expressed by the following equation: In Equation (2), represents the integer part of the (Equation Removed) desired frequency fm and the (Equation Removed) represents the fractional part of this frequency. When mismatches occur in the PLL, spurious noise signals form at frequencies which coincide with the fractional part of the desired frequency f^ and harmonics of this frequency. In order to achieve the separation required to filter out all or a portion of these spurious signals, the present invention controls one or more parameters in the above equation. Initially, the modulation ratio of the Sigma-Delta modulator is controlled to achieve a desired degree of frequency separation. This may be empirically understood with reference to the fractional part of Equation (2), which corresponds to the frequency offset (Af) between the desired frequency fm and the first-order spurious signals f^. (This offset may also exist between adjacent-orders of the spurious signals themselves.) (Equation Removed) frequency offset (or separation distance between the spurious signals and the desired output frequency) becomes larger. Inclusion of the term in the fractional part of Equation (2) thus ensures that spurious signals fv of a predetermined order are formed sufficiently far from the desired output frequency fm that they can be removed by loop filter 23 along the signal path. This may be achieved, for example, by making the fractional part in Equation (2) and more specifically the ratio of NΣ and DΣ relatively large. This affects the values of P and S which, in turn, ultimately leads to an adjustment of the value of the pulse-swallow feedback divider of the PLL To achieve complete noise succession, the fractional part of Equation (2) is set large enough to ensure that the first-order spurious signals are shifted below the cutoff frequency of the loop filter. If desired, however, the fractional part may be set to other proper values to filter out higher-order spurious signals. White a lesser degree of noise suppression is realized in this case, oflier system requirements may be met, thereby making the present invention a suitable solution. Fig. 4 shows how adjusting the values of NΣ and DΣ can lead to suppression of spurious noise signals in the output of the PLL. In this illustrative example, fm corresponds to the desired output frequency of the PLL, f corresponds to the cutoff frequency of the loop filter, and the loop bandwidth corresponds to the difference between fm and fcMf. In accordance with the presentinventkxi, the fractional part of Equation (2) and particularly the ratio of NΣ and DΣ is computed to be sufficiently large to shift the spurious noise signals fspv fsp» • • fst* outside the loop bandwidth and thus in this case below cutoff frequency f^ where they can be removed by the loop filter. This shift is shown by frequency offset Af. The ratio of NΣ and DΣ of reference modulator 20 may be controlled to further adjust the degree of separation. More specifically, while this reference modulator is considered to be an optional feature of the present invention (e.g., the frequency separation required for spurious noise suppression may be accomplished solely by adjusting the modulation ratio formed between NΣ and DΣ), the ratio of NΣ and DΣ may be controlled as a way of fine tuning the spurious signal shift performed in the fractional part of Equation (2). The values of NΣ and 0Σ are preferably determined based on the design of the reference modulator. Table 1 provides examples of values which when input into Equation (2) generate a frequency separation Af sufficient to shift spurious noise signals outside the loop bandwidth of the PLL. These values are reflected in Fig. 4 to illustrate the superior performance of the invention. (T able Removed)Tabte-1 In Table 1, NΣ and DΣ values are set to 11817 and 15744 respectively and the modulation ratio of the reference signal modulator is 8/9. Plugging these values into Equation (2), the output frequency fm of the PLL is calculated to be 905.29 MHz. The value corresponding to the fractional part of this equation reveals the superior performance of the present invention for this example: As shown by Equation (3), spurious noise signals produced from mismatches in the PLL will appear at frequencies which coincide with the fractional part of Equation (2), which . is computed to be 1 3. 1 3 MHz. The frequency separation Af between the output frequency and the first-order spurious noise signal fv1 will therefore be 6.55 MHz. (This number is obtained by subtracting 13.13 MHz from the frequency of the modulated input reference signal (19.68 * 8/9)). Using these values, the Sigma-Delta modulator shifts the first-order spurious signals outside the loop bandwidth of the PLL, thereby allowing the cutoff frequency /^of the loop filter to eliminate these and higher-order noise signals from the output frequency. While the modulation ratio of 8/9 is used in this example and provides for fine resolution adjustment, it can be seen that an even wider frequency separation may be achieved with other reference modulating ratios. In the foregoing example, the cutoff frequency and/or the loop bandwidth may be determined based on the specific application requirements of the system including requirements for phase noise and spurious signal suppression. As shown, a greater suppression of the spurious signal fv occurs by the loop filter as the frequency offset (Af) increases from the carrier fm increases. White optional, the reference modulation may advantageously be used to increase this frequency offset Also, in the foregoing example, the frequency separation was achieved at least in part by setting the modulation ratio of the Sigma-Delta modulator to a relatively large value. For comparison purposes, it is noted that a small value of this ratio would not be able to and the P and S values are 11 and 2 respectively, then the resulting frequency separation would be 1 0 kHz for the same values of K and f^ using an umodulated reference frequency. This separation would in most applications He well within the loop bandwidth of the PLL and thus would not be able to be suppressed by the loop fitter. Additionally or alternatively, in controlling the values of the Sigma-Delta modulator the numerator Nu may be' adjusted to be far away from the sub-harmonics of the denominator Dza. This means, for example, that if the ratio of the numerator and denominator — — of the Sigma-Defta modulator is near (Equation Removed) reference modulation can reduce or eliminate the spurious signals. The present invention thus effectively suppresses noise in a frequency generator such as a PLL in a way that substantially improves signal-to-noise ratio. This is evident by comparing the present invention to other circuits. For example, in the related-art system of Fig. 1(a), the frequency separation between the spurious noise signal and the PLL output frequency is equal to 1 0 kHz, which is shown to lie within the loop bandwidth of the circuit. (See Fig. 2). Because the spurious signal lies within this bandwidth, the loop filter of the Fig. 1 (a) PLL will not be able to remove the spurious noise signal from the output frequency. As a result, the output of this circuit will have a tower signal-to-noise ratio than desired by many applications. In contrast, by setting at least one of the N^ and D^ parameters to appropriate values based on the loop bandwidth of tie PLL and then optionally modulating the input reference frequency by to. perform fine tuning adjustment, the present invention ensures that spurious noise generated from loop mismatches forms far away from the output frequency of the PLL, thereby enabling their suppression by the loop filter. In addition to achieving greater noise suppression, the system of the present invention is able to achieve faster lock times white concurrently using a wider loop bandwidth compared with other systems which have been proposed. This may be understood by realizing that PLL lock time is inversely proportional to loop bandwidth. Operating with a wider loop bandwidth will therefore allow the present invention to achieve reduced lock times compared with other PLL circuits, while simultaneously achieving an improved level of spurious signal suppression. All of these advantages translate into improved signal-to-noise ratio and thus a higher quality communications transicever. Modulation of the reference signal may be accomplished in a variety of ways. Preferably, the refiefence frequency f^ is modulated to ensure that f^ is not close to the harmonics of the original reference frequency f^. Performing modulation in this manner is desirable in order to avoid the possibility of having spurious noise signals reappear in the output of PLL, in spite of the modulation performed by the Sigma-Delta modulator. This may be understood with reference to the following example. Figs. 5{a) and 5(b) are graphs respectively showing harmonics of an original reference frequency and a modulated reference frequency generated in accordance with one example of the present invention. In Fig. 5(a), harmonics of the original reference frequencare shown as (Equation Removed) and so on. In Fig. 5(b), the modulated reference signal is generated based on a modulation ratio of Harmonics of the modulated input reference frequency therefore appear at frequencies of (Equation Removed) In this example, N is assumed to be an integer and preferably a multiple of 6, and a zone where the harmonics of the modulated reference frequency and original reference signal are coincident are shown by X. In this zone, the invention may prove to be ineffective because the modulated reference frequency may not be able to suppress spurious signals in the output of the PLL. These principles may serve as a basis for defining the operating range of the Sigma-Delta controlled PLL of the present invention. More specifically, as shown in Figs. 5(a) and 5{b), the modulated reference frequency may be used as the comparison frequency input into the phase and frequency detector, instead of the original reference frequency, until harmonics of toe modulated reference frequency become equal to the harmonics of the original reference frequency. If no restriction on chip area exists, various values of N^ and 0,^ may be used for a given frequency channel. For example, an N^/)^ of 5/6 may be desirable to effect spurious signal suppression for one channel but an N^D^ of 8/9 may be desirable for another channel. Also, for any given channel both modulation ratios may be acceptable. By changing the value of NMIJDmaai a variety of acceptable frequency offsets may be achieved for purposes of spurious signal suppression. The one that is most compatible to the system (e.g., given hardware complexity) may be selected. Fig. 6 shows one type of reference modulator of the present invention which can achieve the flexibility discussed above. This modulator is formed from two reference modulators 51 and 52 and a selector 53 may be included to select the appropriate modulation ratio N^/D,^ for the applicable channel. The first modulator has a modulation ratio of 5/6 and the second modulator a ratio of 8/9. While two modulators are shown, those skilled in the art can appreciate that the reference modulator of the present invention may include more than two modualtors, e.g., one modulator may be provided for each channel or group of channels in Die communications system. In this case, each modulator may have a modulation ratio selected specifically, and preferably optimally, for that channel or channel group. For channels which have no spurious tones, the reference modulator may be omitted or circumscribed and the reference clock may be fed directly to the internal PLL block. Fig. 7 shows another way in which the reference modulator of the present invention may be constructed to produce these results. This modulator includes a first duty cycle corrector 70, a frequency doubter 71, a second duty cycle corrector 72, a fractional divider 73, a third duty cycle corrector 74, and anotier fractional divider 75. The fractional dividers are set to multiple their input signals by 2/3. Those skilled in the art can appreciate, however, that other fractional values may be used if desired. Figs. 8(a) - 8(g) are diagrams showing the manner in which signals are processed by each of the elements of the reference modulator shown in Fig. 7. Fig. 8(a) shows the original reference frequency f^input Into the reference modulator. Fig. 8(b) shows that the first duty cycle corrector processes the original reference to produce a clean signal by removing sub-harmonic components therefrom. Fig. 8{c) shows that the frequency doubter doubles the frequency of the signal output from the first duty cycle corrector. This results in cutting the period of the signal in half. Fig. 8(d) shows that the second duty cycle corrector deans up the output of the frequency doubler by removing sub-harmonics. Fig. 8(e) shows that the signal output from the second duty cycle corrector is multiplied by a predetermined fraction, which in this example is 2/3. Fig. 8(f) shows that the third duty cycle corrector cleans up the output of the first fractional divider by removing sub-harmonics. This causes the period of the signal to be increased by an amount commensurate with the division performed by the first fractional divider. Fig. 8{g) shows that the signal output from the third duty cycle corrector is multiplied by a predetermined fraction, which in this example is also 2/3. The result is to produce a modulated reference frequency. Once ttiis signal is processed to remove harmonics, the final modulated reference signal is produced whose period is increased by an amount commensurate with the division performed by the second fractional divider. In the foregoing embodiment of the reference modulator, the numerator of the reference modulator should be different from one in order to increase operating range of the PLL while simultaneously preventing a reformation of the spurious signals. In fact, it may be preferable to usea high value of the numerator. The fractional divider and frequency doubler may be adapted to generate a numerator of .this type. For instance, in the examjpte previously discussed one frequency doubler and two fractional .dividers were used to generate the modulated reference signal, equal to fm " to generate the modulated reference frequency, with the same fraction of 2/3 used for both dividers. While these values may be preferable, those skiHed in the art can appreciate that any number of the frequency multiplication and division circuits may be used, as long as a desired fractional division ratio — MBL js achieved. Fig. 9 shows another way in which Uie reference frequency modulator of the present invention may be constructed. This modulator includes a number of frequency dividers 80 connected to a mixer 81 . The frequency dividers multiply the original reference frequency f^, by values which, when input into the mixer, generate the desired fractional frequency. For example, the frequency dividers may outout signals equal to — frtf . The mixer will then output a signal equal to -frtf . After mixing, unwanted harmonics generated from the mixer are filtered out using a bandpass filter 82. A limiter 83 is then used to produce the modulated reference frequency in the form of a digital pulse. Example Table 2 shows exemplary values that may be used in accordance with the present (Equation Removed) invention. To achieve an acceptable level of spur reduction, the ratio is selected to be large to shift spurious signals outside the cutoff frequency. Also, the reference frequency is modulated by an —sasi ratio which ensures that the harmonics of is not dose to the (T able Removed) Sigma-Delta modulator values of Nj^ and D^. The worst case spur is shown to exist between 905.29 MHz and 1161.13 MHz. (The N and D columns make up the N/D ratio which corresponds to the worst-case spur, e.g., N/D = 1/1968. The ratio of N/D = 1967/1968 is not induded because it has the same characteristics shown in the Table 2.) The worst-case spur is near at a multiple of the reference dock frequency. They are listed from 46 f^ to 59 ^ as an example. Also, an 8/9 reference modulation is used as an example. Note that the Sigma-Delta modulation ratio -sss- ratio has a circular relation according to fm or Aiew multiples of the reference clock as in Fig. 5, e.g., the ratio of (Equation Removed) .... 11817/15744,13785/15744 is repeated. Not all the values of in Table 2 are optimal. For example, in the case where fM = 944.65, the Sigma-Delta modulation ratio —. This produces a frequency separation of 10 kHz when a reference modulation rato —(Equation Removed) separation may in some instances prove to be Insufficient for purposes of achieving spurious signal suppression. In this case, the reference signal modulation ratio may be changed to produce a frequency separation sufficient to achieve an acceptable level of spurious signal supression. In the example under consideration, this may be accomplished by setting = 5/6. A comparison of the results obtained for these modulation ratios is set forth in Table 3. (T able Removed)* Tables Using the modulation ratio of 5/6 instead of 8/9, the following frequency offset is obtained: k * (N»AJ * (N.JD.J = 19.68(5/6}(5910/9840) = 9.85 MHz. This offset is considerably larger than the 10 kHz offset obtained using the 8/9 modulation ratio and in fact large enough to shift spurious noise outside the cutoff frequency of the loop filter in this example, thereby achieving spurious signal suppression. From this example, it is therefore evident that at least one and preferably both of (Equation Removed) may be controlled to suppress spurious signals to thereby improve signal-to-noise ratio in a communications receiver. Other modifications and variations to the invention wiU be apparent to those skilled in the art from the foregoing disclosure. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention. We claim:- 1. A frequency generator, comprising: a phase-locked loop (22, 23, 24, 25) (herein after referred to as the PLL) which generates a frequency signal based on a reference signal; and a noise suppressor which shifts a spurious signal of a predetermined order outside a loop bandwidth of the PLL, wherein the noise suppressor includes a frequency divider (24) in a feedback loop of the PLL, and a controller (30) which sets the frequency divider to a value Which shifts the spurious signal of said predetermined order outside the loop bandwidth of the PLL, and wherein the frequency divider (24) have a swallow counter (28) and a program counter (27) and wherein values for the swallow and program counters are controlled based on a modulation ratio of a Sigma-Delta modulator (30), said values for the swallow and program counters being controlled to generate said values which shifts the spurious signal of said predetermined order outside the loop bandwidth of the PLL. 2. The frequency generator as claimed in claim 1, wherein the PLL have a loop filter (23) and the loop bandwidth is defined by a cutoff frequency of the loop filter. 3. The frequency generator as claimed in claim 1, wherein said values of the swallow and program counters (27, 28) are controlled to shift a first-order spurious signal outside the loop bandwidth of the PLL. 4. The frequency generator as claimed in claim 1, wherein the PLL generates the frequency signal (fveo) in accordance with the equation 1 described in description Where fref is the reference signal, R is a value of a reference signal divider (20), P is the value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio of the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24). 5. The frequency generator as claimed in claim 1 wherein the PLL generates the frequency signal in accordance with the equation 2 as described in the description. Where fref is the reference signal, R is a value of a reference signal divider (20), Nmod and Dmod define a modulation ratio for the reference signal, P is the value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio qf the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24). 6. The frequency generator as claimed in claim 1, wherein the modulated reference signal is used as a comparison signal for the PLL as long as harmonics of the modulated reference signal are not coincident with harmonics of the unmodulated reference signal. 7. The frequency generator as claimed In claim 1, comprising: a frequency shifter (20) which shifts the reference signal to a fractional fixed value for input into a phase/frequency detector (22) of the PLL, said fractional fixed value further shifting the spurious signal of said predetermined order. 8. A noise suppression method employed an apparatus as claimed in claim 1, comprising generating a frequency signal from a phase-locked loop (22, 23, 24, 25) (hereinafter referred to as the PLL) based on a reference signal; and removing noise from the frequency signal by setting a frequency divider (24) in a feedback loop of the PLL to a value which shifts a spurious signal of a predetermined order outside a loop bandwidth of the PLL, wherein setting the frequency divider (24) includes: adjusting at least one of a swallow counter (28) and a program counter (27) in the frequency divider (24) to a value which shifts the spurious signal of a said predetermined order outside the loop bandwidth of the PLL. 9. The method as claimed in claim 8, wherein the loop bandwidth Is defined by a cutoff frequency of a loop filter (23) in the PLL. 10. The method as claimed in claim 8, wherein the loop bandwidth corresponds to a frequency range that lies between the frequency signal generated from the PLL and a cutoff frequency of a loop filter (23) in the PLL. 11. The method as claimed in claim 8, wherein said noise is removed by adjusting at least one of the swallow counter (28) and a program counter (27) to a value which shifts a first-order spurious signal outside the loop bandwidth of the PLL. 12. The method as claimed in claim 8, wherein at least one of the swallow counter (28) and program counter (27) is set by a Sigma-Delta modulator (30). 13. The method as claimed in claim 12, comprising computing a modulation ratio of the Sigma-Delta modulator (30) based on the loop bandwidth of the PLL; and setting the value of at least one of the swallow counter (27) and program counter (28) base on the modulation ratio computed for the Sigma-Delta modulator (30). 14. The method as claimed in claim 8, wherein the spurious signal is generated by a mismatch relating to at least one of a phase and frequency detected and a charge pump of the PLL. 15. The method as claimed in claim 8, wherein a value for at least one of the swallow and program counters (27, 28) is controlled based on a modulation ratio of a Sigma-Delta modulator (30). 16. The method as claimed in claim 15, wherein a numerator of the modulation ratio (NΣ) is at least 50% of a denominator of the modulation ratio (DΣ). 17. The method as claimed in claim 16, further comprising: modulating the reference signal into the PLL with a reference modulator (20), wherein the reference modulator has a modulation ratio (Nmod/Dmod) such that Nmod is at least 50% of Dmod- 18. The method as claimed in claim 8, wherein the spurious signal is generated from a mismatch in at least one of a charge pump and phase/frequency detector (22) in the PLL, wherein the mismatch in the charge pump includes a mismatch between UP and DOWN current sources, wherein the spurious signal is generated from a mismatch between UP and DOWN signal paths in the phase/frequency detector (22). 19. The method as claimed in claim 8, wherein the value of the frequency divider (24) is set based on a modulation ratio of a Sigma-Delta modulator (30) for removing the spurious signal. 20. The method as claimed in claim 8, further comprising: shifting the reference signal to a fractional fixed value for input into a phase/frequency detector (22) of the PLL, said fractional fixed value further shifting the spurious signal of said predetermined order. 21. The method as claimed in claim 8, wherein the swallow counter and program counter (27, 28) are both adjusted to shift the spurious signal of said predetermined order outside the loop bandwidth of the PLL. 22. The method as claimed in claim 21, wherein the values for the swallow and program counters (27, 28) are controlled based on the modulation ratio of the Sigma-Delta modulator (30), said values for the swallow and program counters (27-28) being controlled to generate said value which shifts the spurious signal of said predetermined order outside the loop bandwidth of the PLL. 23. The method as claimed in claim 22, wherein the frequency signal of the PLL (fvco) is generated in accordance with the equation 2 as described in the description, Where fref is the reference signal, R is a value of a reference signal divider (20), Nmod and Dmod define a modulation ratio for the reference signal, P is the value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio of the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24). 24. The method as claimed in claim 22, further comprising: modulating the reference signal input into the PLL. 25. The method as claimed in claim 24, wherein the frequency signal of the PLL (fvco) is generated in accordance with the equation 1 as described in the description Where fret is the reference signal, R is a value of a reference signal divider, P is the value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio of the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24). 26. The method as claimed in claim 24, comprising using the modulated reference signal as a comparison signal for the PLL as long as harmonics of the modulated reference signal and the unmodulated reference signal are not coincident. 27. A noise suppression method substantially as herein described with reference to the foregoing description and the accompanying drawings. 28. A method for suppressing noise in a frequency generator substantially as herein described with reference to the foregoing description, tables and the accompanying drawings. 29. A frequency generator substantially as herein described with reference to the foregoing description, tables and the accompanying drawings.

Full Text

SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT
BACKGROUND OF THE INVENTION
1. Field of the Invention.
This invention relates to generating frequency signals in a signal processing system.
2. Description of the Related Art.
Phase-Locked Loop (PLL) circuits have been used in many wireline and wireless applications for generating carrier frequencies and timing reference signals.
Fig. 1(a) shows a PLL which is commonly used in a communications transceiver. This circuit includes a phase and frequency detector 1, a loop filter 2, and a voltage-controUed oscillator 3 which outputs a signal f^, at a desired frequency. A feedback loop connecting the oscillator to an input of the phase and frequency detector includes a divider 4 which divides the output of the oscillator by a value of (N + 1)/N. A modulus control circuit outputs a signal to the divider for controlling the value of N.
In a PLL of the aforementioned type, it is well known that a trade-off exists between loop bandwidth and channel spacing. It is also known that channel spacing is the same as the comparison frequency. Given this relationship, it is often desirable to set the loop bandwidth of the PLL to be smaller than the comparison frequency by a factor of ten. Reducing the loop bandwidth to this value, however, produces a number of drawbacks.
For example, loop bandwidth not only affects channel spacing, it also affects the lock time and amount of phase noise in a PLL. In fact, loop bandwidth is inversely proportional to both of these values. Therefore, reducing the loop bandwidth to a value smaller than the comparison frequency by a factor of ten wHI produce a commensurate increase in phase noise and lock time, which has found to be undesirable for many applications.
Another drawback of the aforementioned PLL relates to a second type of noise. This noise appears in the form of spurious signals generated from mismatches that occur, for example, from the charge pump and the phase and frequency detector. More specifically, as shown in Fig. 1 (b), one mismatch occurs between the UP and DOWN current (ormore accurately the current sources) of the charge pump. Another mismatch occurs between the UP and DOWN signal paths in the phase and frequency detector, where ideally no mismatch should exist. These mismatches
generate spurious signals which propagate throughout the host system to degrade performance and therefore, like phase noise, are also considered to be undesirable.
Fig. 2 shows the manner in which these spurious signals are formed. In this diagram, fout corresponds to the output frequency of the phase-locked loop and fcutoff corresponds to the cutoff frequency of the PLL loop filter. The difference between fout and fcutoff defines the loop bandwidth of the circuit. In operation, mismatches along the signal path of the loop generate one or more spurious signals fsp that are located very dose to the output frequency fout in fact the spurious signals are so close to the output frequency (Af is very small) that they lie within the loop bandwidth of the circuit and therefore cannot be removed by the loop filter. These unsuppressed spurious signals further contribute to the degradation of signal quality and performance of the host system.
In view of the foregoing discussion, it is evident that there is a need for a system and method for effectively suppressing noise in phase-locked loop circuits and especially loop circuits that are used in host systems having low noise and lock-time requirements.
SUMMARY OF THE INVENTION
An object of the present invention to provide a system and method for effectively suppressing noise in a phase-locked loop circuit.
Another object of the present invention is to provide a system and method for suppressing at least two types of noise in a phase-locked loop, namely phase noise and spurious noise generated from mismatches that exist along the loop circuit signal path.
Another object of the present invention is to provide a system and method which achieves one or more of the aforementioned objects without placing any restrictions on loop bandwidth, operating frequency, or any other functional parameter of the phase-locked loop.
Another object of the present invention is to provide a system and method which achieves one or more of the aforementioned objects while simultaneously reducing the lock time of the phase-locked loop.
Another object of the present invention is to suppress at least one of the aforementioned types of noise using a loop filter of the phase-locked loop.
Another object of the present invention is to achieve one or more of the aforementioned objects for a phase-locked loop controlled by a Sigma-Delta modulator.
Another object of the present invention is to provide a control system which achieves one or more of the aforementioned objects and also modulates a reference signal for the phase-locked loop in a way that finely adjusts the resolution of spurious noise suppression.
These and other objects and advantages of the present invention are achieved by providing a system and method which suppress noise from the output of a frequency generator such as a phase-locked loop. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a standard filter located along the signal path of the generator. As a result, the signal-to-noise ratio of the generator is substantially improved, loop bandwidth may be increasd, and faster lock times may be realized.
In accordance with one embodiment, the present invention provides a noise supression method that generates a frequency signal from a phase-locked loop based on a reference signal and then removes noise from the frequency signal by shifting a spurious signal of a predetermined order outside a loop bandwidth of ttie PLL. The loop bandwidth may be defined by a cutoff frequency of a loop filter, or alternatively by a frequency range lying between an output frequency and cutoff frequency of the filter. To achieve complete noise suppression, first-order spurious signals are shifted outside the loop bandwidth. However, suppression of only higher-order signals may be performed if application requirements so require or if otherwise desired.
The spurious noise signals are shifted by controlling the value of a pulse-swallow divider situated along a feedback path of the phase-locked loop. The value of this divider may be controlled by a Sigma-Delta modulator and more specifically the modulation ratio set within this circuit. The noise being suppressed includes at least one of phase noise and noise generated by mismatches that occur in the phase and frequency detector and/or the charge pump of the PLL.
In accordance with another embodiment, the present invention provides a method for suppressing noise by modulating a reference signal and then generating a frequency signal from a phase-locked loop based on the modulated reference signal. The modulation is performed to ensure mat harmonics of the original reference signal and the modulated reference signal are not coincident, at least throughout a significant range of frequencies. Preferably, the modulated reference signal is used to generate tie PLL frequency signal only during times when the harmonics are not coincident. This method may be used to provide fine adjustments to the spurious noise suppression performed by the Sigma-Deita modulator discussed herein.
In accordance with another embodiment, the present invention provides a frequency generator which includes a phase-locked loop that generates a frequency signal based on a reference signal and a noise suppressor which shifts a spurious signal of a predetermined order outside a loop bandwidth of the PLL. The phase-locked loop includes a loop filter, and the loop bandwidth is defined by a cutoff frequency of the loop filter or corresponds to a frequency range that lies between the frequency signal generated from the PLL and a cutoff frequency of the filter. The noise suppressor preferably includes a frequency divider in a feedback loop of the PLL and a controller which sets the frequency divider to a value which performs the spurious signal shift. The frequency divider may be a pulse-swallow divider and the controller may include a Sigma-Delta modulator. In addition to these features, the noise suppressor may include a reference signal modulator for fine tuning suppression of the spurious signals.
In accordance with another embodiment, the present invention provides a system for controlling a phase-locked loop comprising a divider which divides a frequency signal output from the PLL and a controller which sets the divider to a value which shifts a spurious noise signal of a predetermined order outside the loop bandwidth of the PLL. The loop bandwidth may be defined based on the cutoff frequency of a loop fitter and the divider value may be controlled to suppress virtually any order of spurious noise signals desired. The controller may also include a modulator for generating a modulated reference signal for fine tuning supression of the spurious signals.
BRIEF DESCWPTKW OF THE DRAWINGS
Fig. 1(a) is a diagram showing a related-art phase-locked loop circuit, and Fig. 1(b) is a diagram showing different types of mismatches that may occur in the phase and frequency detector and/or charge pump of the related-art phase-locked loop, which mismatches lead to the generation of spurious signals that degrade system performance.
Fig. 2 is a diagram showing the generation of a spurious noise signal in the related-art circuit of FIG. 1(a).
Fig. 3 is a diagram showing one embodiment of a phase-locked loop circuit in accordance with the present invention.
Rg. 4 is a diagram showing an example of how the system and method of the present invention may be implemented to shift spurious noise signals outside the loop bandwidth of a PLL to thereby enable them to be removed by a loop fitter.
Figs. 5(a) and 5(b) are graphs showing harmonics of an original reference frequency and a modulated reference frequency generated in accordance with one example of the present invention.
Fig. 6 is a diagram showing one embodiment of the reference modulator of the present invention.
Fig. 7 is a diagram showing another embodiment of the reference modulator of the present invention.
Figs. 8(a) - 8(g) are diagrams showing the manner in which signals are processed by each of the elements of the reference modulator shown in Fig. 7.
Fig. 9 is a diagram showing one embodiment of the reference modulator of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention includes various embodiments of a system and method for suppressing noise in a phase-locked loop circuit. In accordance with one embodiment, the system and method suppresses noise that results from mismatches relating to the charge pump and phase and frequency detector. This is accomplished using a Sigma-Delta modulator which controls a divider in a feedback path of the PLL so that spurious noise components are shifted outside the operating loop bandwidth of the circuit Other embodiments suppress noise by modulating a reference frequency signal input into the phase and frequency and detector. Still other embodiments suppress noise using a combination of the foregoing techniques. Through these embodiments, spurious noise components are shifted far away from the desired output frequency of the PLL so that they can be eliminated by a loop filter. As a result, a substantial improvement in signal-to-noise ratio and loop bandwidth may be realized along with a proportional reduction in phase noise and lock time.
Referring to Fig. 3, one embodiment of the system and method of the present invention includes a reference modulator 20 and a Sigma-Delta modulator 30 for controlling the output frequency of a phase-locked loop. The phase-locked loop is formed from a phase and frequency detector 22, a loop filter (e.g., a low-pass or bandpass filter) 23, a pulse-swallow frequency divider 24, and a voltage-controlled oscillator 25 for outputting a signal at a desired frequency fvco The pulse-swallow frequency divider includes a program counter 27 and swallow counter 28 which respectively assume values P and S under control of the Sigma-Delta modulator.
The Sigma-Defta modulator sets the values of the program and swallow counters based on parameters, NΣ and DΣ, in order to generate the desired output frequency fm. This output signal may be used to modulate or demodulate signals in a communication transceiver or to perform any one of a variety of other purposes. The values of P, S, NΣ and DΣ may be determined from the specific prescaler being used. Various prescalers and the manner in which they may be used to set the values of the counters are generally known to those skilled in the art. See, for example, the text RF MICROELECTRONICS, Chapter 8, by Behzad Razavi.
If left unconnected, the output frequency of the voltage-controlled oscillator will contain various types of noise, including spurious signals generated from mismatches relating to the phase and frequency detector and the charge pump. This situation is depicted in Fig. 2 where the frequency separation Af is so small that the spurious signals cannot be removed by the loop filter. The present invention removes this and other types of noise (including phase noise) by shifting the spurious signals far away from the output frequency f^ of the PLL. This is accomplished through adjustments made by the Sigma-Defta modulator, which adjustments are preferably performed in combination with a modulation of the reference signal of the PLL.
First, the reference modulator modulates the input reference signal fre,by an amount which
causes this signal to be multiplied by the value Had. . This results in the formation of a modulated
reference signal, (Equation Removed) , which is input into the phase and frequency detector. To effect this modulation, the values of NΣ, and DΣ are preferably selected to be integers by observing one or more of the following considerations:
1) The frequency range of the system. If the required frequency range is very narrow and only a few channels exist hi the range, only one reference modulator may be used. However, if the range is very wide, one reference modulator may not be sufficient to achieve a desired degree of spurious signal suppression. In this case, multiple reference modulators may be included and selectively chosen to achieve an optimal degree of suppression. Tables 2 and 3 (discussed in greater detail infra) include non-limiting example of the values of N^ and D^ which may be used to perform the reference signal modulation of the present invention. If the required frequency range does not include the frequency of 944.65 MHz or 1102.1 MHz, 8/9 modulation may be enough for suppression. But, if that frequency is included another modulation such as 5/6
may be used for the applicable channel. This multiple reference-modulator embodiment is discussed in greater detail below.
2) The desired spur level for the system.
3) The loop filter bandwidth, which may be explained as follows. The parameters of
the loop filter depend on the reference frequency. As the reference modulation changes the
reference dock, the loop filter parameters should be changed. If the difference between the
original reference clock and the modulated reference clock is small, the loop filter can be shared
for both the original clock and the modulated dock as long as system specifications such as phase
noise, spurious signal suppression, and lock time allows it. For example, if 8/9 modulation and 2/3
modulation for a channel shows the same spurious signal suppression, the 8/9 modulation may
be preferred because the 8/9 modulated reference signal is closer to the original reference
frequency than the 2/3 modulated reference signal.
4) The hardware complexity of the system. For example, while multiple modulation
ratios (3/4, 5/6,7/8, 8/9, etc.) may be acceptable for purposes of achieving a desired level of
spurious signal suppression, it may not be possible to achieve all the ratios given the hardware
in use. Thus, hardware may be one factor to consider when selecting a modulation ratio in
accordance with the present invention.
During the time the reference signal is modulated or some predetermined time before, the values defining the modulation ratio of the Stgma-Delta modulator, NΣ and DΣ are computed along with P and S which correspond to the values of the program and swallow counters. Together, these parameters along with parameter K of prescaier 29 determine the value the pulse-swallow frequency divider uses to divide the output frequency of the VCO. One way in which parameters NΣ, DΣ, P, and S may be calculated will now be discussed in greater detail.
The values of fico, R, K, and k are preferably determined at the system or architecture level to meet, for example, the requirements of a desired application. (The R value may be related to the design specification of the PLL (e.g., R = 1 if k = 19.2 MHz) and the K value may be related to the design of the prescaier.) The only unknown values therefore are P, S, NΣ, and DΣ
DΣ. This parameter may be determined in various ways. First, DΣ may be determined as a simple power of two, e.g., 210/212/213... In this case, as the denominator increases, hardware complexity also increases and the frequency resolution of the PLL increases. Thus, there is a trade off between precision and hardware complexity. Second, if the frequency resolution (or channel spacing) of the system is known, DΣ may be determined by the following equation:
DΣ = (fref R) / fch. For example, in the Korean CDMA system, fref= 19.2 MHz, R = 1, and fch = 10 kHz. Given these values, DΣ = 1920.
P. S.andNΣ. These parameters are integer values which satisfy the following relation: fvco = (fre R) * (K P + S + NΣ DΣ). If two or more consfrainte are added to this relation, the solution is unique. The first constraint is that 0 ≤S Second, the pulse-swallow frequency divider divides the output of the voltage-controlled oscillator f.xo by the value in Equation (1), so that the comparison frequency input into the phase
(Equation Removed) Since the modulated reference frequency fΣ is different from the unmodulated reference frequency fΣ, the parameters of the pulse-swallow frequency divider must be changed so that the signal input into the phase and frequency detector from the feedback loop matches the modulated reference frequency output from the reference modulator. Before being input into the phase and frequency detector, the modulated reference frequency f^ may be divided by the value R corresponding to an optional reference divider 31.
From Equation (1), it is dear that in order to achieve a desired output frequency signal (m (which, for example, may be a local osciator signal used in baseband signal recovery circuit of a communications transceiver), the output of the voltage-controiled oscillator must be divided by a value given by Equation (1) in the feedback loop. If the reference divider and prescaler counter values R and K are known for a given application, the remaining parameters (P, S, N) can be determined as explained above and in view of Equation (1) for a given input frequency and the VCO output frequency.

The output frequency of the PU_ may be expressed by the following equation:
In Equation (2), represents the integer part of the
(Equation Removed) desired frequency fm and the
(Equation Removed)
represents the fractional part
of this frequency. When mismatches occur in the PLL, spurious noise signals form at frequencies which coincide with the fractional part of the desired frequency f^ and harmonics of this frequency. In order to achieve the separation required to filter out all or a portion of these spurious signals, the present invention controls one or more parameters in the above equation.
Initially, the modulation ratio of the Sigma-Delta modulator is controlled to achieve a desired degree of frequency separation. This may be empirically understood with reference to the fractional part of Equation (2), which corresponds to the frequency offset (Af) between the desired frequency fm and the first-order spurious signals f^. (This offset may also exist between adjacent-orders of the spurious signals themselves.)
(Equation Removed) frequency offset (or separation distance between the spurious signals and the desired output frequency) becomes larger. Inclusion of the term in the fractional part of
Equation (2) thus ensures that spurious signals fv of a predetermined order are formed sufficiently far from the desired output frequency fm that they can be removed by loop filter 23 along the signal path. This may be achieved, for example, by making the fractional part in Equation (2) and more specifically the ratio of NΣ and DΣ relatively large. This affects
the values of P and S which, in turn, ultimately leads to an adjustment of the value of the pulse-swallow feedback divider of the PLL
To achieve complete noise succession, the fractional part of Equation (2) is set large enough to ensure that the first-order spurious signals are shifted below the cutoff frequency of the loop filter. If desired, however, the fractional part may be set to other proper values to filter out higher-order spurious signals. White a lesser degree of noise suppression is realized in this case, oflier system requirements may be met, thereby making the present invention a suitable solution.
Fig. 4 shows how adjusting the values of NΣ and DΣ can lead to suppression of spurious noise signals in the output of the PLL. In this illustrative example, fm corresponds to the desired output frequency of the PLL, f corresponds to the cutoff frequency of the loop filter, and the loop bandwidth corresponds to the difference between fm and fcMf. In accordance with the presentinventkxi, the fractional part of Equation (2) and particularly the ratio of NΣ and DΣ is computed to be sufficiently large to shift the spurious noise signals fspv fsp» • • fst* outside the loop bandwidth and thus in this case below cutoff frequency f^ where they can be removed by the loop filter. This shift is shown by frequency offset Af.
The ratio of NΣ and DΣ of reference modulator 20 may be controlled to further adjust the degree of separation. More specifically, while this reference modulator is considered to be an optional feature of the present invention (e.g., the frequency separation required for spurious noise suppression may be accomplished solely by adjusting the modulation ratio formed between NΣ and DΣ), the ratio of NΣ and DΣ may be controlled as a way of fine tuning the spurious signal shift performed in the fractional part of Equation (2). The values of NΣ and 0Σ are preferably determined based on the design of the reference modulator.
Table 1 provides examples of values which when input into Equation (2) generate a frequency separation Af sufficient to shift spurious noise signals outside the loop bandwidth of the PLL. These values are reflected in Fig. 4 to illustrate the superior performance of the invention.
(T able Removed)Tabte-1
In Table 1, NΣ and DΣ values are set to 11817 and 15744 respectively and the modulation ratio of the reference signal modulator is 8/9. Plugging these values into Equation (2), the output frequency fm of the PLL is calculated to be 905.29 MHz. The value corresponding to the fractional part of this equation reveals the superior performance of the present invention for this example:
As shown by Equation (3), spurious noise signals produced from mismatches in the PLL will appear at frequencies which coincide with the fractional part of Equation (2), which . is computed to be 1 3. 1 3 MHz. The frequency separation Af between the output frequency and the first-order spurious noise signal fv1 will therefore be 6.55 MHz. (This number is obtained by subtracting 13.13 MHz from the frequency of the modulated input reference signal (19.68 * 8/9)). Using these values, the Sigma-Delta modulator shifts the first-order spurious signals outside the loop bandwidth of the PLL, thereby allowing the cutoff frequency /^of the loop filter to eliminate these and higher-order noise signals from the output frequency. While the modulation ratio of 8/9 is used in this example and provides for fine resolution adjustment, it can be seen that an even wider frequency separation may be achieved with other reference modulating ratios.
In the foregoing example, the cutoff frequency and/or the loop bandwidth may be determined based on the specific application requirements of the system including requirements for phase noise and spurious signal suppression. As shown, a greater suppression of the spurious signal fv occurs by the loop filter as the frequency offset (Af) increases from the carrier fm increases. White optional, the reference modulation may advantageously be used to increase this frequency offset
Also, in the foregoing example, the frequency separation was achieved at least in part by setting the modulation ratio of the Sigma-Delta modulator to a relatively large value.
For comparison purposes, it is noted that a small value of this ratio would not be able to
and the P and S values are 11 and 2 respectively, then the resulting frequency separation would be 1 0 kHz for the same values of K and f^ using an umodulated reference frequency. This separation would in most applications He well within the loop bandwidth of the PLL and thus would not be able to be suppressed by the loop fitter.
Additionally or alternatively, in controlling the values of the Sigma-Delta modulator the numerator Nu may be' adjusted to be far away from the sub-harmonics of the denominator Dza. This means, for example, that if the ratio of the numerator and
denominator — — of the Sigma-Defta modulator is near (Equation Removed)
reference modulation can reduce or eliminate the spurious signals.
The present invention thus effectively suppresses noise in a frequency generator such as a PLL in a way that substantially improves signal-to-noise ratio. This is evident by comparing the present invention to other circuits. For example, in the related-art system of Fig. 1(a), the frequency separation between the spurious noise signal and the PLL output frequency is equal to 1 0 kHz, which is shown to lie within the loop bandwidth of the circuit. (See Fig. 2). Because the spurious signal lies within this bandwidth, the loop filter of the Fig. 1 (a) PLL will not be able to remove the spurious noise signal from the output frequency. As a result, the output of this circuit will have a tower signal-to-noise ratio than desired by many applications.
In contrast, by setting at least one of the N^ and D^ parameters to appropriate values based on the loop bandwidth of tie PLL and then optionally modulating the input
reference frequency by to. perform fine tuning adjustment, the present invention
ensures that spurious noise generated from loop mismatches forms far away from the output frequency of the PLL, thereby enabling their suppression by the loop filter.
In addition to achieving greater noise suppression, the system of the present invention is able to achieve faster lock times white concurrently using a wider loop bandwidth compared with other systems which have been proposed. This may be understood by realizing that PLL lock time is inversely proportional to loop bandwidth. Operating with a wider loop bandwidth will therefore allow the present invention to achieve
reduced lock times compared with other PLL circuits, while simultaneously achieving an improved level of spurious signal suppression. All of these advantages translate into improved signal-to-noise ratio and thus a higher quality communications transicever.
Modulation of the reference signal may be accomplished in a variety of ways. Preferably, the refiefence frequency f^ is modulated to ensure that f^ is not close to the harmonics of the original reference frequency f^. Performing modulation in this manner is desirable in order to avoid the possibility of having spurious noise signals reappear in the output of PLL, in spite of the modulation performed by the Sigma-Delta modulator. This may be understood with reference to the following example.
Figs. 5{a) and 5(b) are graphs respectively showing harmonics of an original reference frequency and a modulated reference frequency generated in accordance with one example of the present invention. In Fig. 5(a), harmonics of the original reference frequencare shown as (Equation Removed)
and so on. In Fig. 5(b), the modulated reference signal is generated based on a modulation ratio of
Harmonics of the modulated input reference frequency therefore appear at frequencies of (Equation Removed)
In this example, N is assumed to be an integer and preferably a multiple of 6, and a zone where the harmonics of the modulated reference frequency and original reference signal are coincident are shown by X. In this zone, the invention may prove to be ineffective because the modulated reference frequency may not be able to suppress spurious signals in the output of the PLL. These principles may serve as a basis for defining the operating range of the Sigma-Delta controlled PLL of the present invention. More specifically, as shown in Figs. 5(a) and 5{b), the modulated reference frequency may be used as the comparison frequency input into the phase and frequency detector, instead of the original reference frequency, until harmonics of toe modulated reference frequency become equal to the harmonics of the original reference frequency.
If no restriction on chip area exists, various values of N^ and 0,^ may be used for a given frequency channel. For example, an N^/)^ of 5/6 may be desirable to effect spurious signal suppression for one channel but an N^D^ of 8/9 may be desirable for another channel. Also, for any given channel both modulation ratios may be acceptable. By changing the value of NMIJDmaai a variety of acceptable frequency offsets may be achieved
for purposes of spurious signal suppression. The one that is most compatible to the system (e.g., given hardware complexity) may be selected.
Fig. 6 shows one type of reference modulator of the present invention which can achieve the flexibility discussed above. This modulator is formed from two reference modulators 51 and 52 and a selector 53 may be included to select the appropriate modulation ratio N^/D,^ for the applicable channel. The first modulator has a modulation ratio of 5/6 and the second modulator a ratio of 8/9. While two modulators are shown, those skilled in the art can appreciate that the reference modulator of the present invention may include more than two modualtors, e.g., one modulator may be provided for each channel or group of channels in Die communications system. In this case, each modulator may have a modulation ratio selected specifically, and preferably optimally, for that channel or channel group. For channels which have no spurious tones, the reference modulator may be omitted or circumscribed and the reference clock may be fed directly to the internal PLL block.
Fig. 7 shows another way in which the reference modulator of the present invention may be constructed to produce these results. This modulator includes a first duty cycle corrector 70, a frequency doubter 71, a second duty cycle corrector 72, a fractional divider 73, a third duty cycle corrector 74, and anotier fractional divider 75. The fractional dividers are set to multiple their input signals by 2/3. Those skilled in the art can appreciate, however, that other fractional values may be used if desired.
Figs. 8(a) - 8(g) are diagrams showing the manner in which signals are processed by each of the elements of the reference modulator shown in Fig. 7. Fig. 8(a) shows the original reference frequency f^input Into the reference modulator. Fig. 8(b) shows that the first duty cycle corrector processes the original reference to produce a clean signal by removing sub-harmonic components therefrom. Fig. 8{c) shows that the frequency doubter doubles the frequency of the signal output from the first duty cycle corrector. This results in cutting the period of the signal in half. Fig. 8(d) shows that the second duty cycle corrector deans up the output of the frequency doubler by removing sub-harmonics. Fig. 8(e) shows that the signal output from the second duty cycle corrector is multiplied by a predetermined fraction, which in this example is 2/3.
Fig. 8(f) shows that the third duty cycle corrector cleans up the output of the first fractional divider by removing sub-harmonics. This causes the period of the signal to be increased by an amount commensurate with the division performed by the first fractional
divider.
Fig. 8{g) shows that the signal output from the third duty cycle corrector is multiplied by a predetermined fraction, which in this example is also 2/3. The result is to produce a modulated reference frequency. Once ttiis signal is processed to remove harmonics, the final modulated reference signal is produced whose period is increased by an amount commensurate with the division performed by the second fractional divider.
In the foregoing embodiment of the reference modulator, the numerator of the reference modulator should be different from one in order to increase operating range of the PLL while simultaneously preventing a reformation of the spurious signals. In fact, it may be preferable to usea high value of the numerator. The fractional divider and frequency doubler may be adapted to generate a numerator of .this type.
For instance, in the examjpte previously discussed one frequency doubler and two
fractional .dividers were used to generate the modulated reference signal, equal to
fm "
to generate the modulated reference frequency, with the same fraction of 2/3 used for both dividers. While these values may be preferable, those skiHed in the art can appreciate that any number of the frequency multiplication and division circuits may be used, as long as a
desired fractional division ratio — MBL js achieved.
Fig. 9 shows another way in which Uie reference frequency modulator of the present invention may be constructed. This modulator includes a number of frequency dividers 80 connected to a mixer 81 . The frequency dividers multiply the original reference frequency f^, by values which, when input into the mixer, generate the desired fractional frequency. For
example, the frequency dividers may outout signals equal to — frtf . The mixer will then
output a signal equal to -frtf . After mixing, unwanted harmonics generated from the mixer
are filtered out using a bandpass filter 82. A limiter 83 is then used to produce the modulated reference frequency in the form of a digital pulse.
Example Table 2 shows exemplary values that may be used in accordance with the present
(Equation Removed) invention. To achieve an acceptable level of spur reduction, the ratio is selected to be
large to shift spurious signals outside the cutoff frequency. Also, the reference frequency is modulated by an —sasi ratio which ensures that the harmonics of is not dose to the
(T able Removed)
Sigma-Delta modulator values of Nj^ and D^. The worst case spur is shown to exist between 905.29 MHz and 1161.13 MHz. (The N and D columns make up the N/D ratio which corresponds to the worst-case spur, e.g., N/D = 1/1968. The ratio of N/D = 1967/1968 is not induded because it has the same characteristics shown in the Table 2.) The worst-case spur is near at a multiple of the reference dock frequency. They are listed from 46 f^ to 59 ^ as an example. Also, an 8/9 reference modulation is used as an example. Note that
the Sigma-Delta modulation ratio -sss- ratio has a circular relation according to fm or
Aiew
multiples of the reference clock as in Fig. 5, e.g., the ratio of (Equation Removed)
.... 11817/15744,13785/15744 is repeated.
Not all the values of in Table 2 are optimal. For example, in the case where fM =
944.65, the Sigma-Delta modulation ratio —. This produces a frequency
separation of 10 kHz when a reference modulation rato —(Equation Removed)
separation may in some instances prove to be Insufficient for purposes of achieving spurious signal suppression. In this case, the reference signal modulation ratio may be changed to produce a frequency separation sufficient to achieve an acceptable level of spurious signal

supression. In the example under consideration, this may be accomplished by setting

= 5/6. A comparison of the results obtained for these modulation ratios is set forth in Table 3.
(T able Removed)*
Tables
Using the modulation ratio of 5/6 instead of 8/9, the following frequency offset is obtained:
k * (N»AJ * (N.JD.J = 19.68*(5/6}*(5910/9840) = 9.85 MHz. This offset is considerably larger than the 10 kHz offset obtained using the 8/9 modulation ratio and in fact large enough to shift spurious noise outside the cutoff frequency of the loop filter in this
example, thereby achieving spurious signal suppression. From this example, it is therefore evident that at least one and preferably both of (Equation Removed) may be controlled to
suppress spurious signals to thereby improve signal-to-noise ratio in a communications receiver.
Other modifications and variations to the invention wiU be apparent to those skilled in the art from the foregoing disclosure. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.

We claim:-
1. A frequency generator, comprising:
a phase-locked loop (22, 23, 24, 25) (herein after referred to as the PLL) which generates a frequency signal based on a reference signal; and
a noise suppressor which shifts a spurious signal of a predetermined order outside a loop bandwidth of the PLL, wherein the noise suppressor includes a frequency divider (24) in a feedback loop of the PLL, and a controller (30) which sets the frequency divider to a value Which shifts the spurious signal of said predetermined order outside the loop bandwidth of the PLL, and
wherein the frequency divider (24) have a swallow counter (28) and a program counter (27) and wherein values for the swallow and program counters are controlled based on a modulation ratio of a Sigma-Delta modulator (30), said values for the swallow and program counters being controlled to generate said values which shifts the spurious signal of said predetermined order outside the loop bandwidth of the PLL.
2. The frequency generator as claimed in claim 1, wherein the PLL have a loop filter (23) and the loop bandwidth is defined by a cutoff frequency of the loop filter.
3. The frequency generator as claimed in claim 1, wherein said values of the
swallow and program counters (27, 28) are controlled to shift a first-order spurious signal outside the loop bandwidth of the PLL.
4. The frequency generator as claimed in claim 1, wherein the PLL generates
the frequency signal (fveo) in accordance with the equation 1 described in
description
Where fref is the reference signal, R is a value of a reference signal divider (20), P is the value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio of the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24).
5. The frequency generator as claimed in claim 1 wherein the PLL generates
the frequency signal in accordance with the equation 2 as described in the
description.
Where fref is the reference signal, R is a value of a reference signal divider (20), Nmod and Dmod define a modulation ratio for the reference signal, P is the value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio qf the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24).
6. The frequency generator as claimed in claim 1, wherein the modulated
reference signal is used as a comparison signal for the PLL as long as
harmonics of the modulated reference signal are not coincident with harmonics of the unmodulated reference signal.
7. The frequency generator as claimed In claim 1, comprising:
a frequency shifter (20) which shifts the reference signal to a fractional fixed value for input into a phase/frequency detector (22) of the PLL, said fractional fixed value further shifting the spurious signal of said predetermined order.
8. A noise suppression method employed an apparatus as claimed in claim 1,
comprising generating a frequency signal from a phase-locked loop (22, 23, 24,
25) (hereinafter referred to as the PLL) based on a reference signal; and
removing noise from the frequency signal by setting a frequency divider (24) in a feedback loop of the PLL to a value which shifts a spurious signal of a predetermined order outside a loop bandwidth of the PLL, wherein setting the frequency divider (24) includes:
adjusting at least one of a swallow counter (28) and a program counter (27) in the frequency divider (24) to a value which shifts the spurious signal of a said predetermined order outside the loop bandwidth of the PLL.
9. The method as claimed in claim 8, wherein the loop bandwidth Is defined by
a cutoff frequency of a loop filter (23) in the PLL.
10. The method as claimed in claim 8, wherein the loop bandwidth corresponds to a frequency range that lies between the frequency signal generated from the PLL and a cutoff frequency of a loop filter (23) in the PLL.
11. The method as claimed in claim 8, wherein said noise is removed by adjusting at least one of the swallow counter (28) and a program counter (27) to a value which shifts a first-order spurious signal outside the loop bandwidth of the PLL.
12. The method as claimed in claim 8, wherein at least one of the swallow counter (28) and program counter (27) is set by a Sigma-Delta modulator (30).
13. The method as claimed in claim 12, comprising computing a modulation ratio of the Sigma-Delta modulator (30) based on the loop bandwidth of the PLL; and
setting the value of at least one of the swallow counter (27) and program counter (28) base on the modulation ratio computed for the Sigma-Delta modulator (30).
14. The method as claimed in claim 8, wherein the spurious signal is generated by a mismatch relating to at least one of a phase and frequency detected and a charge pump of the PLL.
15. The method as claimed in claim 8, wherein a value for at least one of the swallow and program counters (27, 28) is controlled based on a modulation ratio of a Sigma-Delta modulator (30).
16. The method as claimed in claim 15, wherein a numerator of the modulation ratio (NΣ) is at least 50% of a denominator of the modulation ratio (DΣ).
17. The method as claimed in claim 16, further comprising:
modulating the reference signal into the PLL with a reference modulator (20), wherein the reference modulator has a modulation ratio (Nmod/Dmod) such that Nmod is at least 50% of Dmod-
18. The method as claimed in claim 8, wherein the spurious signal is generated
from a mismatch in at least one of a charge pump and phase/frequency
detector (22) in the PLL, wherein the mismatch in the charge pump includes a
mismatch between UP and DOWN current sources, wherein the spurious signal
is generated from a mismatch between UP and DOWN signal paths in the
phase/frequency detector (22).

19. The method as claimed in claim 8, wherein the value of the frequency divider (24) is set based on a modulation ratio of a Sigma-Delta modulator (30) for removing the spurious signal.
20. The method as claimed in claim 8, further comprising:
shifting the reference signal to a fractional fixed value for input into a phase/frequency detector (22) of the PLL, said fractional fixed value further shifting the spurious signal of said predetermined order.
21. The method as claimed in claim 8, wherein the swallow counter and program counter (27, 28) are both adjusted to shift the spurious signal of said predetermined order outside the loop bandwidth of the PLL.
22. The method as claimed in claim 21, wherein the values for the swallow and program counters (27, 28) are controlled based on the modulation ratio of the Sigma-Delta modulator (30), said values for the swallow and program counters (27-28) being controlled to generate said value which shifts the spurious signal of said predetermined order outside the loop bandwidth of the PLL.
23. The method as claimed in claim 22, wherein the frequency signal of the PLL (fvco) is generated in accordance with the equation 2 as described in the description,
Where fref is the reference signal, R is a value of a reference signal divider (20), Nmod and Dmod define a modulation ratio for the reference signal, P is the
value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio of the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24).
24. The method as claimed in claim 22, further comprising:
modulating the reference signal input into the PLL.
25. The method as claimed in claim 24, wherein the frequency signal of the PLL
(fvco) is generated in accordance with the equation 1 as described in the
description
Where fret is the reference signal, R is a value of a reference signal divider, P is the value of the program counter (27), S is the value of the swallow counter (28), NΣ and DΣ is the modulation ratio of the Sigma-Delta modulator (30), and K is the value of the prescaler (29) in the pulse swallow frequency divider (24).
26. The method as claimed in claim 24, comprising using the modulated reference signal as a comparison signal for the PLL as long as harmonics of the modulated reference signal and the unmodulated reference signal are not coincident.
27. A noise suppression method substantially as herein described with reference to the foregoing description and the accompanying drawings.
28. A method for suppressing noise in a frequency generator substantially as herein described with reference to the foregoing description, tables and the accompanying drawings.
29. A frequency generator substantially as herein described with reference to the foregoing description, tables and the accompanying drawings.

Documents:

2198-delnp-2005-abstract.pdf

2198-delnp-2005-assignment.pdf

2198-delnp-2005-claims.pdf

2198-delnp-2005-complete specification (as,files).pdf

2198-delnp-2005-complete specification (granted).pdf

2198-delnp-2005-correspondence-others.pdf

2198-delnp-2005-correspondence-po.pdf

2198-delnp-2005-description (complete).pdf

2198-delnp-2005-drawings.pdf

2198-delnp-2005-form-1.pdf

2198-delnp-2005-form-13.pdf

2198-delnp-2005-form-18.pdf

2198-delnp-2005-form-2.pdf

2198-delnp-2005-form-3.pdf

2198-delnp-2005-form-5.pdf

2198-delnp-2005-gpa.pdf

2198-delnp-2005-pct-101.pdf

2198-delnp-2005-pct-105.pdf

2198-delnp-2005-pct-110.pdf

2198-delnp-2005-pct-210.pdf

2198-delnp-2005-pct-304.pdf

2198-delnp-2005-pct-318.pdf

2198-delnp-2005-petition-137.pdf

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Patent Number

255943

Indian Patent Application Number

2198/DELNP/2005

PG Journal Number

15/2013

Publication Date

12-Apr-2013

Grant Date

08-Apr-2013

Date of Filing

24-May-2005

Name of Patentee

GCT SEMICONDUCTOR,INC.

Applicant Address

2121 RINGWOOD AVENUE,SAN JOSE,CA 95131,U.S.A

Inventors:

#	Inventor's Name	Inventor's Address
1	AHN YOUNGHO	934-15 SHINJUNG 5 DONG,YANGCHEON KU,SEOUL ,REPUBLIC OF KOREA
2	SONG EUNSEOK	IMKWANG APT 15-405,BANGBAE-DONG,SEOCHO-KU,SEOUL,RIPUBLIC OF KOREA
3	KOO YIDO	BANPO JOOGONG APT 225-307,BANPO 2 DONG,SEOCHO GU,SEOUL REPUBLIC OF KOREA
4	LEE JEONG-WOO	SAMHWAN APT 101-204,SHINKIL-7 DONG,YOUNGDEUNG-POGU,SEOUL,REPUBLIC OF KOREA
5	PARK JOONBAE	SAMPOONG APT.8-303,SEOCHO-DONG,SEOCHO-GU,SEOUL,REPUBLIC OF KOREA
6	LEE KYEONGHO	SAMSUNG-SAN JOOKONG APT.309-901,SHINLIM-10 DONG,KWANAK GU,SEOUL,REPUBLIC OF KOREA

PCT International Classification Number

H03L 7/06

PCT International Application Number

PCT/US2003/033709

PCT International Filing date

2003-10-23

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	60/421,060	2002-10-25	U.S.A.
2	10/689,986	2003-10-22	U.S.A.