Title of Invention

"A PROGRAMMABLE GLITCH FILTER"

Abstract

This invention relates to a programmable glitch filter comprising a storage means for storing a current state, which is the output of the said filter, the output of said storage means is connected to one input of a state comparator and the other input of the said state comparator is connected to the input signal, a programmable clock delay means for any required duration which is independent of technology of implementation, is connected between the said state comparator and said storage means, the arrangement being such that the input signal is stored as the new current state in the said storage means only if the input signal changes and then remains unchanged for the programmed duration. It also includes a method for filtering glitches.

Full Text

A PROGRAMMABLE GLITCH FILTER This invention relates to a programmable glitch filter. BACKGROUND: All the digital designs use the binary signal levels logic '0' and logic '1'. These signals are also referred as logic LOW and logic HIGH respectively. A glitch is an unwanted transition in the logic level (either LOW or HIGH). This effects the performance of any digital circuit since the storage elements (Flip Flops) change their logic state on either a LOW to HIGH or HIGH to LOW logic transition. The glitch is shown in figure 1. The most conventional method of suppressing the glitches in PCBs is by using RC circuit.The glitch suppression mechanism by RC circuit is discussed in the following paragraphs The RC circuit is shown in figure 2A, the step input to the RC circuit (at point X) is shown in figure 2B. The response of the circuit is illustrated in figure 2C. Waveform at the output of the buffer (at Z) is shown in figure 2D. When a step input (shown in figure 2B) is given to a RC circuit (at X of figure 2A), the response of the circuit (at Y is shown in figure 2-C) can be mathematically represented by equation EQU-1. (Equation Removed) Where t is time in seconds R is resistance in ohms and C is capacitance in farads. The glitch is suppression technique by RC circuit can be employed both for positive and negative glitches. The glitch suppression mechanism for positive glitches is shown in figures 3A to 3C. Figures 4A to 4C depict the glitch suppression mechanism for negative glitches. The values of R and C are to be selected such that for maximum glitch width the response of RC circuit doesn't cross the threshold of the buffer. The waveform with positive glitch is shown in figure 3A. This wave form is input to the RC circuit, (point X in figure 2A). The response of RC circuit to the input waveform (at Y in figure 2A) is shown in figure 3B. The glitch free signal (at Z in figure 2A) is shown in figure 3C. The waveform with negative glitch is shown in figure 4A. This wave form is input to the RC circuit, (point X in figure 2A). The response of RC circuit to the input waveform (at Y in figure 2A) is shown in figure 3B. The glitch free signal (at Z in figure 2A) is shown in figure 4C. The glitch suppression by delay elements is the most widely used glitch suppression for ASIC applications. A large number of patents exist on glitch suppression using delay elements. A typical such glitch suppression is discussed below using figures from the Japanese patent number 4287512. The glitch suppression mechanism for positive glitches is shown in figure 6A to 6E. The glitch suppression mechanism for negative glitches is shown in figures 7A to 7E. The circuit essentially uses a SR (Set Reset) Flip-flop. The SR flip-flop is realized using two nand gates NAND1 and NAND2. The component DELBUF acts as a delay buffer. The delay buffer delays the input signal (signal at A in figure 5) by a fixed amount. The delay buffer is selected such that the delay inserted by it is equal to maximum glitch width that is to be suppressed. Figure 6A shows a waveform having a positive glitch. Figure 6B shows the output of delay buffer. The wave forms at S & R inputs of SR flip-flop are shown in figures 6C and 6D respectively. The output glitch free waveform is shown in figure 6E Figure 7A shows a waveform having a negative glitch. Figure 7B shows the output of delay buffer. The wave forms at S & R inputs of SR flip-flop are shown in figures 7C and 7D respectively. The output glitch free waveform is shown in figure 7E An existing prior art on programmable glitch filter is shown in figure 8 from US patent no. 5,289,060. The circuit consists of a SR flip-flop. The output of the flip-flop 'Q' is set to logic '1' only when S is '1' and R is '0'. 'Q' is set to logic '0' only when 'S' is at '0' and 'R' is at T. When 'S' and 'R' are at '0' same logic state is maintained. A logic '1' on 'S' and 'R' is not allowed. A programmable delay buffer (represented as "PROGRAMMABLE DELAY" in the figure above) provides delay which is programmable to a pre-determined value. This block delays the input signal at 'A' to a programmable value. The incrementally delayed outputs of the programmable delay are fed to AND gate and (BAND) Bubbled AND gate (The inputs of this logic element are first inverted and then logically ANDed). The output of AND gate is '1' only when all the inputs are at logic '1'. The output of BAND gate is at logic '1' only when all the inputs are at logic '0'. The glitch suppression mechanism for positive pulses is shown in figures 9A to 9E. Figure 9A shows the waveform having positive glitches. Figure 9B shows the waveform after maximum programmed delay at In. The output of AND gate is shown in figure 9C and output of BAND gate is shown in figure 9D. The glitch free output present at 'Q of SR flip-flop is shown in figure 9E. The glitch suppression mechanism for negative pulses is shown in figures 10A to 10E. Figure 10A shows the waveform having negative glitches. Figure 10B shows the waveform after maximum programmed delay at In. The output of AND gate is shown in figure IOC and output of BAND gate is shown in figure 10D. The glitch free output present at 'Q of SR flip-flop is shown in figure 10E. All the existing prior arts use a delay element to delay the signal. The delay signal and the original signal are compared. The output of glitch filter is assigned to the input only when both the inputs have same value. The delay elements are implemented using buffers, the existing glitch suppression techniques work fine for glitches of small pulse widths (typically ~ tens of ns). If the glitch width is of the order of few hundreds of microseconds or few milliseconds, the glitch suppression with the existing techniques become very difficult. This is mainly because realizing a delay element to delay the signal by few hundreds of microseconds is very difficult. The object of this invention is to obviate the above drawbacks and provide a programmable glitch filter, which can suppress glitch width of the order of few hundreds of microseconds or few milliseconds. To achieve said objective this invention provides a programmable glitch filter comprising: a storage means for storing a current state, which is the output of the said filter, the output of said storage means is connected to one input of a state comparator and the other input of the said state comparator is connected to the input signal, a programmable clock delay means for any required duration which is independent of technology of implementation, is connected between the said state comparator and said storage means, the arrangement being such that the input signal is stored as the new current state in the said storage means only if the input signal changes and then remains unchanged for the programmed duration. The said means for providing a programmable clock delay comprising. a counter for counting clock pulses to provide a time delay, the control input of the said counter being connected to the output of the said state comparator, the output of the said counter is connected to one input of a digital delay comparator, the other input of the said delay comparator receives a digital value corresponding to the maximum glitch width to be filtered, the output of the said delay comparator is connected to the input of the said storage means. The counter is enabled only if the input to the said glitch filter is not equal to the output of said storage means and the said counter is initialized when the input of the said glitch filter is equal to the output of said storage means A multiplexer is provided at the output of the said storage means, which also receives the input signal at its other input and the programmable digital value for the desired maximum glitch width at its control input, the arrangement being such that when the programmed digital value is zero, the input signal is fed to the output of the multiplexer and when the value is not zero, the storage means output is fed to the output of the multiplexer. The number of bits used for the said counter and said digital delay comparator depends upon the desired range of programmable digital values for maximum glitch width. This invention further relates to a mehtod for filtering glitches comprising: storing a current state, which is the final output, comparing the said current state with the input signal, enabling a programmable delay whenever the input signal is different from the stored current state and initializing the programmable delay whenever the input signal is same as the stored current state, making the stored current state equal to the input signal if the programmed delay is complete. The programmable delay is obtained by: counting clock pulses comparing the counted clock pulses with a digital value corresponding to the maximum glitch width, generating a signal indicating completion of programmed delay when the counted clock pulses become equal to the said digital value. The counting is enabled only if the input signal is not equal to the stored output state and counting is initialized whenever the input signal is equal to the stored output state. The filtering of glitches is enabled only when the digital value for desired glitch width is non-zero and is disabled when the digital value is zero. The invention will now be described with reference to the accompanying drawings: Fig. 1 shows the glitch. Fig. 2a shows the conventional RC circuit for suppression of glitches. Figs. 2b, 2c and 2d show the step input in the said RC circuit, response of the RC circuit and the wave form at the output of the buffer. Figs. 3a to 3c show glitch suppression mechanism for positive glitches for said RC circuits . Fig. 4a to 4c depict the glitch suppression mechanism for negative glitches for said RC circuits. Fig. 5 shows the known glitch suppression using delay elements for ASIC application described in Japanese patent no. 4287512. Fig. 6a to 6e shows the glitch suppression mechanism for positive glitches for said ASIC application. Fig 7a to 7e show the glitch suppression mechanism for negative glitches for said ASIC application. Fig. 8 shows the programmable glitch filter described in US patent 5,289,060. Fig. 9a to 9e shiows the glitch suppression mechanism for positive pulses in respect of programmable glitch filter described in US patent no. 5,289,060 Figs 10a to lOe show the glitch suppression mechanism for the negative pulses Fig. 11 shows the block diagram of the programmable glitch filter, according to our invention Fig. 12 shows the schematic for anti-glitch filter, according to our invention Fog. 13 shows the schematic for state comparator, according to our invention Fig. 14 shows programmable delay, according to our invention Fig. 15 shows the schematic for counter, according to our invention Fig. 16 shows the schematic for digital delay comparator, according to our invention Fig. 17 shows the schematic for storage element, according to our invention Referring to drawings figures 1 to l0e describe the prior art, as explained in the background and figures 11 to 17 describe the invention according to this invention.. Referring to figure 11. state comparator (SC) receives the input signal at one input and the current outpur state from the output of storage element (SE) at its other input. Whenever the input signal is different from the current stored state, the output of the state comparator (SC) activates 'counter control' to enable programmable clock delay circuit (PCD), which begins counting clock pulses received at its clock input. The programmable clock delay circuit (PCD) also receives the required value of maximum glitch width at its programme input. If the 'counter control' remains active for a number of clock pulses equal to the required value of maximum glitch width, the change state' output from the programmable clock delay circuit (PCD) is activated. This causes the storage element (SE) to change its state to the value of the input signal, which also changes the output of the filter. At this point the current stored state becomes equal to the input signal, which causes state comparator (SC) to deactivate 'counter control' and thereby initialize programmable delay circuit (PCD). If the input signal does not remain stable for the duration of the number of clock pulses equal to the required value of maximum glitch width, 'counter control' is deactivated by state comparator (SC) to initialize programmable clock delay circuit (PCD) before 'change state' can become active. Hence, a glitch (which is a change of state before the programmed value of delay) will not cause the storage element (SE) to change its state and therefore, the output remains as such. In figure 12, multiplexer (M) is added at the output of the storage element (SE). the multiplexer (M) receives the output of the storage element (SE) at one of its inputs while the other input receives the input signal. The control input of the multiplexer (M) is connected to the desired value of maximum glitch width. If the desired value of maximum glitch width is zero, the multiplexer (M) connects the input signal directly to the output of the filter, thereby suppressing the glitch filtering. If however, the maximum glitch width value is not zero, the multiplexer (M) connects the output of storage element (SE) to the output of the filter and thereby enabling the filter operation. Figure 13 shows the state comparator (SC). The circuit is the simple two-input exclusive-or gate (XOR), which receives the input signal and the stored current state at its two inputs and generates the 'counter control' at its output whenever the two inputs are unequal. Figure 14 shows the internal structure of the programmable clock delay circuit (PCD). Digital counter (C) receives the 'counter control' signal at its enable input and a clock signal at its clock input and reset signal at its reset input. The digital value representing the current count value of the counter is connected to one input of digital delay comparator (DDC) while the digital value corresponding to the clock count for desired maximum glitch width is received at the other input of the said digital delay comparator (DDC). Then the counter control' signal is activated, the counter is enabled and counts clock pulses received at its clock input. When the count value becomes equal to the corresponding count for desired maximum glitch width, the digital delay-comparator (DDC) activates the 'change state' signal. Figure 15 shows the internal structure of the digital counter (C). • When 'counter control' is at logic '0' output of and gates ANO to AN7 is at logic '0' and 'count value' is loaded with 0x00 on every rising clock edge. • When 'countercontrol' is at logic T output of adder is shifted into the into D-flip-flops DFO to DF7 on every rising clock edge. • The adder increments the current 'count value' by one. This is done by feeding the count value and '0x01' to the inputs of the adder. • The 'count value +1' is assigned to the count value on every rising clock edge. Hence the counter increments the count value on every rising clock edge when 'countercontrol' is at logic '1' and the 'count value' is loaded with 0x00 on every rising clock edge when 'countercontrol' is at logic '0'. Figure 16 shows the internal structure of the digital delay comparator (DDC). The bit 0 of'countvalue' and 'noisesuppressionwidth' is fed to XNOR0, bit 1 to XNOR1 and so on. 'changestate' is at logic ' 1' only when 'count value' and 'noisesuppressionwidth' are equal else it is at logic '0'. Figure 17 shows the internal structure of the storage element (SE). The output of DFF toggles on rising clock edge only when 'change state' is at logic '1' else the same logic state is maintained at the output of DFF. The typical working of the programmable glitch suppression filter is shown in figure 18. In the example, the value of'noisesuppression width' is assumed to be 4, this suppresses a glitch whose maximum width is 5 clock cycles. When there is a glitch of 3 clock cycles, the counter control is HIGH for three cycles and count is counted up to a value of 3. When the glitch disappears the 'countercontrol' goes to logic '0' and 'count value' is loaded with 0. The output state remains unchanged. When the data changes (for the second time in the ligure above), the 'counter control" goes to logic 1. The count value increments on every rising clock edge. When the count value reaches 4, the 'change state" is also forced to logic "1". This toggles the logic state of data out". The 'data out" now changes to logic '0' Since the logic state on 'data in' and 'data out' is same 'counter control" is forced to logic '0' and the 'counter value' is loaded with 0 on every rising clock-edge. Figure 19 shows an example for a negative glitch. The circuit operates exactly the same way as for the positive glitch. It may be noted that the functioning of the programmable glitch filter is as follows. • The filter requires a fast clock (typically least 5 times faster than the signal transitions). • When the filter is initialized on power on all the internal variables 'counter control', 'change state', and 'data out' are set to zero. • To enable the filtering the 'noisesuppression width ' (which is a binary data bus) must have a value other than zero. • When the 'noise suppression width ' is zero 'datain' is fed to 'filtered data out' and filtering is disabled. • The storage element has a state machine inside it which changes the logic state of data out only when 'changestate' is '1'. • The programmable delay is enabled only when 'countercontrol' is at logic'1'. • If the 'countercontrol' is at logic '0' the programmable delay is initialized on every rising clock edge. • The change state signal is forced to logic ' 1' only when the logic state on input signal remains different from the state of data out for a time which is equal to that held in "noise suppression width" • 'countercontrol' is at logic T only when the logic state on 'data in' and 'dataout' is different. Else it is '0'. • The data input to the filter should be synchronous to the system clock. The asynchronous data is to be synchronized before being fed to this module. We claim: 1. A programmable glitch filter comprising: a storage means for storing a current state, which is the output of the said filter, the output of said storage means is connected to one input of a state comparator and the other input of the said state comparator is connected to the input signal, a programmable clock delay means for any required duration which is independent of technology of implementation, is connected between the said state comparator and said storage means, the arrangement being such that the input signal is stored as the new current state in the said storage means only if the input signal changes and then remains unchanged for the programmed duration. 2. A programmable glitch filter as claimed in claim 1 wherein the said means for providing a programmable clock delay comprising: a counter for counting clock pulses to provide a time delay, the control input of the said counter being connected to the output of the said state comparator, the output of the said counter is connected to one input of a digital delay comparator, the other input of the said delay comparator receives a digital value corresponding to the maximum glitch width to be filtered, the output of the said delay comparator is connected to the input of the said storage means. 3. A programmable glitch filter as claimed in claim 2 wherein the counter is enabled only if the input to the said glitch filter is not equal to the output of said storage means and the said counter is initialized when the input of the said glitch filter is equal to the output of said storage means 4. A programmable glitch filter as claimed in claim 1 wherein a multiplexer is provided at the output of the said storage means, which also receives the input signal at its other input and the programmable digital value for the desired maximum glitch width at its control input, the arrangement being such that when the programmed digital value is zero, the input signal is fed to the output of the multiplexer and when the value is not zero, the storage means output is fed to the output of the multiplexer. 5. A programmable glitch filter as claimed in claim 2 wherein the number of bits used for the said counter and said digital delay comparator depends upon the desired range of programmable digital values for maximum glitch width. 6. A method for filtering glitches comprising: storing a current state, which is the final output, comparing the said current state with the input signal, enabling a programmable delay whenever the input signal is different from the stored current state and initializing the programmable delay whenever the input signal is same as the stored current state, making the stored current state equal to the input signal if the programmed delay is complete. 7. A method as claimed in claim 6 wherein programmable delay is obtained by: counting clock pulses comparing the counted clock pulses with a digital value corresponding to the maximum glitch width, generating a signal indicating completion of programmed delay when the counted clock pulses become equal to the said digital value. 8. A method as claimed in claim 7 wherein the counting is enabled only if the input signal is not equal to the stored output state and counting is initialized whenever the input signal is equal to the stored output state. 9. A method as claimed in claim 6 wherein the filtering of glitches is enabled only when the digital value for desired glitch width is non-zero and is disabled when the digital value is zero. 10. A programmable glitch filter substantially as herein described with reference to and as illustrated by the accompanying drawings 11. A method for filtering glitches substantially as herein described with reference to and as illustrated by the accompanying drawings

Documents:

543-del-2000-abstract.pdf

543-del-2000-claims.pdf

543-del-2000-correspondence-others.pdf

543-del-2000-correspondence-po.pdf

543-del-2000-description (complete).pdf

543-del-2000-drawings.pdf

543-del-2000-form-19.pdf

543-del-2000-form-2.pdf

543-del-2000-form-3.pdf

543-del-2000-gpa.pdf

543-del-2000-petition-137.pdf