|Title of Invention||
APPARATUS COMPRISING AN INDUCTOR-CAPACITOR VOLTAGE CONTROLLED OSCILLATOR (LC-VCO), METHOD OF TUNING A CIRCUIT AND LC-VCO
|Abstract||Tuning method and apparatus for LC oscillators are disclosed. Embodiments of the present invention include an adaptively controlling the bitcomparison time to provide the smallest coarse tuning time. The bit comparison time is scaled inversely to the amount of redundancy of corresponding weighted capacitors (C1, C2, ..., CN, C1', C2', ..., CN') in a capacitor array(314, 316) of the LC oscillator.|
|Full Text||BACKGROUND OF THE INVENTION
Field of the Invention
Embodiments of the present invention relate to circuit design. Particularly,
embodiments of the present invention relate to improvements in phase lock loop
Background of the Related Art
Phase locked loops (PLLs) are widely used in various wireless systems due
to its usefulness for digital clock synchronization, frequency synthesizing, and die
like Fig. 1 illustrates a general schematic diagram of a PLL according to the
related art The PLL includes a phase frequency detector 102 (PFD), charge
pump (CP) and loop filter (LF) 104, voltage-controlled oscillator 106(VCO), and
frequency divider. PFD 102 compares the phase/frequency of input and output
signals and sends the result to CP & LF 104. CP & LF 104 converts the result of
comparison in PFD 102 into a DC voltage. PFD 102 generates the "UP" or
"DOWN" signal according to whether the input signal leads or lags the output
VCO 106 generates the pulse frequency as a function of the DC voltage
(Vcontrol) supplied from CP & LF 104.
In PLL applications, inductor-capacitor VCOs (LC-VCOs) are widely used
because of their jitter/phase noise performance, which is typically better than ring
oscillators, for example. LC-VCOs are tuned because process variations, •which
produce tolerances/variations in the various inductor and capacitor components '
and to cover the required frequency and range.
A simple schematic diagram of a related art LC-VCO is illustrated in Fig. 2.
Two CMOS inverters 202 and 204 are cross-coupled by connecting the common
drain of the first inverter 202 to the common gate of the second inverter 204 and
vice versa. The cross-coupled inverters 202 and 204 constitute a multivibrator.
The inductor 206 (L) is connected in parallel with the capacitor circuit 210 to form
a tank circuit. The capacitor circuit 210 is subdivided into analog varactor 212
(CV) and discrete capacitor array 214 (CD). The discrete capacitor array 214 is
used for coarse tuning of the frequency and the varactor is used for fee-tuning.
The voltage nodes for controlling the switches of the discrete capacitor array 214
are omitted in this figure for simplicity. This type of VCO has recently been
applied in wireless applications, because it provides better phase noise
performance than typical varactor-only controlled LC oscillators.
Figure 3 illustrates a block diagram of a related art PLL incorporating the
LC- VCO with discrete capacitors as part of the tank circuit in phase lock
operation. During the normal operating mode, the PFD and the charge pump
302 via low pass filter 304 control the analog varactor 306 to have an exact
frequency and phase lock However, when the PLL becomes activated or tries to
change the desired frequency, the PLL enters into the coarse tuning period to
achieve coarse frequency lock. This coarse frequency acquisition process is
performed using the coarse tuning controller 310, which turns on and off the
appropriate capacitor(s) 312 to move the output frequency of the VCO 308 as
close as possible to the desired frequency.
The block diagram of the PLL during the coarse tuning process according
to the related art is illustrated in Fig. 4. In coarse tuning process, the Bias
Generator generates a fixed control voltage for the varactor of the VCO. Hence,
the capacitance of the varactor (e.g., Cv in Fig. 2) is fixed during the coarse tuning.
Instead of controlling the capacitance of the varactor, the frequency of the VCO
is determined by the discrete coarse tuning capacitors. The Crystal Oscillator
provides the reference for coarse tuning. The Prescaler & Counter counts the
number of VCO clocks during the pre-determined duration for the desired lock
frequency. Here, the predetermined duration is the high duration of the
EN_COUNTER. In each coarse tuning stage, the Digital Comparator compares
the reference number and the counter value from the Prescaler&Counter and
generates UP/DOWN signal to determine whether the VCO frequency is higher
or lower than the desired frequency. With the UP/DOWN signal, the capacitor of
each stage is set as ON or OFF. The Reset Generator & Counter Controller
resets the counter value of the Prescaler&Counter for each coarse tuning stage.
Several methods are published in the related art that perform coarse tuning
and fine-tuning control of the VCO (see, e.g., U.S. Patent No. 6,137,372 and "A
CMOS Self-Calibrating Frequency Synthesizer", IEEE Journal of solid-state
circuits, Vol. 35, No. 10,2000. Each reference is hereby incorporated by reference
herein in its entirety). The accuracy of the coarse tuning process is relevant to
reducing the varactor size. Since the size of the varactor is inversely proportional
to the phase noise, it is advantageous to reduce the size of the varactor to improve
the phase noise performance. As the coarse tuning process is performed more
accurately, the smallest capacitor should be designed to provide a fine frequency
step size during coarse tuning.
To perform the coarse tuning process accurately, both frequency error
detection and the step size of the smallest capacitor should be determined
accurately. Even though modem process techniques provide well-matched
capacitors in terms of capacitance, this error can be minirnized or compensated
during the coarse tuning for a more accurate coarse tuning. The design of the
frequency error detector during the coarse tuning is related to the coarse tuning
time, which will be discussed below in the following paragraphs.
Figs. 5 and 6 illustrate an example of the coarse tuning process with key
timing parameters and a block diagram of detection logic in the coarse tuning
controller, respectively, according to the related art The coarse tuning process
starts whenever the desired frequency is changed or after power-up. Since the
coarse tuning process is a kind of frequency tracking, the digital accumulator 630
is used to estimate the period of the VCO 610. This result is compared with the
reference-timing signal from the external crystal clock. In the particular
implementation of the coarse tuning illustrated in Fig. 6, the digital accumulator
630 (or counter) is periodically reset by the RST_COUNTER signal generated-by
the coarse tuning controller. This counting operation is masked by the
EN_COUNTER signal. As illustrated in Fig. 6, the operation of the counter is
enabled (e.g., using AND gate 620) only when the EN_COUNTER is high.
When the output of the accumulator/counter 630 exceeds the reference number
(e.g., "M" in Figure 6) as determined by digital comparator 650, the
OUT_COUNTER signal becomes high. This OUT_COUNTER signal and
COMP_CLK signal from the coarse tuning controller are used for lead-and-lag
detection of die frequency, by flip-flop 660.
As illustrated in Fig. 5, the OUT_COUNTER signal becomes high at 510
prior to low-to-high transition of the COMP_CLK signal. According to the
frequency error, the latched value will vary from one to zero at 520. In the
illustration of Fig. 5, the VCO frequency is determined to be greater than
expected. This polarity at the latched output (e.g., flip-flop 660) can be used to
decide the polarity of the switch connected to the (i-th) capacitor in the VCO.
When the PLL receives the channel information, the coarse tuning
controller converts the channel information to appropriate timing parameters for
the coarse tuning. For example, when the desired target frequency is 1GHz and
the external reference clock frequency is 20MHz, the coarse tuning controller
works with this 20MHz external clock signal to generate RST_COUNTER,
EN_COUNTER, the reference number, and COMP_CLK signals.
For example, let's assume that the high duration of the EN__COUNTER is
set as 1 us and the target VCO frequency is 1 GHz. Here, the "lus" for the
duration of the EN_COUNTER is a design value and can be changed to other
value according to the accuracy of the coarse tuning process. In this example, the
external clock is divided by 20 (20/20MHz=lus) to generate the high duration of
the EN_COUNTER signal. The reference number is determined from the
division of the EN_COUNTER by the duration of the target VCO frequency.
Hence, in this example, the reference number is 1000 ( = lus/(l/lGHz)). This
reference number is compared with the counter value of the Prescaler&Counter at
the Digital Comparator. The COMP_CLK is synchronized with the falling edge of
the EN_COUNTER and used as a timing clock in the Digital Comparator. The
RST_COUNTER is a reset signal for each coarse toning stage and high during
one external clock after the EN_COUNTER goes from high to low.
The accuracy of the coarse tuning process is a design parameter to be
decided and is mainly determined by the EN_COUNTER signal In Fig. 5 the
Tc,1bit means the total cycle time for switch on and off of one bit in the coarse
tuning, which is mainly determined by operating time of the counter, Tccounter.
A limiting factor for the accurate coarse tuning is the uncertainty of the
lead-and-lag detection logic in Fig. 6. Assuming the goal of the coarse tuning is to
discriminate the frequency difference of 1MHz, then two VCO frequencies of
0.9995GHz and 1.0005GHz should be detected, for example. When the duration
of the EN_COUNTER is set to lus, then the reference number ("M" in Fig. 6)
should be set to 1000(=lus/lns). The time differences between the rising edge of
EN_COUNTER and the rising edge of the OUT_COUNTER are 1.0005 us for
the VCO frequency of 0.9995GHz and 0.9995 us for the VCO frequency of the
1.001 GHz. "When there is no timing uncertainty, the former case will produce
frequency "DOWN" signal and the latter case will produce frequency "UP" by
the lead-and-lag detection logic. However, if the timing uncertainty from the lead-
and-lag detection logic is Ins, the two results can be same. Thus, it is uncertain
whether those two VCO frequencies can be distinguished by the lead-and-lag
When the timing uncertainty is fixed, the accuracy can be improved by
increasing the reference number or the duration of EN_COUNTER. Assuming
that the reference number is increased by 10 times, then the time differences will
be 10.005 us and 9.995 us for those two cases. Since the timing margin of 5ns is
larger than the timing uncertainty of 1ns, the decision will be correct. In other
words, 0.1% of the initial frequency difference of the VCO results in 10ns of the
difference in time rather than Ins in former case. Since this value is large enough
to compensate the uncertainty from the lead-and-lag detection logic, the desired
accuracy can be obtained.
However, the penalty for the improvement in coarse tuning is an increase
of the comparison time or the time required for the coarse tuning. If the number
of bits to be determined is 10bits, then the time required to finish the coarse
tuning will be 10 times for the 1bit decision case. In summary, as the number of
the bits or the accuracy for the coarse tuning is increased, the coarse tuning time is
After finishing the coarse tuning, the PLL enters into the phase lock
operation (eg., as illustrated in Fig. 3). Since the total lock time of the PLL
includes the time required for the coarse tuning, an accurate coarse tuning tends
to increase the total lock time. Further, as stated earlier, the size reduction of the
analog varactor can improve the phase noise performance, because the analog
varactor typically has a poor quality factor when compared to a discrete capacitor
array used for coarse tuning. Additionally, the size of the analog varactor can be
reduced only when the accurate coarse tuning is guaranteed. If the coarse tuning
is less accurate, then the operating range of the analog varactor can extend beyond
the desired frequency and no phase and frequency lock can be achieved.
Accordingly, the coarse tuning should be performed very fast both for good phase
noise performance and small lock time.
The above references are incorporated by reference herein where
appropriate for appropriate teachings of additional or alternative details, features
and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or
disadvantages and to provide at least the advantages described hereinafter.
Accordingly, embodiments of the present invention include tuning
methods and apparatuses for LC oscillators. Embodiments of the present
invention include adaptively controlling the bit-comparison time to provide the
smallest coarse tuning time. The bit comparison time is scaled inversely to the
amount of redundancy of corresponding weighted capacitors in a capacitor array
of the LC oscillator.
Additional advantages, objects, and features of the invention will be set
forth in part in the description which follows and in part will become apparent to
those having ordinary skill in the art upon examination of the following or may be
learned from practice of the invention. The objects and advantages of the
invention may be realized and attained as particularly pointed out in the appended
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The invention will be described in detail with reference to the following
drawings in which like reference numerals refer to like elements wherein:
Fig. 1 illusttates a general schematic diagram of a PLL according to the
Fig. 2 illustrates a simple schematic diagram of a related art LC-VCO;
Fig. 3. illustrates a block diagram of a related art PLL incorporating the
LC- VCO with discrete capacitors as part of the tank circuit in phase lock
Fig. 4 illustrates a block diagram of the PLL during the coarse tuning
process according to the related art;
Fig. 5 illustrates an example of the coarse tuning process with key timing
parameters according to the related art.
Fig. 6 illusttates a block diagram of detection logic in the coarse tuning
Fig. 7 illustrates an arrangement of a simplified timing diagram of the
coarse tuning process; and
Fig. 8 illustrates a simplified timing diagram of the coarse timing process
according to an embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
In the following detailed description of preferred embodiments, reference
. is made to the accompanying drawings that show, by way of illustration, specific
embodiments in which the invention may be practiced. In the drawings, like
numerals describe substantially similar components throughout the several views.
These embodiments are described in sufficient detail to enable those skilled in the
art to practice the invention. Other embodiments may be utilized, and structural,
logical, and intellectual changes may be made without departing from the scope of
the present invention. Moreover, it is to be understood that various embodiments
of the invention, although different, are not necessarily mutually exclusive. For
example, a particular feature, structure, or characteristic described in one
embodiment may be included within other embodiments. The following detailed
description is not to be taken in a limiting sense, and the scope of the present
invention is defined only by appended claims, along with the full scope of
equivalence to which such claims are entitled.
Embodiments of the present invention disclose methods to reduce the
total bit-comparison time of the coarse tuning period. For example, the trade-off
between the coarse tuning time and the accuracy of the coarse tuning can be
resolved by adopting weighted comparison time for the coarse tuning of the each
bit decision. Thus, the bit-comparison time for each coarse tuning bit can be set
differently according to its comparison resolution.
Fig. 7r illustrates a simplified timing diagram of the coarse tuning process in
the related art for comparison purposes. As noted above, the final resolution of
the coarse tuning should be set small enough to allow reduction of the varactor.
However, the coarse tuning time fot the each bit also is set large enough to cover
all of the variation in decision process. Those variations can come from the
uncertainty of the lead-and-lag detection logic, other logic delay, noise (e.g., power
supply noise), start-up time of the each component, and the like. Accordingly,
when the number of the coarse tuning bits increases, the total time required for
the coarse tuning increases linearly as illustrated in Fig. 7.
In contrast, Fig. 8 illustrates a simplified timing diagram of the coarse
tuning process according to embodiments of the present invention. Unlike the
example in Fig. 7, the decision time for the each bit can set differently. The last
bit (e.g., LSB) has a longer decision time and the first bit (e.g., MSB) has a shorter
decision time. However, the duration of the each bit can be optimized according
to the specific implementation of the coarse tuning algorithm. Therefore,
weighting the decision time can provide accurate coarse tuning result, while also
reducing coarse tuning time.
Adaptive time regulation for the coarse tuning according to embodiments
of the present invention is provided by incorporating redundant weighting in the
discrete capacitor array for the coarse tuning. Table 1 shows an example for the
implementation of the capacitor array for the coarse tuning. However, those
skilled in the art will appreciate other weighing schemes can be used. In Table 1,
Caps(n) corresponds to the (n-th) capacitor used to tune the frequency of the
VCO. For example, Caps(l) is the last capacitor to be selected through the coarse
tuning process. Referring to Table 1, only the relative weighting factor for the
capacitance value is shown. The weighting factors from Caps(lO) to Caps(7) are
selected by binary weighting for the wide VCO range. Further, the weighting factors
from Caps(6) to Caps(l) can be selected, empirically from the trade-off the coarse tuning
time and the redundancy margin. For example, the weighting of Caps(6) is 10 and the
sum of the weightings from Caps(5) to Caps(l) is 16. So there is redundancy amount of 6
in Caps(6) level.
Since the frequency of the LC-VCO is determined by the equation of
the relative weighting of the capacitance is sufficient to indicate the
variation of the frequency. The redundancy R(i) in the Table 1 can be obtained
using the weighting W(i) by equation (1) as follows.
Since the capacitance value corresponds with the frequency, the above equation
indicates that the redundancy can be used to compensate error in the decision
process. For example, R(10) is 10 and thus if the switch for the Caps(10) is
selected in wrong way, this error can be corrected in the following decision
process. However, when the polarity of the switch for Caps(10) is set to zero by
unexpected error in the decision logic and the amount of the redundancy is
negative unlike Table. 1. The coarse tuning process cannot resolve the frequency
error caused by this negative redundancy. In an ideal situation, if the decision
process is perfect and the redundancy can be all set to zero, then the result of the
coarse tuning will also be ideal and the resulting accuracy will be determined by
the smallest weighting factor. However, in practical implementations of the
capacitor array, there is some mismatch between two binary-weighted capacitors.
If there is no redundancy for the lower bits, this mismatch at certain stage cannot
be resolved. Since the amount of the mismatch is proportional to the weighting
factor, the frequency error caused by the mismatch will be less severe for
capacitor arrays with smaller weighting factors. For example, a 10% error for two
binary weighted capacitors, 64 and 1, will result in the error of the capacitance, 6.4
and 0.1, respectively. If the final resolution of the tuning capacitor is assumed to
be one, a 10% error in the most-significant bit will give too large an error for the
frequency calculation. Thus, the redundancy is usually given to high index (e.g.,
MSB) value rather than the low index as illustrated in Table 1.
Although redundancy in an array of capacitors can intentionally be made to
compensate for fabrication mismatch of the capacitor array, this property can also
be used to reduce the coarse tuning time effectively. Even though some
uncertainty or error happens to exist in the decision process of the coarse tuning,
those errors or uncertainty will be corrected if amount of the error is smaller than
the redundancy amount at that specific index.
For example, assuming that the desired target frequency corresponds to
"130" as the sum of the weighted capacitance, the coarse tuning values of
Caps(10) and Caps(2) should be set to one (e.g., switched on) in the ideal case. For
example, referring to Fig. 6, even though the Caps(10) is set to one, the lead-and-
lag detection logic produces the comparison result of "UP". Accordingly, the
frequency of the VCO should be increased. In this case, it is assumed that the
frequency increases as the number of weighted capacitor increases. Thus, the
effective frequency of the VCO with "1" of Caps(10) is slower than the target
frequency with "130" of the effective weighting value. If the decision logic has
some offset and, for example, that value is "3", then the coarse toning value for
Caps(lO) will be one rather than zero. Since the weighting factor given to the
capacitor is a factor to determine the operating frequency of the VCO, the offset
value is directly expressed as timing error when converted to the time domain
from the frequency domain.
For example, if the unit value of "1" corresponds to a period error of 3ns,
then an offset value "3" indicates that the coarse tuning process has a 9ns offset at
its decision. This timing error can be corrected by increasing the comparison time
for each bit. Assuming that only the first decision process has decision error for
simplicity, then the remaining coarse toning decision will be correct. Thus, the
Caps(lO-l) from the coarse tuning will be  to get the total weighted
value of 130. Even though the above example is simplified for the decision error,
it is clear that the redundancy helps to compensate the decision error at certain
stage. Redundancy in Caps(N) level,where N32, is the difference between the sum
of Caps from N-1 to 1 and Caps(N). For example, the target VCO frequency is
"13". Let's assume there is a decision error in Caps(6) level and, therefore, Caps(6)
is erroneously selected as "0", instead of the correct "1". Because the weighting of
the Caps(6) is "10" and selected as "0", the rest of the Caps(i.e. Caps(5-1)) should
be selected to cover the target VCO frequency. As a result, Caps, ,
instead of  is selected. So, in case there are decision errors, the rest
of the stages can cover the error with the help of redundancy.
The amount of the mismatch in two binary-weighted capacitor arrays is
typically larger than error sources from the decision logic. Thus, the redundancy
value is designed to be able to compensate for the mismatch rather than the error
in the decision process of the coarse toning. Therefore, the timing error during
the decision process has less impact on the accuracy of the coarse toning. Thus,
the duration of the coarse tuning can be reduced if there is large redundancy.
Since the extension of the duration of the comparison time (e.g., as illustrated in
Fig. 5) can reduce the effect from the decision process, the most accurate decision
or longest comparison time can be made when the redundancy is zero. In the
particular example of Table, the coarse tuning controller should have the most
accurate decision when it decides the switching polarity of Caps (3-1) where the
redundancy is zero. The comparison accuracy for the other bits can be relaxed and
thus smaller comparison time can be allowed.
As stated before, when the comparison time is doubled, the accuracy of the
coarse toning process is typically doubled. Assuming that Tmin is the minimum 1-
bit comparison time required for Caps(1-3), the comparison time for Caps(4) can
have the value of Tmin/2 to give correct coarse tuning result Likewise, the
comparison time of Tmin/10 can be used for Caps(10), which will have the same
probability of error with that of Tmin for Caps(1-3).. The following table illustrates
one example procedure for timing according to embodiments of the present
As illustrated in Table 2, multiple bits are switched in a different way than
disclosure in the related art. Caps can be switched from the MSB to LSB in pairs,
sequentially. For example, in the first stage, Caps(10) and Caps(9) are selected. In
the second stage, Caps(9) and Caps(8) are selected. Coarse tuning time is limited
by the longest comparison time between neighboring Caps, Caps(N) and Caps(N-
1). In contrast in the related art, Caps(6) and Caps(3) are switched at lie same
stage, thus, coarse tuning time is limited by the redundancy amount of Caps(3).
However, according to the broadwork of the present invention, Caps(6) and
Caps(5) are switched at the same stage, thus, coarse tuning time is limited by that
of Caps(5), not Caps(3). Accordingly, cbarse tuning time can be significantly
reduced compared to the related art systems.
If the same comparison cycle time is applied for the coarse tuning, the total
time for the coarse tuning will be 10* Tmin However, when the adaptive
optimization for the comparison time is made, the total coarse tuning time will be
reduced. For example, the course tuning time of Table 1 is
Thus, the total coarse tuning is reduced by
greater than two times with essentially the same accuracy. Accordingly, accurate
coarse tuning can be performed by using the adaptive scaling for the comparison
time as described in embodiments of the present invention. The accurate coarse
tuning also allows for a smaller size of the analog varactor, which improves phase
Additionally, the total lock time can be reduced or made consistent across
all conditions by employing techniques described with reference to embodiments
of the present invention. The coarse tuning process is digital and thus its
functionality and the operating time is determined by the initial design. However,
the phase lock operation after the coarse tuning is affected by the initial state of
the PFD, the amount of the frequency error, and the variation of the loop
characteristics. Accurate coarse tuning reduces the frequency error to the target
frequency after the coarse tuning, and thus the maximum value of the frequency
error can be reduced. Accordingly, the time required to obtain frequency and
phase lock can be reduced. Thus, the total lock time can be regulated and reduced
over all initial frequency errors by the accurate coarse tuning.
The overhead due to accurate coarse tuning is greatly relaxed due to the
adaptation of the comparison time in embodiments of present invention. The
overhead for the accurate coarse tuning and increase of number of bits to be
decided are nulled by the regulation of the coarse tuning time and the time
reduction of the phase lock operation. Accordingly, embodiments of the present
invention can reduce the time of coarse tuning in LC-VCOs and thus reduce the
lock time of PLLs.
The foregoing description relates to coarse tuning methods and
apparatuses for LC oscillators to improve the phase noise performance and to
increase the operating range of the LC oscillator. The coarse tuning increases the
effective lock time of the PLL and this overhead increases as the desired accuracy
of the coarse tuning increases. In embodiments of the present invention, the bit-
comparison time is adaptively controlled to provide the smallest coarse tuning
time. The redundancy in the weighted capacitor array for the coarse tuning allows
for reduced comparison times without sacrificing the accuracy of the coarse
tuning. The bit comparison time is scaled according to the amount of the
redundancy. Since the redundancy of the weighted capacitor is used to
compensate for the mismatch in the capacitance, the use of this property to
reduce the coarse tuning is not an additional burden. Further, if the same time
limit on the coarse tuning time is used, embodiments of the present invention can
increase the accuracy of the coarse tuning. Since accurate coarse tuning can
reduce the operating time and the time variation for the phase lock operation,
embodiments of the present invention can reduce lock time of PLLs.
The foregoing embodiments and advantages are merely exemplary and are
not to be construed as limiting the present invention. The present teaching can be
readily applied to other types of apparatuses. The description of the present
invention is intended to be illustrative, and not to limit the scope of the claims.
Many alternatives, modifications, and variations will be apparent to those skilled in
the art In the claims, means-plus-function clauses are intended to cover the
structures described herein as performing the recited function and not only
structural equivalents but also equivalent structures.
1. An apparatus comprising an inductor-capacitor voltage controlled oscillator (LC-VCO),
the LC-VCO comprising:
a capacitor array having a plurality of capacitors, wherein the plurality of capacitors are
arranged to have a non-linear weighting function; and
a coarse tuning controller configured to provide an adaptive comparison time for each
capacitor based on the weighting function of each capacitor, wherein the weighting function of
the plurality of capacitors has a first portion that is linearly weighted and a second portion that
is binary weighted;
said LC-VCO also having:
a multivibrator which outputs a frequency signal;
a first tuning circuit which tunes the frequency signal by a first amount;
a second tuning circuit which tunes the frequency signal by a second amount which is
less than said first amount; and
a control circuit which controls the first and second tuning circuits to tune the frequency
signal by said first and second amounts, wherein the first tuning circuit comprises:
a first array of switches coupled to the first array of capacitors respectively; and
a second array of switches coupled to the second array of capacitors respectively,
wherein the control circuit controls the first array of switches to selectively couple the first
array of capacitors to the first node of the multivibrator, and controls the second array of
switches to selectively couple the second array of capacitors to the second node of the
multivibrator, to tune the frequency signal, wherein the first and second arrays of capacitors are
assigned weight values or redundancy values, at least a portion of which are different from one
2. A method of tuning a circuit comprising:
selecting a capacitor from a plurality of capacitors in a discrete capacitor array, wherein
the plurality of capacitors have a non-linear weighting function;
adapting a comparison time of a circuit that compares a frequency output of the circuit to
a reference value, based on the weighting of the selected capacitor, wherein the comparison
time is inversely proportional to a redundancy amount of the weighting of the selected
3. The apparatus as claimed in claim 1, wherein the multivibrator comprises:
a first inverter circuit having a first node;
a second inverter circuit having a second node and being cross-coupled to the first
inverter circuit; and
an inductor coupled between the first and second nodes, wherein the first and second
tuning circuits charge and discharge the inductor to tune frequency signal.
4. The apparatus as claimed in claim 3, wherein the first tuning circuit comprises:
a first array of capacitors selectively coupled to the first node of the multivibrator; and
a second array of capacitors selectively coupled to the second node of the multivibrator
which outputs the frequency signal tuned by the first and second tuning circuits.
5. The apparatus as claimed in claim 1, wherein the control circuit controls the first and
second arrays of switches to selectively couple different numbers of capacitors to the first and
second nodes of the multivibrator to tune the frequency signal.
6. The apparatus as claimed in claim 5, wherein the control circuit controls the first and
second arrays of switches so that zero capacitors are coupled to the first node and more than
zero capacitors are coupled to the second node to tune the frequency signal.
7. The apparatus as claimed in claim 4, wherein the second tuning circuit comprises:
a first varactor coupled to the first node of the multivibrator through the first array of
a second varactor coupled to the second node of the multivibrator through the second
array of capacitors, wherein the control circuit controls the first and second varactors to tune
the frequency signal.
8. The apparatus as claimed in claim 7, wherein the control circuit comprises:
a first controller which controls tuning by the first tuning circuit; and
a second controller which controls tuning by the second tuning circuit, wherein the first
and second controllers generate independent control signals for controlling the first and second
tuning circuits respectively, to tune the frequency signal by said first and second amounts.
9. The apparatus as claimed in claim 8, wherein the first control signal is a digital signal
which controls tuning of the first tuning circuit
10. The apparatus as claimed in claim 9, wherein the second control signal is an analog
signal which controls tuning of the second tuning circuit.
11. The apparatus as claimed in claim 4, wherein each of the first and second arrays of
capacitors comprises at least one capacitor.
12. The apparatus as claimed in claim 1, wherein the frequency signal is tuned based on the
weight and redundancy values assigned to the capacitors which are selectively coupled to the
first and second nodes of the multivibrator by the first control signal.
13. The apparatus as claimed in claim 12, wherein the first and second arrays of capacitors
are selectively coupled to the first and second nodes of the multivibrator according to an
iterative process, wherein a decision time for selective coupling of the capacitors in said first
and second arrays is in ascending order from a capacitor controlled by a most significant bit in
the first control signal to a capacitor controlled by a least significant bit in the first control
APPARATUS COMPRISING AN INDUCTOR-CAPACITOR VOLTAGE CONTROLLED
OSCILLATOR (LC-VCO). METHOD OF TUNING A CIRCUIT
Tuning method and apparatus for LC oscillators are disclosed. Embodiments of the
present invention include an adaptively controlling the bitcomparison time to provide the
smallest coarse tuning time. The bit comparison time is scaled inversely to the amount of
redundancy of corresponding weighted capacitors (C1, C2, ..., CN, C1', C2', ..., CN') in a
capacitor array(314, 316) of the LC oscillator.
|Indian Patent Application Number||2320/KOLNP/2006|
|PG Journal Number||35/2012|
|Date of Filing||16-Aug-2006|
|Name of Patentee||GCT SEMICONDUCTOR.INC.|
|Applicant Address||2121 RINGWOOD AVENUE, SAN JOSE, CA 95131, U.S.A.|
|PCT International Classification Number||H03B5/00|
|PCT International Application Number||PCT/US2005/001142|
|PCT International Filing date||2005-01-13|