Title of Invention  " A METHOD FOR ENCODING THAT GENERATES PARITYCHECK BITS (P0,...Pm1) BASED ON A CURRENR SYMBOL SET S=(S0,....Sk1)" 

Abstract  A method for encoding that generates paritycheck bits (po, ..., pm1) based on a current symbol set s=(s0, ..., sk1) is disclosed. The method involves the steps of: obtaining the current symbol set s=(s0, • • •, Sk1), where k is the length of the entire current symbol set when unshortened; using a matrix H to determine the paritycheck bits, wherein H comprises a section H1 and a section H2, and wherein H1 has a plurality of different column weights and comprises a plurality of submatrices where H1 comprises a plurality of submatrices each having column weights substantially interlaced between the submatrices; and transmitting the paritycheck bits along with the current symbol set. 
Full Text  Field of the Invention The present invention relates generally to encoding and decoding data and in particular, to a method and apparatus for encoding and decoding data utilizing low density paritycheck (LDPC) codes. Background of the Invention A lowdensity paritycheck (LDPC) code is defined by a parity check matrix H, which is a lowdensity pseudorandom binary matrix. For implementation reasons, a single H matrix is sometimes preferred even though multiple code rates and block sizes must be supported. In this case, the multiple code rates and block sizes may be obtained by shortening a systematic LDPC code. In a systematic code that maps k information tits to n coded bits, the first k bits of the coded bits are the information bits. When shortening, L of the information bits are set to zero and the corresponding zeros are removed from the coded bits. Shortening is typically performed by (logically or physically) setting the. first L information bits to zero. In some encoders, leading zeros do not change the state of the encoder, so that the zeros do not have to be fed into the encoding circuit. For an LDPC code, shortening by setting the first L information hits to zero can be accomplished in two equivalent ways. First, a k bit information vector can be set with L bits as zero, which is assumed to be located in the first L information bit positions in the following without losing generality. The length k information vector can be fed into the encoder (which may be based on the unshortened (nk)byn H matrix or the equivalent kbyn generator matrix G), and the L zeros subsequently stripped from' the coded bits after encoding. Second, a shortened information vector may be passed to the encoder which encodes based on a shortened (nk)by(nL) H matrix with the first L columns removed, or the equivalent shortened (kL)by(nL) G matrix. However, the resulting shortened LDPC code(s) are likely to have poor performance because their weight distribution may be inferior to a code custom designed for that code rate and block size. It is not clear how to construct a shortened LDPC code that maintains good performance. The digital video broadcasting satellite standard PVBS2) uses LDPC codes, and defines an H matrix for each desired code rate. DVBS2 defines ten different LDPC code rates, 1/4, 1/3, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 3/9 and 9/10, all with a coded block length n — 64 800 bits. For each code rate, a different parity check matrix H is specified — shortening is not used in the standard. As is known in the art, irregular LDPC codes offer better performance than the regular LDPC codes. The term regular when used for an LDPC code means that all rows of H have the same number of 1's, and all the columns of H have a same number of l's, where the number of l's in a row or column is also called the weight of the row or column. Otherwise the LDPC code is considered irregular. In a narrower sense, the term regular can also be applied to either the rows or the columns (i.e., a matrix may have regular column weights, but irregular row weights), and can also be applied to a submatrix of a matrix (e.g., a submatrix of a matrix is regular when all the columns of the submatrix have the same column weight and all the rows of the submatrix have the same row weight). Because irregular codes are desired for good performance, DVBS2 defines multiple H matrices, each with the desired weight distribution for good performance at that code rate. The numbers of columns of each weight are shown in Table 1 for all the DVBS2 code rates. Some code designs, such as Intel's LDPC code proposed to 802.16, have only one H matrix and uses shortening to get other code rates, but the codes after shortening do not perform well. The portion of H corresponding to the information bits (denoted H1) is regular (and therefore the entire matrix is sometimes referred to as semiregular), and after shortening the code weight ilistribution is poor compared to a good design. Good LDPC designs tend not to have regular column weight in H1. Accordingly, the present invention provides a method for encoding that generates paritycheck bits (p0, ..., pm1) based on a current symbol set s=(S0...., Sk1), the method comprising the steps of: obtaining the current symbol set s=(s0, ..... Sk1), where k is the length of the entire current symbol set when unshortened; using a matrix H to determine the paritycheck bits, wherein H comprises a section H1 and a section H2, and wherein H1 has a plurality of different column weights and comprises a plurality of submatrices where H1 comprises a plurality of submatrices each having column weights substantially interlaced between the submatrices; and transmitting the paritycheck bits along with the current symbol set. This invention proposes a method for constructing an irregular H matrix that performs well unshortened or shortened. The matrix and its shortened versions can he used for encoding and decoding. For a code that takes k information bits and generates n code bits, the H matrix is divided into two parts H = [H1 H2 ], where H1 has size mbyk and H2 has size mbym, m=nk. H1 corresponds to the unshortened information bits, and H2 corresponds to the parity bits, so that [(H1)Jnxt (HJ),„„][(J)M (PL,]T =0,. When shortening the first L positions of s, the first L columns of H1 are essentially removed. H1 is deterministic in that a particular column weight structure is defined. H2 is nondeterministic in that it can be regular or irregular, have any structure, or be randomly constructed. A preferred H2 can be similar to the one described in US Pat. Application No. 10/839995 "Method And Apparatus For Encoding And Decoding Data" in the Intel 802.16 LDPC proposal (approximately lower triangular, all columns having weight 2 except last column having weight 1, l's in a column are on top of each other, top 1 is on the diagonal. Mathematically the mbym H2 matrix is described as the entry of row i column j being 1 if i=j, and i=j+l, 0 Another exemplary realization of Hz is For irregular codes that have better performance than regular codes, the columns of various weights can he arranged in any order without affecting performance, since permuting the order of code bits does not affect errorcorrecting performance. The column weights are therefore typically distributed with no particular order. For example, all columns of the same weight may be grouped together. When the leading L columns of H are effectively removed through shortening, the remaining weights can result in poor performance. To solve the problem, the deterministic section H1 comprises a plurality of submatrices each having column weights substantially interlaced between the sub matrices. Interlacing between submatrices is based on a desired column weight distribution for the submatrices. The interlacing between the submatrices is uniform if the desired column weight distribution is the same for all submatrices. The interlacing between the matrices is nonuniform if the desired column weight distribution is different for two submatrices. Within a submatrix, the columns of different weights may be interlaced such that the columns of different weight are spread predominantly uniformly over the submatrix. In this invention, the columns of different weights are uniformly or non uniformly interlaced between submatrices, so that the resulting shortened matrix can have much better weight distribution, and therefore better errorcorrecting performance. Let H1 be irregular in that it has two or more distinct columns weights (e.g., 3 and 10 ones in each column of H1). The columns of H1 are further divided into two sections (submatrices), H1a and Hlb, where Hla is an mbyL matrix (i.e., first L columns of H1) and Hib is an mby(kL) matrix (i.e., remaining kL columns . of H1). The columns of different weights are interlaced between Hla and HIb, so that after shortening L bits (i.e., effectively removing Hla from H); the resulting code with [Hlb H2] has a good weight distribution. When encoding, the encoder first prepends L zeros to the current symbol set of length (IcL). Then the zeropadded information vector S=[0L sb, where % has length IcL, is encoded using H as if unshortened to generate parity bit vector p (length m), After removing the prepended zeros from the current symbol set, the code bit vector x=[sb p] is transmitted over the channel. This encoding procedure is equivalent to encoding the information vector Sb using the shortened matrix [Hlb H2] to determine the paritycheck bits. The simple example was described with two regions of H1, but H1 can be further subdivided with the columns interlaced over smaller regions. The column weight interlacing is performed such that after shortening the resulting parity check matrices all have a good weight distribution. The interlacing between submatrices may be performed in a uniform or non uniform manner. Uniform interlacing has a desired weight distribution that preserves the approximate column weight ratio of H1 for each region of H1. For example, if H1 has approximately 25% weight x1 and 75% weight x2 columns, H!a and Hlb can each have approximately 25% weight xl and 75% weight x2 columns by interlacing one weight xl column with three weight x2 columns throughout H1. Alternatively, the columns can be arranged by placing approximately round( 0.25*width(Hla)) weight xl column followed by round(0.75*width(Hla) weight x2 columns in Hla. In both cases Hlb will have a column weight distribution as Hlb, and the arrangement of the columns in Hlb does not affect performance unless the code is further shortened (i.e., Hib is divided into additional regions). Uniform interlacing generally results in sub optimal weight distributions for the shortened codes. Nonuniform interlacing attempts to match a desired weight distribution for each region of H1. For example, if H1 has a weight distribution of 25% weight x1 and 75% weight x2, but a 50% shortened code with Hlb has a desired weight distribution of 50% weight xl and 50% weight x2, Hlb can achieve the desired distribution by nonuniform interlacing of the columns between H1aand Hlb. In this case, approximately round(0.25*width(H1)  0.5*width( Hlb) weight x1 columns and approximately round(0.75*width(H1)  0.5*width(Hlb) weight x2 columns are placed in Hla, and Hlb has the desired weight distribution of 0.5*widfh(Hlb) weight xl and 0.5*width( Hlb) weight x2 columns. An interlaced nonuniform distribution is achieved by interlacing approximately one weight x2 column with zero weight x1 columns in Hla (i.e., all of Hla are weight x2 columns) and (if desired) by alternating approximately one weight x2 column with one weight x1 column in Hlb. If multiple shortened code rates are to be supported, then the nonuniform interlacing with columns of various weight scattered over the submatrix is desirable in providing better performance for all shortened code rates. Algorithm Pseudo code [The following Matlab is included to illustrate how a good column weight distribution may be found for a given code rate and cods size using the desired weight distributions. % get optimized degree distribution, dv = maximum column weight, rate is code rate vDeg = getDegDist(rate, dv); % get the number of variable nodes of each weight, N is the number of columns in H vNodes = round(N * vDeg(2,:)./vDeg(l);)/sum(vDeg(2,:)./vDeg(l,:))); function [vDeg] = getDegDist( rate, dv) % vDeg(li); col weight i % vDeg(2,i): fraction of edges linked to variable node of weight vDeg(l,i) The following Matlab code illustrates how to interlace within a submatrix. Note that s is the vector of column weights, and z1 and z2 are dependent on the particular column weight distribution within the submatrix. temp = [s(l:lengthl) ones(l,total_lengthlengthl)]; submatrixl = reshape( reshape( temp, z1, z2)', 1, z1*z2); idx = find(submatrixl submatrixl (idx) =[]; Example An example is used to illustrate the proposal described above. For a rate 4/5 code of size (2000,1600), an H matrix is found with column weights of 2, 3, and 10. The column weight distribution of the uninterlaced paritycheck matrix Hnon is plotted in Figure 1. After column interlacing of the H1 portion, the column weight distribution of the resulting paritycheck matrix Hinter is plotted in Figure 2, and listed in Appendix A. Matrix Hinter is the same as matrix Hnon except that the column permutation is introduced. When shortening Hinter, the resulting matrix still maintains good column weight distributions. As an example, given target weight distributions of a rate 2/3 code, vDeg = [ 2 0.1666670000 (0.33000059795989) 3 0.3679650000 (0.48571370868582) 10 0.4653680000 (0.18428569335429)]; where the first column indicates desired column weight, the third column indicates the number of columns with the given weight, the nonuniform insertion algorithm yields the column weight distributions of derived rate 2/3 code in Table 2. Similar procedure is used to find the desired column weight distribution of the rate 54 code (after shortening the original rate 4/5 code) in Table 2. The weight distributions for Hnon and Hu_inter (with uniform interlacing) are given in Tables 3 and 4, respectively. Note that in all cases H2 has 399 weight 2 and one weight 3 columns, and H1 has one weight 2 column. Table 2. Number of Columns of Various Weight In irate 4/5 Hinter and its derived codes. Simulations studies show that nonuniform interlacing yields LDPC codes with good performance unshortened or shortened. The performance of the un shortened rate 4/5 code is shown in Figure 3, in comparison to the 802.16 proposed code design. Note that without shortening, the irregular code design has the same performance with or without column weight interlacing. Simulation shows that Hnon and ninter perform 0.2 dB better than the 802.16 proposed design (Intel) at FER=102. When shortening the code by L=800 information positions, the leading 800 columns of Hnon (or Hinter) are essentially removed, resulting in a rate 2/3 code. The performance of the shortened codes is shown, in Figure 4, in comparison to the similarly shortened 802.16 proposed design. The simulation shows that without interlacing, the code performance after shortening is inferior to the 802.16 proposed design (Intel) due to the poor weight distribution after shortening. However, after interlacing, the code performance is 0.25 dB better than the 802.16 proposed design at FER=102. Similarly, the code can be further shortened. When shortening the original code by L=1200 information positions, the leading 1200 columns of Hnon (or Hinto) are essentially removed, resulting in a rate ½ code. The performance of the shortened codes is shown in Figure 5, in comparison to the similarly shortened 802.16 proposed design. The simulation shows that without interlacing, the code performance after shortening is slightly inferior to the 802.16 proposed design due to the poor weight distribution after shortening. However, after interlacing., the code performance is 0.35 dB better than the 802.16 proposed design at FER=102. Figure 1 shows column weight distribution of the parity check matrix with noninterlaced column weight in H1, i.e., the columns of the same weight is grouped together. The code size is (2000, 1600). Figure 2 shows column weight distribution of the parity check matrix with interlaced column weight in H1. The code size is (2000,1600). Figure 3 shows FER performance of the unshortened codes of size (2000, 1600). The two unshortened codes are: (a). 802.16 proposed design (Intel); (b). The irregular code design. Note that without shortening, the irregular code design has the same performance with or without column weight interlacing. Figure 4 shows FER performance of the (1200, 800) codes shortened from the (2000, 1600) codes by 800 bits. The three unshortened codes are: (a). 802.16 proposed design (Intel); (b). The irregular code design without column weight interlacing; (c). the irregular code design with the column weight interlacing. Figure 5 shows FER performance of the (800, 400) codes shortened from the (2000, 1600) codes by 1200 bits. The three unshortened codes are: (a). 802.16 proposed design (Intel); (b). the irregular code design without column weight interlacing; (c). the irregular code design with the column weight interlacing. Appendix: Interlaced Column Weight Distribution Presented below is the column weight distribution of the irregular (2000, 1600) H matrix after interlacing the H1 section. The column weight of each column are shown starting from the first column. 10 333333 10 333333 10 333333 10 333333 10 333333 10 333333 10 333333 10 333333 10 333333 10 333333 10 333333 10 333333 The present invention also provides a method for operating a decoder that estimates a current symbol set s=C?0, •••, %i). the method comprising the steps of: receiving a signal vector y=(yo ■■■ yni); and using a matrix H to estimate the current symbol set (J0, ..., sk.i), wherein H comprises a section Hi and a section H2, and wherein Hi has a plurality of different column weights and comprises a plurality of submatrices where Hi comprises a plurality of submatrices each having column weights substantially interlaced between the submatrices wherein Brief Description of the Accompanying Drawings FIG. 1 shows column weight distribution of a parity check matrix with non interlaced column weight in Hi, i.e., the columns of the same weight are grouped ■ together. The code size is (2000,1600). FIG. 2 shows column weight distribution of a parity check matrix with interlaced column weight in Hi. The code size is (2000, 1600). FIG. 3 shows FEE.performance of unshortened codes of size (2000, 1600). FIG. 4 shows FER. performance of the (1200, 800) codes shortened from the (2000, 1600) codes by 8 00 bits. FIG. 5 shows FER performance of the (800, 400) codes shortened from the (2000, 1600) codes by 1200 bits. Detailed Description of the Drawings 3. That unless the irregularity in procedure on the part of the petitioner due to its failure in observing the time limit, for not furnishing the said particulars of the corresponding applications, which have been filed outside India on or before the date of filing of the instant Indian application, or subsequent to the filing of the instant Indian Application within six months from the date(s) of filing said nonIndian application^), is condoned by the Learned Controller in exercise of the residuary power vested in him, under Rule 137, the petitioner will suffer irreparable loss and prejudice. 4. That the petition is bonafide and made for the ends of justice. hi the premises, the Petitioner would humbly pray that the irregularity in procedure caused by not complying with the time schedules, as mentioned hereinabove, be condoned in exercise of the residuary Power vested in the Learned Controller, under Rule 137 of the prevalent Indian Patents Rules, as amended by die Patents (Amendment) Rules 2006, and said "foreign filing particulars" be taken on record. And for this act of kindness your Petitioner, as in duty bound, shall ever pray. WE CLAIM: 1. A method for encoding that generates paritycheck bits (p0, ...,pm1) based on a current lowdensity parity check symbol set s=(s0, ..., Skl1), the method comprising the steps of: acquiring a value L; obtaining the current symbol set s=(s0,..., SkL1) of length (kL); obtaining a zeropadded information vector s of length k by zero padding the current symbol set with L zeroes where L>0; using a matrix H and the zeropadded information vector s to determine the paritycheck bits, wherein H comprises a section H1 and a section H2 and H1 has size m bykand H2 has size mbym; and transmitting the paritycheck bits along with the current symbol set s=(so, ..., skL 1); charactersied in that H1 consists of two submatrices; one of the two submatrices comprising columns having a first column weight and columns having a second column weight, the first column weight being different from the second column weight, the columns of the first column weight and the columns of the second column weight being substantially interlaced in the submatrix; and the other of the two sub matrices comprising columns having the first column weight and columns having the second column weight, the columns of the first column weight and the columns of the second column weight being substantially interlaced in the submatrix. ABSTRACT A Method For Encoding That Generates ParityCheck Bits (po,...,Pm1) Based On A Current Symbol Set s=(so,..., sK1) A method for encoding that generates paritycheck bits (po, ..., pm1) based on a current symbol set s=(s0, ..., sk1) is disclosed. The method involves the steps of: obtaining the current symbol set s=(s0, • • •, Sk1), where k is the length of the entire current symbol set when unshortened; using a matrix H to determine the paritycheck bits, wherein H comprises a section H1 and a section H2, and wherein H1 has a plurality of different column weights and comprises a plurality of submatrices where H1 comprises a plurality of submatrices each having column weights substantially interlaced between the submatrices; and transmitting the paritycheck bits along with the current symbol set. 

02310kolnp2006 assignment.pdf
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02310kolnp2006 description[complete].pdf
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2310KOLNP2006(13122011)ASSIGNMENT.pdf
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2310KOLNP2006GRANTEDABSTRACT.pdf
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2310KOLNP2006GRANTEDDRAWINGS.pdf
2310KOLNP2006GRANTEDFORM 1.pdf
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2310KOLNP2006GRANTEDSPECIFICATION.pdf
2310KOLNP2006OTHERS 1.1.pdf
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2310KOLNP2006PETITION UNDER RULE 137.pdf
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Patent Number  253220  

Indian Patent Application Number  2310/KOLNP/2006  
PG Journal Number  27/2012  
Publication Date  06Jul2012  
Grant Date  04Jul2012  
Date of Filing  14Aug2006  
Name of Patentee  MOTOROLA MOBILITY, INC.  
Applicant Address  600 NORTH US HIGHWAY 45, LIBERTYVILLE, IL 60048, UNITED STATES OF AMERICA  
Inventors:


PCT International Classification Number  H03M13/11  
PCT International Application Number  PCT/US2005/016410  
PCT International Filing date  20050511  
PCT Conventions:
