Title of Invention	METHOD FOR FAULT HANDLING IN A CONVERTER CIRCUIT FOR SWITCHING THREE VOLTAGE LEVELS
Abstract	The document specifies a method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem (1) provided for each phase (R,S,T), in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem (1) is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches (SI, S2, S3, S6) in the converter subsystem (1) or through the first and fifth power semiconductor switches (SI, S5) in the converter subsystem (1), and the bottom fault current path (B) running through the second, third, fourth and fifth power semiconductor switches (S2, S3, S4, S5) in the converter subsystem (1) or through the fourth and sixth power semiconductor switches (S4, S6) in ~he converter subsystem (1), and in which the power semiconductor switches (SI, S2, S3, S4, 35, S6) are switched on the basis of a fault switching sequence. To avoid phase shorting of all the phases of the converter circuit in order to achieve a safe operating state for the converter circuit in the event of a fault, the fault switching sequence in the even-: of detection of the top or the bottom fault current path (A, B) is initially followed by the detection's accompanying switching status of each power semiconductor switch (SI, S2, S3, S4, S5, S6) being recorded. In addition, in the event of detection of the top fault current path (A) the first power semiconductor switch (SI) and then the third power semiconductor (S3) are turned off, and in the event of detection of the bottom fault current path (B) the fourth power semiconductor switch (S4) and then the second power semiconductor (S2) are turned off. Figure 2a

Title of Invention

METHOD FOR FAULT HANDLING IN A CONVERTER CIRCUIT FOR SWITCHING THREE VOLTAGE LEVELS

Abstract

The document specifies a method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem (1) provided for each phase (R,S,T), in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem (1) is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches (SI, S2, S3, S6) in the converter subsystem (1) or through the first and fifth power semiconductor switches (SI, S5) in the converter subsystem (1), and the bottom fault current path (B) running through the second, third, fourth and fifth power semiconductor switches (S2, S3, S4, S5) in the converter subsystem (1) or through the fourth and sixth power semiconductor switches (S4, S6) in ~he converter subsystem (1), and in which the power semiconductor switches (SI, S2, S3, S4, 35, S6) are switched on the basis of a fault switching sequence. To avoid phase shorting of all the phases of the converter circuit in order to achieve a safe operating state for the converter circuit in the event of a fault, the fault switching sequence in the even-: of detection of the top or the bottom fault current path (A, B) is initially followed by the detection's accompanying switching status of each power semiconductor switch (SI, S2, S3, S4, S5, S6) being recorded. In addition, in the event of detection of the top fault current path (A) the first power semiconductor switch (SI) and then the third power semiconductor (S3) are turned off, and in the event of detection of the bottom fault current path (B) the fourth power semiconductor switch (S4) and then the second power semiconductor (S2) are turned off. Figure 2a

Full Text	Method for fault handling in a converter circuit for switching three voltage levels DESCRIPTION Technical Field The invention relates to the field of actuation methods for converter circuits. It is based on a method for fault handling in a converter circuit for switching three voltage levels in accordance with the precharacterizing part of claim 1. Prior Art Power semiconductor switches are currently being used increasingly ir. converter technology and particularly in converter circuits for switching three voltage levels. Such a converter circuit for switching three voltage levels is specified in DE 699 02 227 T2. Figure la shows a conventional converter subsystem for a phase of the converter circuit, where the converter subsystem shown in figure la corresponds to a converter subsystem from DE 699 02 227 T2. As figure la shows, the converter circuit is provided with a DC voltage circuit formed by two series-connected capacitors, the DC voltage circuir having a first principal connection and a second principal connection and a subconnection formed by the two adjacent and interconnected capacitors. The capacitance value of the two capacitors is usually chosen to be the same. The first principal connection and the second principal connection have a DC voltage applied between them, with half the DC voltage UDC/2 therefore being applied between the first principal connection and the subconnection, i.e. to the one capacitor, and half the DC voltage likewise being applied between the subconnection and the second principal connection, i.e. to the other capacitor. The DC voltage is denoted by UDC in figure la. Each converter subsystem in the converter circuit from DE 699 02 227 T2 or from figure la has a first, a second, a third, a fourth, a fifth and a sixth power semiconductor switch, the first, second, third and fourth power semiconductor switches being connected in series and the first power semiconductor switch being connected to the first principal connection and the fourth power semiconductor switch being connected to the second principal connection. The junction between the second power semiconductor switch and the third power semiconductor switch forms a phase connection. In addition, the fifth and sixth power semiconductor switches are connected in series and form a clamping switching group, the junction between the fifth power semiconductor switch and the sixth power semiconductor switch being connected to the subconnection, the fifth power semiconductor switch being connected to the junction between the first power semiconductor switch and the second power semiconductor switch, and the sixth power semiconductor switch being connected to the junction between the third power semiconductor switch and the fourth power semiconductor switch. The first, second, third and fourth power semiconductor switches are actuatable bidirectional power semiconductor switches, each formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. The fifth and sixth power semiconductor, switches in DE 699 02 227 T2 are nonactuatable unidirectional power semiconductor switches, each formed by a diode. In this case, the fifth and sixth power semiconductor switches form a passive clamping switching group. However, it is also conceivable for the fifth and sixth power semiconductor switches to be actuatable bidirectional power semiconductor switches, each formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. In that case, the fifth and sixth power semiconductor switches form an active clamping switching group. DE 699 02 227 T2 also specifies a method for fault handling in a converter circuit for switching three voltage levels. First of all, in the event of a fault occurring, for example on account of a faulty power semiconductor switch, it is detected whether the fault is in a top fault current path or in a bottom fault current path in the converter circuit. In this context, the top fault current path is defined by a fault current through the first, second, third and sixth power semiconductor switches or by a fault current through the first and fifth power semiconductor switches. In adiition, the bottom fault current path is defined by a fault current through the second, third, fourth and fifth power semiconductor switches or by a fault current through the fourth and sixth power semiconductor switches. For fault handling, a fault switching seguence is initially followed by the power semiconductor switch(es) which is/are in desaturation being turned off. This requires each power semiconductor switch being monitored for desaturation using a desaturation monitoring device. Such desaturation on the power semiconductor switch, particularly on the IGBT, occurs, by way of example, when a fault, such as a short, occurs in the principal current path, i.e. between the anode and the cathode or between the collector and the emitter of the IGBT. Other faults are naturally also conceivable. In such a fault situation, the current in the principal current path typically rises very quickly to a high current amplitude, which means that the current integral over time assumes inadmissibly high values. During this overcurrent which arises, the IGBT is driven to desaturation, with the anode/cathode voltage across the IGBT rising quickly, particularly to the value of the voltage which is to be connected. This achieves an extremely critical state for the IGBT: the IGBT firstly routes a high current (overcurrent.) through the anode and the cathode in the principal current path. Secondly, a high anode/cathode voltage is simultaneously applied between the anode and the cathode of the IGBT. This results in an extremely high instantaneous power loss which can destroy the IGBT. When the desaturated power semiconductor switch (es) has/have been turned off, the . power semiconductor switches are then switched on the basis of the fault switching sequence such that a phase short arises in each converter subsystem, i.e. the converter circuit is then shorted on each of its phases. The short on all phases of the converter circuit from DE 699 02 227 T2 allows a short circuit current to be produced in the converter subsystem affected by the fault and in the other converter subsystems, however, said short circuit current placing a burden on the power semiconductor switches. A power semiconductor switch burdened in this manner can therefore age more quickly or can even be damaged, which means that the availability of the converter circuit is severely impaired or at worst is eliminated. In addition, JP 11032426 discloses a method for fault handling in a converter circuit for switching three voltage levels. To avoid an overvoltage on one of the power semiconductor switches, detection of an overcurrent through the first and second power semiconductor switches and detection of an overcurrent through the third and fourth power semiconductor switches prompt first of all the first and fourth power semiconductor switches and then the second and third power semiconductor switches to be turned off. Illustration of the Invention It is therefore an object of the invention to specify a method for fault handling in a converter circuit for switching three voltage levels which essentially does not necessitate phase shorting of all the phases of the converter circuit in order to achieve a safe operating state for the converter circuit in the event of a fault. This object is achieved by the features of claim 1. The dependent claims specify advantageous developments of the invention. In the case of the inventive method for fault handling in a converter circuit for switching three voltage levels, the converter circuit has a converter subsystem provided for each phase and comprises a DC voltage circuit formed by two series-connected capacitors, where the DC voltage circuit comprises a first principal connection and a second principal connection and a subconnection formed by the two adjacent and interconnected capacitors. In addition, each converter subsystem has a first, a second, a third and a fourth actuatable bidirectional power semiconductor switch and a fifth and a sixth power semiconductor switch, the first, second, third and fourth power semiconductor switches being connected in series. The first power semiconductor switch is connected to the first principal connection and the fourth power semiconductor switch is connected to the second principal connection. In addition, the fifth and sixth power semiconductor switches are connected in series, the junction between the fifth power semiconductor switch and the sixth power semiconductor switch being connected to the subconnection, the fifth power semiconductor switch being connected to the junction between the first power semiconductor switch and the second power semiconductor switch, and the sixth power semiconductor switch being connected to the junction between the third power semiconductor switch and the fourth power semiconductor switch. The method additionally involves detection of a top fault current path or a bottom fault current path in the converter subsystem when a fault occurs in the converter subsystem, the top fault current path running through the first, second, third and sixth power semiconductor switches or through the first and fifth power semiconductor switches, and the bottom fault current path running through the second, third, fourth and fifth power semiconductor switches or through the fourth and sixth power semiconductor switches. In addition, the power semiconductor switches are switched on the basis of a fault switching sequence. In line with the invention, the fault switching sequence in the event of detection of the top or bottom fault current path is followed by the detection’s accompanying switching status of each actuatable bidirectional power semiconductor switch being recorded. The effect advantageously achieved by this is that there is first of all no further actuation of the actuatable bidirectional power semiconductor switches and hence also no switching action. In the event of detection of the top fault current path in the converted section system, the invention involves the first power semiconductor switch and then the third power semiconductor in the converted section system being turned off. In the event of detection of the bottom fault current parh in the converted section system, the invention also involves the fourth power semiconductor switch and then the second power semiconductor switch in the convened section system being turned off. Advantageously, the effect which may be achieved by this is that the converted section system affected by the fault and hence the entire converter circuit is put into a safe operating state. Preferably, the power semiconductor switches in the converter circuit’s converter systems which are not affected by the fault are turned off. This allows formation of a short circuit current in the converter subsystem affected by the fault and any other converted section systems to be largely avoided, which means that the power semiconductor switches in the converter subsystem affected by the fault and also those in the other converter subsystems are subjected to less of the burden. The ageing of the power semiconductor switches can therefore advantageously be slowed down and damage to the power semiconductor switches can be largely prevented. Overall, this increases the availability of the converter circuit. In addition, turning off the relevant two power semiconductor switches upon detection of a top or bottom fault current path advantageously produces a freewheeling path for the load current flowing in normal operation of the converter circuit, the DC voltage circuit also advantageously being protected against a shorz as a result of the relevant two power semiconductor switches being turned off. This and other objects, advantages and features of the present invention will become obvious from the detailed description of preferred embodiments of the invention which follows in conjunction with the drawing. Brief description of the drawings In the drawings: figure la shows a first embodiment of a conventional converter subsystem in a known converter circuit for switching three voltage levels, figure lb shows a second embodiment of a conventional converter subsystem in a known converter circuit for switching three voltage levels, figure 2a shows an example of current formation in a converter subsystem as shown in figure lb in the event of a fault in the first power semiconductor switch in the converter subsystem, figure 2b shows current formation in the event of a fault as shown in figure 2a following a fault switching sequence in line with the inventive method for fault handling, figure 3a shows an example of current formation in a converter subsystem as shown figure lb in the event of a fault in the second power semiconductor switch in the converter subsystem, figure 3b shows current formation in the event of a fault as shown in figure 3a following a fault switching sequence in line with the inventive method for fault handling, figure 4a shows an example of a logic circuit for detecting a top and a bottom fault current path for a converter subsystem as shown in figure la, and figure 4b shows an example of a logic circuit for detecting a top and a bottom fault current path for a converter subsystem as shown in figure lb. The reference symbols used in the drawing and their meaning are listed in summarized form in the list of reference symbols. In principle, identical parts have been provided with the same reference symbols in the figures- The embodiments described are examples of the subject matter of the invention and have no restrictive effect. Ways of implementing the invention Figure la shows the embodiment, already described in detail at the outset, of a conventional converter subsystem 1 in a known converter circuit for switching three voltage levels. The converter circuit has a converter subsystem 1 provided for each phase R, S, T, figure la showing just one converter subsystem 1 for the phase R. The converter circuit comprises a DC voltage circuit 2 formed by two series-connected capacitors, the DC voltage circuit 2 having a first principle connection 3 and a second principle connection 4 and a subconnection 5 formed by the two adj acent and interconnected capacitors. In addition, the converter subsystem 1 has a first, a second, a third and a fourth actuatable bi directional power semiconductor switch S1, S2, S3, S4 and a fifth and a sixth power semiconductor switch S5, S6. The respective actuable bidirectional power semiconductor switch S1, S2, S3, S4 is, in particular, formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. However, it is also conceivable for an actuatable bidirectional power semiconductor switch as mentioned above to be in the form of a power MOSFET with an additionally back-to-back connected diode, for example. In line with figure la, the fifth and sixth power semiconductor switches S5, S6 are nonactuatable unidirectional power semiconductor switches, each formed by a diode. In this case, the fifth and sixth power semiconductor switches form a passive clamping switching group. As figure la shows, the first, second, third and fourth power semiconductor switches S1, S2, S3, S4 are connected in series and the first power semiconductor switch S1 is connected to the first principal connection 3 and the fourth power semiconductor switch S4 is connected to the second principal connection 4. In addition, the fifth and sixth power semiconductor switches S5, S6 are connected in series, the junction between the fifth power semiconductor switch S5 and the sixth power semiconductor switch S6 being connected to the subconnection 5, the fifth power semiconductor switch S6 being connected to the junction between the first power semiconductor switch S1 and the second power semiconductor switch S2, and the sixth power semiconductor switch S6 being connected to the junction between the third power semiconductor switch S3 and the fourth power serdconductor switch S4. Figure lb shows a second embodiment of a conventional converter subsystem 1 in a known converter circuit for switching three voltage levels. In contrast to the first embodiment of the converter subsystem shown in figure la, the fifth and sixth power semiconductor switches S5, So are likewise actuatable bi directional power semiconductor switches, each formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. As figure lb shows, the fifth and sixth power semiconductor switches S5, S6 then form- an active clamping switching group. In the case of the inventive method for fault handling in the converter circuit for switching three voltage levels, the occurrence of a fault in the converter subsystem 1 now prompts a top fault current path A or a bottom fault current path B in the converter subsystem 1 to be detected, the top fault current path A running through the first, second, third and sixth power and then the third power semiconductor switch S3 being turned off. Furthermore, in the event of detection of the bottom fault current path B, the fault switching sequence is followed by the fourth power semiconductor switch S4 and then the second power semiconductor switch S2 being turned off. The converter subsystem 1 affected by the fault and hence the entire converter circuit are advantageously put into a safe operating state as a result of the measures described above -Formation of a short circuit current in the converter subsystem 1 affected by the fault and in the other converter subsystems 1 can therefore be avoided almost entirely, which means that the power semiconductor switches S1, S2, S3, S4, S5, S6 in the converter subsystem 1 affected by the fault and also those in the other converter subsystems 1 for the other phases R, S, T are subjected to less of a burden. The ageing of the power semiconductor switches S1, S2, S3, S4, S5, S6 can therefore advantageously be slowed down or damage to the power semiconductor switches S1, S2, S2, S4, S5, S6 can be largely prevented. Overall, this increases the availability of the converter circuit. In addition, maintenance of the converter circuit is simplified, since normally a fault damages fewer power semiconductor switches S1, S2, S3, S4, S5, S6 and hence it is also necessary to replace fewer power semiconductor switches S1, S2, S3, S4, S5, S6. In addition, turning off the relevant two power semiconductor switches S1, S2, S3, S4 upon detection of a top or bottom fault current path A, B advantageously produces a freewheeling path for the load current C flowing in normal operation of the converter circuit, the DC voltage circuit also advantageously being protected against a short as a result of the relevant two power semiconductor switches being turned off. In this regard, figure 2b shows, by way of example, current formation in the event of a fault as shown in figure 2a following the fault switching sequence, described in more detail above, in line with the inventive method for fault handling. In this figure, the first power semiconductor switch S1 and the third power semiconductor switch S3 are turned off, the fourth power semiconductor switch S4 being turned off anyway and the third and fourth power semiconductor switches S3, S4 respectively having half the DC voltage UDC/2 of the DC voltage circuit applied to them, and the load current C flowing through the faulty first and second power semiconductor switches S1, S2 as before the fault in the first power semiconductor switch S1. The overall effect achieved by this is therefore a safe operating state for the converter subsystem 1 affected by the fault and hence also for the entire converter circuit. By way of example, figure 3a shows current formation in the converter subsystem 1 shown in figure lb in the event of a fault in the second power semiconductor switch S2 of the converter subsystem 1, said faulty second power semiconductor switch S2 being identified by a star. In this case, one of the bottom fault current paths B forms through the second, third, fourth and fifth power semiconductor switches S2, S3, S4, S5, for example, as already mentioned above. In addition, the original current path, before the fault, for the load current C in respect of the phase is also shown in figure 3a for the sake of completeness. Finally, figure 3b shows current formation in the event of a fault as shown in figure 3a by way of example following the fault switching sequence, described in more detail above, on the basis of the inventive method for fault handling. In this figure, the fourth power semiconductor switch S4 and the second power semiconductor switch S2 are turned off, the first power semiconductor switch S1 being turned off anyway, the first and fourth power semiconductor switches S1, S4 respectively having half the DC voltage UDC/2 of the DC voltage circuit applied to them and the load current C flowing through the fifth and faulty second power semiconductor switches S5, S2, as before the fault in the second power semiconductor switch S2. The overall effect achieved by this is a safe operating state for the converter subsystem 1 affected by the fault and hence also for the entire converter circuit even when there is a fault in the bottom fault current path B. In figure lb, as already described above, the fifth and sixth power semiconductor switches S5, S6 are respectively an actuatable bidirectional power semiconductor switch. In the case of the inventive method, detection of the top fault current path A after the fault switching sequence now prompts the sixth power semiconductcr switch S6 to be turned on before the first power semiconductor switch S1 is turned off, particularly if the sixth power semiconductor switch S6 had not previously been turned on. In the event of detection of the bottom fault current path B, the fault switching sequence is followed by the fifth power semiconductor switch S5 being turned on before the fourth power semiconductor switch S4 is turned off, particularly if the fifth power semiconductor switch S5 had not previously been turned on. This achieves the aforementioned safe operating state for the converter subsystem shown ir_ figure lb and hence for the entire converter circuit. It has been found to be advantageous that in the event of detection of the top fault current path A the third power semiconductor switch S3 is turned off with a selectable delay time tv relative to the first power semiconductor switch S1, and that in the event of detection of the bottom fault current path B the second power semiconductor switch S2 is turned off with a selectable delay time tv relative to the fourth power semiconductor switch S4. this ensures that the first power semiconductor switch S1 is already turned off when the third power semiconductor switch S3 is turned off, and that the fourth power semiconductor switch S4 is already turned off when the second power semiconductor switch S2 is turned off. Preferably, the delay time tv is selected in the order of magnitude of between 1 µs and 5 µs. In line with the invention, the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, . S5, S6 in the converter circuit’s converter subsystems 1 which are not effected by the fault are turned off, which means that it is also possible to ensure that a short circuit current is not produced in the converter subsystems 1 which are not effected by the fault, as occurs in methods based on the prior art through shorting of all the phases R, S, T of the converter circuit. The power semiconductor switches S1, 52, S3, S4, S5, S€ in the converter subsystems 1 which are not effected by the fault are thus subjected to less of a burden in comparison with known methods. Preferably, when the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 in the converter circuit’s converter subsystems 1 which are not effected by the fault are turned off, the respective “outer” actuatable bidirectional power semiconductor switch S1, S4, i.e. the first or the fourth actuatable bidirectional power semiconductor switch S1, S4, is turned off before the associated “inner” actuatable bidirectional power semiconductor switch S2, S3, i.e. the second or third actuatable bidirectional semiconductor power switch S2, S3. The text below discusses the detection options for the top and bottom fault current paths A, B in more detail. To detect the top or bottom fault current path A, B, the invention involves each actuatable bidirectional power semiconductor switch S1, S2, S3, S.4, S5, S6 in the converter subcircuits 1 for the phases R, S, T being monitored for desaturation and also a current through the subconnection 5 in each converter subcircuit 1 being monitored for its direction. To monitor the direction of the current through the subconnection 5, the current is preferably monitored for a threshold value or is compared with a threshold value in order to ensure that the direction of the current is detected even when the current is subjected to noise. The top fault current path A is detected when the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch S1, S2, S3, S5, S6 is in desaturation and a current through the subconnection 5 is detected in the direction of the DC voltage circuit 2. By contrast, the bottom fault current path B is detected when the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch S2, S3, S4, S5, S6 is in desaturation and there is a current through the subconnection 5 from the direction of the DC voltage circuit 2. To monitor the direction of flow of the current through the subconnection 5, the subconnection 5 preferably has an appropriate sensor provided on it. As an alternative to the detection of the top or bottom fault current path A,’ B described above, each actuatable bidirectional power semiconductor switch S1, S2, S3, S4, S5, S6 is likewise monitored for desaturation, but with a current through the first principal connection 3 and a current through the second principal connection 4 being monitored. To monitor the respective current through the first principal connection 3 or through the second principal connection 4, the respective current is preferably monitored for a threshold value in order to ensure detection of the respective current even when the current is subject to noise. The top fault current path A is detected when the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch S1, S2, S3, S5, S6 is in desaturation and a current is detected through the first principal connection 3. By contrast, the bottom fault current path B is detected when the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch S2, S3, S4, S5, S6 is in desaturation and there is a current through the second principal connection 4. To monitor the current in the top or bottom fault current path A, B, the first principal connection 3 and the second principal connection 4 preferably have an appropriate sensor provided on them which needs to be capable of detecting only a current but not a direction for the current, A current sensor of this kind is of simple and hence robust design. As an alternative to the detection of the top or bottom fault current path A, B described above, the anode/cathode voltage Uce of each actuatable bidirectional power semiconductor switch S1, S2, S3, SAr S5, S6 in general is first of all monitored for a threshold value Uce,th. Specifically, this anode/cathode voltage monitoring is performed in the acruatable bidirectional power semiconductor switches S1, S2, S3 and S4 in the case of the converter subsystem 1 shown in figure la and in the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5 and S6 in the case of the converter subsystem 1 shown in figure 1b. Figure 4a shows an exemplary logic circuit for detecting a top and a bottom fault current path A, B for the converter subsystem 1 shown in figure la. In addition, figure 4b shows an exemplary logic circuit for detecting a top and a bottom fault current path for the converter subsystem 1 shown in figure lb. The switching status signals SS1, SS2, SS3 and SS4 shown in figure 4a for the actuatable bidirectional power semiconductor switches S1, S2, S3 and S4 and the switching status signals SS1, SS2, SS3, SS4, SS5 and SS6 shown in figure 4b for the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5 and S6 are logical variables, the switching status signal SS1, SS2, SS3, SS4, SS5, SS6 being logic “0” for a turned-off associated actuatable bidirectional power semiconductor switch S1, S2, S3, S4, S5, S6 and logic “1” for a turned-on associated actuatable bidirectional power semiconductor switch S1, S2, S3, S4, S5, S6. In addition, the threshold value signals SUcel, SUce2, SUce3 and SUce4 shown in figure 4a for the actuatable bidirectional power semiconductor switches S1, S2, S3, S4 monitored for the threshold value Uce,th of the associated anode/cathode voltage Uce and the threshold value signals SUcel, SUce2, SUce3, SUce4, SDce5 and SUce6 shown in figure 4b for the associated actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 are logic variables, the threshold value signal SUcel, SUce2, SUce3, SUce4, SUce5, SUce6 being logic “0” for an anode/cathode voltage Uce of the relevant power semiconductor switch S1, S2, S3, S4, S5, S6 which exceeds the threshold value SUce and logic “1” for an anode/cathode voltage Uce of the relevant power semiconductor switch S1, S2, S3, S4, S5, S6 which undershoots the threshold value Uce,th. In line with the invention, the top fault current path A is now detected when the threshold value Uce,th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 turned on and the fourth actuatable bidirectional power semiconductor switch S4 turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce, th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 turned on and the first actuatable bidirectional power semiconductor switch SI turned on. In addition, in line with the invention, the top fault current path A is also detected when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4 turned off and the fourth actuatable bidirectional power semiconductor switch S4 turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches SI, S2, S3, S4 turned off and the first actuatable bidirectional power semiconductor switch S1 turned on. By contrast, in line with the invention, the bottom fault current path 3 is detected when the threshold value Uce, th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 turned on and the first actuatable bidirectional power semiconductor switch S1 turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce,th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4, 35, S6 “turned on and the fourth actuatable bidirectional power semiconductor switch S4 turned on. In addition, in line with the invention, the bottom fault current path B is also detected when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches SI, S2, S3, S4 turned off and the first actuatable bidirectional power semiconductor switch SI turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches SI, S2, S3, S4 turned off and the fourth actuatable bidirectional power semiconductor switch S4 turned on. Advantageously, this type of detection of the top and bottom fault current paths A, B makes it possible to dispense with current sensors for detection completely, which means that the wiring and materials involvement can advantageously be reduced and the converter subsystem can thus be of simple and less expensive design. Furthermore, the susceptibility of the converter subsystem 1 and hence of the entire converter circuit to interference is advantageously reduced, which results in increased availability for the entire converter circuit. List of reference symbols 1 Converter subsystem 2 DC voltage circuit 3 First principal connection 4 Second principal connection 5 Subconnection S1 First power semiconductor switch S2 Second power semiconductor switch S3 Third power semiconductor switch S4 Fourth power semiconductor switch S5 Fifth power semiconductor switch S6 Sixth power semiconductor switch A Top fault current path B Bottom fault current path C Load current path PATENT CLAIMS 1. A method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem (1) provided for each phase (R,S,T) and comprises a DC voltage circuit (2) formed by two series-connected capacitors, where the DC voltage circuit (2) comprises a first principal connection (3) and a second principal connection (4) and a subconnection (5) formed by the two adjacent and interconnected capacitors, and which system has a first, a second, a third and a fourth actuatable bidirectional power semiconductor switch (SI, S2, S3, S4) and a fifth and a sixth power semiconductor switch (S5, S6), the first, second, third and fourth power semiconductor switches {SI, S2, S3, S4) being connected in series and the first power semiconductor switch (SI) being connected to the first principal connection (3) and the fourth power semiconductor switch (S4) being connected to the second principal connection (4), and where the fifth and sixth power semiconductor switches (S5, S6) are connected in series, the junction between the fifth power semiconductor switch (S5) and the sixth power semiconductor switch (S6) is connected to the subconnection (5), the fifth power semiconductor switch (S6) is connected to the junction between the first power semiconductor switch (SI) and the second power semiconductor switch (S2), and the sixth power semiconductor switch (S6) is connected to the junction between the third power semiconductor switch (S3) and the fourth power semiconductor switch (S4), in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem (1) is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches (SI, S2, S3, S6) or through the first and fifth power semiconductor switches (SI, S5) , and the bottom fault current path running through the second, third, fourth and fifth power semiconductor switches (S2, S3, S4, S5) or through the fourth and sixth power semiconductor switches (S4, S6), and in which the actuatable bidirectional power semiconductor switches (SI, S2, S3, S4) are switched on the basis of a fault switching sequence, characterized in that the fault switching sequence in the event of detection of the top or the bottom fault current path (A, B) is followed by the detection’s accompanying switching status of each actuatable bidirectional power semiconductor switch (SI, S2, S3, S4) being recorded, in that in the event of detection of the top fault current path (A) the first power semiconductor switch (SI) and then the third power semiconductor (S3) are turned off, and in that in the event of detection of the bottom fault current path (B) the fourth power semiconductor switch (S4) and then the second power semiconductor (S2) are turned off. 2. The method as claimed in claim 1, characterized in that the fifth and sixth power semiconductor switches (S5, S6) are actuatable bidirectional power semiconductor switches, and in the event of detection of the top fault current path (A) the sixth power semiconductor switch (S6) is turned on before the first power semiconductor switch (SI) is turned off, and in the event of detection of the bottom fault current path (B) the fifth power semiconductor switch (S5) is turned on before the fourth power semiconductor switch (4) is turned off. 3, The method as claimed in claim 1 or 2, characterized in that in the event of detection of the top fault current path (A) the third power semiconductor switch (S3) is turned off with a selectable delay time (tv) relative to the first power semiconductor switch (Si), and in that in the event of detection of the bottom fault current path (B) the second power semiconductor switch (S2) is turned off with a selectable delay time (tv) relative to the fourth power semiconductor switch (S4). 4. The method as claimed in claim 3, characterized in that the delay time (tv) is selected in the order of magnitude of between lµs and 5µs. 5. The method as claimed in one of the preceding claims, characterized in that the actuatable bidirectional power semiconductor switches (Si, S2, S3, S4, S5, S6) in the converter subsystems (1) which are not affected by the fault are turned off. 6. The method as claimed in one of claims 1 to 5, characterized in that to detect the top or bottom fault current path (A, B) each actuatable bidirectional power semiconductor switch (SI, S2, S3, S4, S5, S6) is monitored for desaturation, and in that a current through the subconnection (5) is monitored for its direction. 7. The method as claimed in claim 6, characterized in that the top fault current path (A) is detected in the case of desaturation of the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch (SI, S2, S3, 34, S5, S6) and a current through the subconnection (5) in the direction of the DC voltage circuit (5), and in that the bottom fault current path (B) is detected in the case of desaturation of the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) and a current through the subconnection (5) from the direction of the DC voltage circuit (5) . 8. The method as claimed in one of claims 1 to 5, characterized in that to detect the/ top or bottom fault current path (A, B) each actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) is monitored for desaturation, and in that a current through the first principal connection (3) and a current through the second principal connection (4) are monitored. 9. The method as claimed in claim 8, characterized in that the top fault current path (A) is detected in the case of desaturation of the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch (SI, S2, S3, 35, S6) and a current through the first principal connection (3), and in that the bottom fault current path (3) is detected in the case of desaturation of the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) and a current through the second principal connection (4). 10. The method as claimed in one of claims 1 to 5, characterized in that the anode/cathode voltage (Uce) of each actuatable bidirectional power semiconductor switch (SI, S2, S3, S4, S5, S6) is monitored for a threshold value (Uce, th), in that the top fault current path (A) is detected (al) when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and the fourth actuatable bidirectional power semiconductor switch (S4) turned off when the threshold value (Uce, th) is exceeded, or (bl) when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and the first actuatable bidirectional power semiconductor switch (SI) turned on, or (cl) when the threshold value (Uce,th) is undershot with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4) turned off and the fourth actuatable bidirectional power semiconductor switch (S4) turned off when the threshold value (Uce,th) is exceeded, or (dl) when the threshold value (Uce,th) is undershot with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4) turned off and the first actuatable bidirectional power semiconductor switch (SI) turned on, and in that the bottom fault current path (B) is detected (a2; when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and the first actuatable bidirectional power semiconductor switch (SI) turned off when the threshold value (Uce,th) is exceeded, or (b2; when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and a fourth actuatable bidirectional power semiconductor switch (S4) turned on, or (c2) when the threshold value (Uce,th) is undershot with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4) turned off and the first actuatable bidirectional power semiconductor switch (SI) turned off when the threshold value (Uce,th) is exceeded, or semiconductor switch (S3) is turned off with a selectable delay time (tv) relative to the first power semiconductor switch (SI) , and in that in the event of detection of the bottom fault current path (B) the second power semiconductor switch (S2) is turned off with a selectable delay time (tv) relative to the fourth power semiconductor switch (S4). 4. The method as claimed in claim 3, characterized in that the delay time (tv) is selected in the order of magnitude of between lµs and 5JXS. 5. The method as claimed in one of the preceding claims, characterized in that the actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) in the converter subsystems (1) which are not affected by the fault are turned off. 6. The method as claimed in one of claims 1 to 5, characterized in that to detect the top or bottom fault current path (A, B) each actuatable bidirectional power semiconductor switch (SI, S2, S3, . S4, S5, S6) is monitored for desaturation, and in that a current through the subconnection (5) is monitored for its direction. 7. The method as claimed in claim 6, characterized in that the top fault current path (A) is detected in the case of desaturation of the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch (SI, S2, S3, S4, S5, S6) and a current through the subconnection (5) in the direction of the DC voltage circuit (5), and in that the bottom fault current path (B) is detected in the case of desaturation of the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) and a current

Full Text

Method for fault handling in a converter circuit for
switching three voltage levels
DESCRIPTION Technical Field
The invention relates to the field of actuation methods for converter circuits. It is based on a method for fault handling in a converter circuit for switching three voltage levels in accordance with the precharacterizing part of claim 1.
Prior Art
Power semiconductor switches are currently being used increasingly ir. converter technology and particularly in converter circuits for switching three voltage levels. Such a converter circuit for switching three voltage levels is specified in DE 699 02 227 T2. Figure la shows a conventional converter subsystem for a phase of the converter circuit, where the converter subsystem shown in figure la corresponds to a converter subsystem from DE 699 02 227 T2. As figure la shows, the converter circuit is provided with a DC voltage circuit formed by two series-connected capacitors, the DC voltage circuir having a first principal connection and a second principal connection and a subconnection formed by the two adjacent and interconnected capacitors. The capacitance value of the two capacitors is usually chosen to be the same. The first principal connection and the second principal connection have a DC voltage applied between them, with half the DC voltage UDC/2 therefore being applied between the first principal connection and the subconnection, i.e. to the one capacitor, and half the DC voltage likewise being applied between the subconnection and the second

principal connection, i.e. to the other capacitor. The DC voltage is denoted by UDC in figure la.
Each converter subsystem in the converter circuit from DE 699 02 227 T2 or from figure la has a first, a second, a third, a fourth, a fifth and a sixth power semiconductor switch, the first, second, third and fourth power semiconductor switches being connected in series and the first power semiconductor switch being connected to the first principal connection and the fourth power semiconductor switch being connected to the second principal connection. The junction between the second power semiconductor switch and the third power semiconductor switch forms a phase connection. In addition, the fifth and sixth power semiconductor switches are connected in series and form a clamping switching group, the junction between the fifth power semiconductor switch and the sixth power semiconductor switch being connected to the subconnection, the fifth power semiconductor switch being connected to the junction between the first power semiconductor switch and the second power semiconductor switch, and the sixth power semiconductor switch being connected to the junction between the third power semiconductor switch and the fourth power semiconductor switch. The first, second, third and fourth power semiconductor switches are actuatable bidirectional power semiconductor switches, each formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. The fifth and sixth power semiconductor, switches in DE 699 02 227 T2 are nonactuatable unidirectional power semiconductor switches, each formed by a diode. In this case, the fifth and sixth power semiconductor switches form a passive clamping switching group. However, it is also conceivable for the fifth and sixth power semiconductor switches to be actuatable bidirectional power semiconductor switches, each formed by an insulated

gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. In that case, the fifth and sixth power semiconductor switches form an active clamping switching group.
DE 699 02 227 T2 also specifies a method for fault handling in a converter circuit for switching three voltage levels. First of all, in the event of a fault occurring, for example on account of a faulty power semiconductor switch, it is detected whether the fault is in a top fault current path or in a bottom fault current path in the converter circuit. In this context, the top fault current path is defined by a fault current through the first, second, third and sixth power semiconductor switches or by a fault current through the first and fifth power semiconductor switches. In adiition, the bottom fault current path is defined by a fault current through the second, third, fourth and fifth power semiconductor switches or by a fault current through the fourth and sixth power semiconductor switches. For fault handling, a fault switching seguence is initially followed by the power semiconductor switch(es) which is/are in desaturation being turned off. This requires each power semiconductor switch being monitored for desaturation using a desaturation monitoring device. Such desaturation on the power semiconductor switch, particularly on the IGBT, occurs, by way of example, when a fault, such as a short, occurs in the principal current path, i.e. between the anode and the cathode or between the collector and the emitter of the IGBT. Other faults are naturally also conceivable. In such a fault situation, the current in the principal current path typically rises very quickly to a high current amplitude, which means that the current integral over time assumes inadmissibly high values. During this overcurrent which arises, the IGBT is driven to desaturation, with the anode/cathode voltage across the

IGBT rising quickly, particularly to the value of the voltage which is to be connected. This achieves an extremely critical state for the IGBT: the IGBT firstly routes a high current (overcurrent.) through the anode and the cathode in the principal current path. Secondly, a high anode/cathode voltage is simultaneously applied between the anode and the cathode of the IGBT. This results in an extremely high instantaneous power loss which can destroy the IGBT. When the desaturated power semiconductor switch (es) has/have been turned off, the . power semiconductor switches are then switched on the basis of the fault switching sequence such that a phase short arises in each converter subsystem, i.e. the converter circuit is then shorted on each of its phases.
The short on all phases of the converter circuit from DE 699 02 227 T2 allows a short circuit current to be produced in the converter subsystem affected by the fault and in the other converter subsystems, however, said short circuit current placing a burden on the power semiconductor switches. A power semiconductor switch burdened in this manner can therefore age more quickly or can even be damaged, which means that the availability of the converter circuit is severely impaired or at worst is eliminated.
In addition, JP 11032426 discloses a method for fault handling in a converter circuit for switching three voltage levels. To avoid an overvoltage on one of the power semiconductor switches, detection of an overcurrent through the first and second power semiconductor switches and detection of an overcurrent through the third and fourth power semiconductor switches prompt first of all the first and fourth power semiconductor switches and then the second and third power semiconductor switches to be turned off.

Illustration of the Invention
It is therefore an object of the invention to specify a method for fault handling in a converter circuit for switching three voltage levels which essentially does not necessitate phase shorting of all the phases of the converter circuit in order to achieve a safe operating state for the converter circuit in the event of a fault. This object is achieved by the features of claim 1. The dependent claims specify advantageous developments of the invention.
In the case of the inventive method for fault handling in a converter circuit for switching three voltage levels, the converter circuit has a converter subsystem provided for each phase and comprises a DC voltage circuit formed by two series-connected capacitors, where the DC voltage circuit comprises a first principal connection and a second principal connection and a subconnection formed by the two adjacent and interconnected capacitors. In addition, each converter subsystem has a first, a second, a third and a fourth actuatable bidirectional power semiconductor switch and a fifth and a sixth power semiconductor switch, the first, second, third and fourth power semiconductor switches being connected in series. The first power semiconductor switch is connected to the first principal connection and the fourth power semiconductor switch is connected to the second principal connection. In addition, the fifth and sixth power semiconductor switches are connected in series, the junction between the fifth power semiconductor switch and the sixth power semiconductor switch being connected to the subconnection, the fifth power semiconductor switch being connected to the junction between the first power semiconductor switch and the second power semiconductor switch, and the sixth power semiconductor switch being connected to the junction between the third power

semiconductor switch and the fourth power semiconductor switch. The method additionally involves detection of a top fault current path or a bottom fault current path in the converter subsystem when a fault occurs in the converter subsystem, the top fault current path running through the first, second, third and sixth power semiconductor switches or through the first and fifth power semiconductor switches, and the bottom fault current path running through the second, third, fourth and fifth power semiconductor switches or through the fourth and sixth power semiconductor switches. In addition, the power semiconductor switches are switched on the basis of a fault switching sequence. In line with the invention, the fault switching sequence in the event of detection of the top or bottom fault current path is followed by the detection’s accompanying switching status of each actuatable bidirectional power semiconductor switch being recorded. The effect advantageously achieved by this is that there is first of all no further actuation of the actuatable bidirectional power semiconductor switches and hence also no switching action. In the event of detection of the top fault current path in the converted section system, the invention involves the first power semiconductor switch and then the third power semiconductor in the converted section system being turned off. In the event of detection of the bottom fault current parh in the converted section system, the invention also involves the fourth power semiconductor switch and then the second power semiconductor switch in the convened section system being turned off. Advantageously, the effect which may be achieved by this is that the converted section system affected by the fault and hence the entire converter circuit is put into a safe operating state. Preferably, the power semiconductor switches in the converter circuit’s converter systems which are not affected by the fault are turned off. This allows formation of a short

circuit current in the converter subsystem affected by the fault and any other converted section systems to be largely avoided, which means that the power semiconductor switches in the converter subsystem affected by the fault and also those in the other converter subsystems are subjected to less of the burden. The ageing of the power semiconductor switches can therefore advantageously be slowed down and damage to the power semiconductor switches can be largely prevented. Overall, this increases the availability of the converter circuit.
In addition, turning off the relevant two power semiconductor switches upon detection of a top or bottom fault current path advantageously produces a freewheeling path for the load current flowing in normal operation of the converter circuit, the DC voltage circuit also advantageously being protected against a shorz as a result of the relevant two power semiconductor switches being turned off.
This and other objects, advantages and features of the present invention will become obvious from the detailed description of preferred embodiments of the invention which follows in conjunction with the drawing.
Brief description of the drawings In the drawings:
figure la shows a first embodiment of a
conventional converter subsystem in a known converter circuit for switching three voltage levels,
figure lb shows a second embodiment of a
conventional converter subsystem in a known

converter circuit for switching three voltage levels,
figure 2a shows an example of current formation in
a converter subsystem as shown in figure lb in the event of a fault in the first power semiconductor switch in the converter subsystem,
figure 2b shows current formation in the event of
a fault as shown in figure 2a following a fault switching sequence in line with the inventive method for fault handling,
figure 3a shows an example of current formation in
a converter subsystem as shown figure lb in the event of a fault in the second power semiconductor switch in the converter subsystem,
figure 3b shows current formation in the event of
a fault as shown in figure 3a following a fault switching sequence in line with the inventive method for fault handling,
figure 4a shows an example of a logic circuit for
detecting a top and a bottom fault current path for a converter subsystem as shown in figure la, and
figure 4b shows an example of a logic circuit for
detecting a top and a bottom fault current path for a converter subsystem as shown in figure lb.
The reference symbols used in the drawing and their meaning are listed in summarized form in the list of reference symbols. In principle, identical parts have

been provided with the same reference symbols in the figures- The embodiments described are examples of the subject matter of the invention and have no restrictive
effect.
Ways of implementing the invention
Figure la shows the embodiment, already described in detail at the outset, of a conventional converter subsystem 1 in a known converter circuit for switching three voltage levels. The converter circuit has a converter subsystem 1 provided for each phase R, S, T, figure la showing just one converter subsystem 1 for the phase R. The converter circuit comprises a DC voltage circuit 2 formed by two series-connected capacitors, the DC voltage circuit 2 having a first principle connection 3 and a second principle connection 4 and a subconnection 5 formed by the two adj acent and interconnected capacitors. In addition, the converter subsystem 1 has a first, a second, a third and a fourth actuatable bi directional power semiconductor switch S1, S2, S3, S4 and a fifth and a sixth power semiconductor switch S5, S6. The respective actuable bidirectional power semiconductor switch S1, S2, S3, S4 is, in particular, formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. However, it is also conceivable for an actuatable bidirectional power semiconductor switch as mentioned above to be in the form of a power MOSFET with an additionally back-to-back connected diode, for example. In line with figure la, the fifth and sixth power semiconductor switches S5, S6 are nonactuatable unidirectional power semiconductor switches, each formed by a diode. In this case, the fifth and sixth power semiconductor switches form a passive clamping switching group.

As figure la shows, the first, second, third and fourth power semiconductor switches S1, S2, S3, S4 are connected in series and the first power semiconductor switch S1 is connected to the first principal connection 3 and the fourth power semiconductor switch S4 is connected to the second principal connection 4. In addition, the fifth and sixth power semiconductor switches S5, S6 are connected in series, the junction between the fifth power semiconductor switch S5 and the sixth power semiconductor switch S6 being connected to the subconnection 5, the fifth power semiconductor switch S6 being connected to the junction between the first power semiconductor switch S1 and the second power semiconductor switch S2, and the sixth power semiconductor switch S6 being connected to the junction between the third power semiconductor switch S3 and the fourth power serdconductor switch S4.
Figure lb shows a second embodiment of a conventional converter subsystem 1 in a known converter circuit for switching three voltage levels. In contrast to the first embodiment of the converter subsystem shown in figure la, the fifth and sixth power semiconductor switches S5, So are likewise actuatable bi directional power semiconductor switches, each formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. As figure lb shows, the fifth and sixth power semiconductor switches S5, S6 then form- an active clamping switching group.
In the case of the inventive method for fault handling in the converter circuit for switching three voltage levels, the occurrence of a fault in the converter subsystem 1 now prompts a top fault current path A or a bottom fault current path B in the converter subsystem 1 to be detected, the top fault current path A running through the first, second, third and sixth power

and then the third power semiconductor switch S3 being turned off. Furthermore, in the event of detection of the bottom fault current path B, the fault switching sequence is followed by the fourth power semiconductor switch S4 and then the second power semiconductor switch S2 being turned off. The converter subsystem 1 affected by the fault and hence the entire converter circuit are advantageously put into a safe operating state as a result of the measures described above -Formation of a short circuit current in the converter subsystem 1 affected by the fault and in the other converter subsystems 1 can therefore be avoided almost entirely, which means that the power semiconductor switches S1, S2, S3, S4, S5, S6 in the converter subsystem 1 affected by the fault and also those in the other converter subsystems 1 for the other phases R, S, T are subjected to less of a burden. The ageing of the power semiconductor switches S1, S2, S3, S4, S5, S6 can therefore advantageously be slowed down or damage to the power semiconductor switches S1, S2, S2, S4, S5, S6 can be largely prevented. Overall, this increases the availability of the converter circuit. In addition, maintenance of the converter circuit is simplified, since normally a fault damages fewer power semiconductor switches S1, S2, S3, S4, S5, S6 and hence it is also necessary to replace fewer power semiconductor switches S1, S2, S3, S4, S5, S6.
In addition, turning off the relevant two power semiconductor switches S1, S2, S3, S4 upon detection of a top or bottom fault current path A, B advantageously produces a freewheeling path for the load current C flowing in normal operation of the converter circuit, the DC voltage circuit also advantageously being protected against a short as a result of the relevant two power semiconductor switches being turned off. In this regard, figure 2b shows, by way of example, current formation in the event of a fault as shown in

figure 2a following the fault switching sequence, described in more detail above, in line with the inventive method for fault handling. In this figure, the first power semiconductor switch S1 and the third power semiconductor switch S3 are turned off, the fourth power semiconductor switch S4 being turned off anyway and the third and fourth power semiconductor switches S3, S4 respectively having half the DC voltage UDC/2 of the DC voltage circuit applied to them, and the load current C flowing through the faulty first and second power semiconductor switches S1, S2 as before the fault in the first power semiconductor switch S1. The overall effect achieved by this is therefore a safe operating state for the converter subsystem 1 affected by the fault and hence also for the entire converter circuit.
By way of example, figure 3a shows current formation in the converter subsystem 1 shown in figure lb in the event of a fault in the second power semiconductor switch S2 of the converter subsystem 1, said faulty second power semiconductor switch S2 being identified by a star. In this case, one of the bottom fault current paths B forms through the second, third, fourth and fifth power semiconductor switches S2, S3, S4, S5, for example, as already mentioned above. In addition, the original current path, before the fault, for the load current C in respect of the phase is also shown in figure 3a for the sake of completeness. Finally, figure 3b shows current formation in the event of a fault as shown in figure 3a by way of example following the fault switching sequence, described in more detail above, on the basis of the inventive method for fault handling. In this figure, the fourth power semiconductor switch S4 and the second power semiconductor switch S2 are turned off, the first power semiconductor switch S1 being turned off anyway, the first and fourth power semiconductor switches S1, S4

respectively having half the DC voltage UDC/2 of the DC voltage circuit applied to them and the load current C flowing through the fifth and faulty second power semiconductor switches S5, S2, as before the fault in the second power semiconductor switch S2. The overall effect achieved by this is a safe operating state for the converter subsystem 1 affected by the fault and hence also for the entire converter circuit even when there is a fault in the bottom fault current path B.
In figure lb, as already described above, the fifth and sixth power semiconductor switches S5, S6 are respectively an actuatable bidirectional power semiconductor switch. In the case of the inventive method, detection of the top fault current path A after the fault switching sequence now prompts the sixth power semiconductcr switch S6 to be turned on before the first power semiconductor switch S1 is turned off, particularly if the sixth power semiconductor switch S6 had not previously been turned on. In the event of detection of the bottom fault current path B, the fault switching sequence is followed by the fifth power semiconductor switch S5 being turned on before the fourth power semiconductor switch S4 is turned off, particularly if the fifth power semiconductor switch S5 had not previously been turned on. This achieves the aforementioned safe operating state for the converter subsystem shown ir_ figure lb and hence for the entire converter circuit.
It has been found to be advantageous that in the event of detection of the top fault current path A the third power semiconductor switch S3 is turned off with a selectable delay time tv relative to the first power semiconductor switch S1, and that in the event of detection of the bottom fault current path B the second power semiconductor switch S2 is turned off with a selectable delay time tv relative to the fourth power

semiconductor switch S4. this ensures that the first power semiconductor switch S1 is already turned off when the third power semiconductor switch S3 is turned off, and that the fourth power semiconductor switch S4 is already turned off when the second power semiconductor switch S2 is turned off. Preferably, the delay time tv is selected in the order of magnitude of between 1 µs and 5 µs.
In line with the invention, the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, . S5, S6 in the converter circuit’s converter subsystems 1 which are not effected by the fault are turned off, which means that it is also possible to ensure that a short circuit current is not produced in the converter subsystems 1 which are not effected by the fault, as occurs in methods based on the prior art through shorting of all the phases R, S, T of the converter circuit. The power semiconductor switches S1, 52, S3, S4, S5, S€ in the converter subsystems 1 which are not effected by the fault are thus subjected to less of a burden in comparison with known methods. Preferably, when the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 in the converter circuit’s converter subsystems 1 which are not effected by the fault are turned off, the respective “outer” actuatable bidirectional power semiconductor switch S1, S4, i.e. the first or the fourth actuatable bidirectional power semiconductor switch S1, S4, is turned off before the associated “inner” actuatable bidirectional power semiconductor switch S2, S3, i.e. the second or third actuatable bidirectional semiconductor power switch S2, S3.
The text below discusses the detection options for the top and bottom fault current paths A, B in more detail.

To detect the top or bottom fault current path A, B, the invention involves each actuatable bidirectional power semiconductor switch S1, S2, S3, S.4, S5, S6 in the converter subcircuits 1 for the phases R, S, T being monitored for desaturation and also a current through the subconnection 5 in each converter subcircuit 1 being monitored for its direction. To monitor the direction of the current through the subconnection 5, the current is preferably monitored for a threshold value or is compared with a threshold value in order to ensure that the direction of the current is detected even when the current is subjected to noise. The top fault current path A is detected when the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch S1, S2, S3, S5, S6 is in desaturation and a current through the subconnection 5 is detected in the direction of the DC voltage circuit 2. By contrast, the bottom fault current path B is detected when the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch S2, S3, S4, S5, S6 is in desaturation and there is a current through the subconnection 5 from the direction of the DC voltage circuit 2. To monitor the direction of flow of the current through the subconnection 5, the subconnection 5 preferably has an appropriate sensor provided on it.
As an alternative to the detection of the top or bottom fault current path A,’ B described above, each actuatable bidirectional power semiconductor switch S1, S2, S3, S4, S5, S6 is likewise monitored for desaturation, but with a current through the first principal connection 3 and a current through the second principal connection 4 being monitored. To monitor the respective current through the first principal connection 3 or through the second principal connection 4, the respective current is preferably monitored for a threshold value in order to ensure detection of the

respective current even when the current is subject to noise. The top fault current path A is detected when the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch S1, S2, S3, S5, S6 is in desaturation and a current is detected through the first principal connection 3. By contrast, the bottom fault current path B is detected when the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch S2, S3, S4, S5, S6 is in desaturation and there is a current through the second principal connection 4. To monitor the current in the top or bottom fault current path A, B, the first principal connection 3 and the second principal connection 4 preferably have an appropriate sensor provided on them which needs to be capable of detecting only a current but not a direction for the current, A current sensor of this kind is of simple and hence robust design.
As an alternative to the detection of the top or bottom fault current path A, B described above, the anode/cathode voltage Uce of each actuatable bidirectional power semiconductor switch S1, S2, S3, SAr S5, S6 in general is first of all monitored for a threshold value Uce,th. Specifically, this anode/cathode voltage monitoring is performed in the acruatable bidirectional power semiconductor switches S1, S2, S3 and S4 in the case of the converter subsystem 1 shown in figure la and in the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5 and S6 in the case of the converter subsystem 1 shown in figure 1b. Figure 4a shows an exemplary logic circuit for detecting a top and a bottom fault current path A, B for the converter subsystem 1 shown in figure la. In addition, figure 4b shows an exemplary logic circuit for detecting a top and a bottom fault current path for the converter subsystem 1 shown in figure lb. The switching status signals SS1, SS2, SS3

and SS4 shown in figure 4a for the actuatable bidirectional power semiconductor switches S1, S2, S3 and S4 and the switching status signals SS1, SS2, SS3, SS4, SS5 and SS6 shown in figure 4b for the actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5 and S6 are logical variables, the switching status signal SS1, SS2, SS3, SS4, SS5, SS6 being logic “0” for a turned-off associated actuatable bidirectional power semiconductor switch S1, S2, S3, S4, S5, S6 and logic “1” for a turned-on associated actuatable bidirectional power semiconductor switch S1, S2, S3, S4, S5, S6. In addition, the threshold value signals SUcel, SUce2, SUce3 and SUce4 shown in figure 4a for the actuatable bidirectional power semiconductor switches S1, S2, S3, S4 monitored for the threshold value Uce,th of the associated anode/cathode voltage Uce and the threshold value signals SUcel, SUce2, SUce3, SUce4, SDce5 and SUce6 shown in figure 4b for the associated actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 are logic variables, the threshold value signal SUcel, SUce2, SUce3, SUce4, SUce5, SUce6 being logic “0” for an anode/cathode voltage Uce of the relevant power semiconductor switch S1, S2, S3, S4, S5, S6 which exceeds the threshold value SUce and logic “1” for an anode/cathode voltage Uce of the relevant power semiconductor switch S1, S2, S3, S4, S5, S6 which undershoots the threshold value Uce,th.
In line with the invention, the top fault current path A is now detected when the threshold value Uce,th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 turned on and the fourth actuatable bidirectional power semiconductor switch S4 turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce, th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3,

S4, S5, S6 turned on and the first actuatable bidirectional power semiconductor switch SI turned on. In addition, in line with the invention, the top fault current path A is also detected when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4 turned off and the fourth actuatable bidirectional power semiconductor switch S4 turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches SI, S2, S3, S4 turned off and the first actuatable bidirectional power semiconductor switch S1 turned on.
By contrast, in line with the invention, the bottom fault current path 3 is detected when the threshold value Uce, th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 turned on and the first actuatable bidirectional power semiconductor switch S1 turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce,th is exceeded with one or more actuatable bidirectional power semiconductor switches S1, S2, S3, S4, 35, S6 “turned on and the fourth actuatable bidirectional power semiconductor switch S4 turned on. In addition, in line with the invention, the bottom fault current path B is also detected when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches SI, S2, S3, S4 turned off and the first actuatable bidirectional power semiconductor switch SI turned off when the threshold value Uce,th is exceeded, or when the threshold value Uce,th is undershot with one or more actuatable bidirectional power semiconductor switches SI, S2, S3, S4 turned off and the fourth actuatable bidirectional power semiconductor switch S4 turned on. Advantageously, this type of detection of the top and bottom fault current paths A, B makes it

possible to dispense with current sensors for detection completely, which means that the wiring and materials involvement can advantageously be reduced and the converter subsystem can thus be of simple and less expensive design. Furthermore, the susceptibility of the converter subsystem 1 and hence of the entire converter circuit to interference is advantageously reduced, which results in increased availability for the entire converter circuit.

List of reference symbols
1 Converter subsystem
2 DC voltage circuit
3 First principal connection
4 Second principal connection
5 Subconnection
S1 First power semiconductor switch
S2 Second power semiconductor switch
S3 Third power semiconductor switch
S4 Fourth power semiconductor switch
S5 Fifth power semiconductor switch
S6 Sixth power semiconductor switch A Top fault current path
B Bottom fault current path
C Load current path

PATENT CLAIMS
1. A method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem (1) provided for each phase (R,S,T) and comprises a DC voltage circuit (2) formed by two series-connected capacitors, where the DC voltage circuit (2) comprises a first principal connection (3) and a second principal connection (4) and a subconnection (5) formed by the two adjacent and interconnected capacitors, and which system has a first, a second, a third and a fourth actuatable bidirectional power semiconductor switch (SI, S2, S3, S4) and a fifth and a sixth power semiconductor switch (S5, S6), the first, second, third and fourth power semiconductor switches {SI, S2, S3, S4) being connected in series and the first power semiconductor switch (SI) being connected to the first principal connection (3) and the fourth power semiconductor switch (S4) being connected to the second principal connection (4), and where the fifth and sixth power semiconductor switches (S5, S6) are connected in series, the junction between the fifth power semiconductor switch (S5) and the sixth power semiconductor switch (S6) is connected to the subconnection (5), the fifth power semiconductor switch (S6) is connected to the junction between the first power semiconductor switch (SI) and the second power semiconductor switch (S2), and the sixth power semiconductor switch (S6) is connected to the junction between the third power semiconductor switch (S3) and the fourth power semiconductor switch (S4), in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem (1) is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches (SI, S2, S3, S6) or through the

first and fifth power semiconductor switches (SI, S5) ,
and the bottom fault current path running through the
second, third, fourth and fifth power semiconductor
switches (S2, S3, S4, S5) or through the fourth and
sixth power semiconductor switches (S4, S6), and
in which the actuatable bidirectional power
semiconductor switches (SI, S2, S3, S4) are switched on
the basis of a fault switching sequence,
characterized
in that the fault switching sequence in the event of
detection of the top or the bottom fault current path
(A, B) is followed by the detection’s accompanying switching status of each actuatable bidirectional power semiconductor switch (SI, S2, S3, S4) being recorded, in that in the event of detection of the top fault current path (A) the first power semiconductor switch
(SI) and then the third power semiconductor (S3) are turned off, and
in that in the event of detection of the bottom fault current path (B) the fourth power semiconductor switch
(S4) and then the second power semiconductor (S2) are turned off.
2. The method as claimed in claim 1, characterized in that the fifth and sixth power semiconductor switches
(S5, S6) are actuatable bidirectional power semiconductor switches, and in the event of detection of the top fault current path (A) the sixth power semiconductor switch (S6) is turned on before the first power semiconductor switch (SI) is turned off, and in the event of detection of the bottom fault current path
(B) the fifth power semiconductor switch (S5) is turned on before the fourth power semiconductor switch (4) is turned off.
3, The method as claimed in claim 1 or 2, characterized in that in the event of detection of the top fault current path (A) the third power

semiconductor switch (S3) is turned off with a selectable delay time (tv) relative to the first power semiconductor switch (Si), and in that in the event of detection of the bottom fault current path (B) the second power semiconductor switch (S2) is turned off with a selectable delay time (tv) relative to the fourth power semiconductor switch (S4).
4. The method as claimed in claim 3, characterized in that the delay time (tv) is selected in the order of magnitude of between lµs and 5µs.
5. The method as claimed in one of the preceding claims, characterized in that the actuatable bidirectional power semiconductor switches (Si, S2, S3, S4, S5, S6) in the converter subsystems (1) which are not affected by the fault are turned off.
6. The method as claimed in one of claims 1 to 5, characterized in that to detect the top or bottom fault current path (A, B) each actuatable bidirectional power semiconductor switch (SI, S2, S3, S4, S5, S6) is monitored for desaturation, and
in that a current through the subconnection (5) is monitored for its direction.
7. The method as claimed in claim 6, characterized in that the top fault current path (A) is detected in the case of desaturation of the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch (SI, S2, S3, 34, S5, S6) and a current through the subconnection (5) in the direction of the DC voltage circuit (5), and
in that the bottom fault current path (B) is detected in the case of desaturation of the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) and a current

through the subconnection (5) from the direction of the DC voltage circuit (5) .
8. The method as claimed in one of claims 1 to 5, characterized in that to detect the/ top or bottom fault current path (A, B) each actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) is monitored for desaturation, and
in that a current through the first principal connection (3) and a current through the second principal connection (4) are monitored.
9. The method as claimed in claim 8, characterized in that the top fault current path (A) is detected in the case of desaturation of the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch (SI, S2, S3, 35, S6) and a current through the first principal connection (3), and in that the bottom fault current path (3) is detected in the case of desaturation of the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) and a current through the second principal connection (4).
10. The method as claimed in one of claims 1 to 5, characterized in that the anode/cathode voltage (Uce) of each actuatable bidirectional power semiconductor switch (SI, S2, S3, S4, S5, S6) is monitored for a threshold value (Uce, th),
in that the top fault current path (A) is detected (al) when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and the fourth actuatable bidirectional power semiconductor switch (S4) turned off when the threshold value (Uce, th) is exceeded, or

(bl) when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and the first actuatable bidirectional power semiconductor switch (SI) turned on, or
(cl) when the threshold value (Uce,th) is undershot with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4) turned off and the fourth actuatable bidirectional power semiconductor switch (S4) turned off when the threshold value (Uce,th) is exceeded, or
(dl) when the threshold value (Uce,th) is undershot with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4) turned off and the first actuatable bidirectional power semiconductor switch (SI) turned on,
and in that the bottom fault current path (B) is
detected
(a2; when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and the first actuatable bidirectional power semiconductor switch (SI) turned off when the threshold value (Uce,th) is exceeded, or
(b2; when the threshold value (Uce,th) is exceeded with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) turned on and a fourth actuatable bidirectional power semiconductor switch (S4) turned on, or
(c2) when the threshold value (Uce,th) is undershot with one or more actuatable bidirectional power semiconductor switches (SI, S2, S3, S4) turned off and the first actuatable bidirectional power semiconductor switch (SI) turned off when the threshold value (Uce,th) is exceeded, or

semiconductor switch (S3) is turned off with a selectable delay time (tv) relative to the first power semiconductor switch (SI) , and in that in the event of detection of the bottom fault current path (B) the second power semiconductor switch (S2) is turned off with a selectable delay time (tv) relative to the fourth power semiconductor switch (S4).
4. The method as claimed in claim 3, characterized in that the delay time (tv) is selected in the order of magnitude of between lµs and 5JXS.
5. The method as claimed in one of the preceding claims, characterized in that the actuatable bidirectional power semiconductor switches (SI, S2, S3, S4, S5, S6) in the converter subsystems (1) which are not affected by the fault are turned off.
6. The method as claimed in one of claims 1 to 5, characterized in that to detect the top or bottom fault current path (A, B) each actuatable bidirectional power semiconductor switch (SI, S2, S3, . S4, S5, S6) is monitored for desaturation, and
in that a current through the subconnection (5) is monitored for its direction.
7. The method as claimed in claim 6, characterized in that the top fault current path (A) is detected in the case of desaturation of the first, second, third, fifth or sixth actuatable bidirectional power semiconductor switch (SI, S2, S3, S4, S5, S6) and a current through the subconnection (5) in the direction of the DC voltage circuit (5), and
in that the bottom fault current path (B) is detected in the case of desaturation of the second, third, fourth, fifth or sixth actuatable bidirectional power semiconductor switch (S2, S3, S4, S5, S6) and a current

Documents:

4632-CHENP-2006 AMENDED CLAIMS 14-12-2011.pdf

4632-CHENP-2006 CORRESPONDENCE OTHERS 24-01-2012.pdf

4632-CHENP-2006 FORM-3 14-12-2011.pdf

4632-CHENP-2006 FORM-3 24-01-2012.pdf

4632-CHENP-2006 POWER OF ATTORNEY 14-12-2011.pdf

4632-CHENP-2006 CORRESPONDENCE OTHERS 29-02-2012.pdf

4632-CHENP-2006 CORRESPONDENCE OTHERS 09-09-2011.pdf

4632-CHENP-2006 CORRESPONDENCE OTHERS 20-06-2012.pdf

4632-CHENP-2006 EXAMINATION REPORT REPLY RECEIVED 14-12-2011.pdf

4632-CHENP-2006 FORM-3 20-06-2012.pdf

4632-CHENP-2006 OTHER PATENT DOCUMENT 29-02-2012.pdf

4632-chenp-2006-abstract.pdf

4632-chenp-2006-abstractimage.jpg

4632-chenp-2006-claims.pdf

4632-chenp-2006-correspondnece-others.pdf

4632-chenp-2006-description(complete).pdf

4632-chenp-2006-drawings.pdf

4632-chenp-2006-form 1.pdf

4632-chenp-2006-form 3.pdf

4632-chenp-2006-form 5.pdf

4632-chenp-2006-pct.pdf

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Patent Number

252921

Indian Patent Application Number

4632/CHENP/2006

PG Journal Number

24/2012

Publication Date

15-Jun-2012

Grant Date

09-Jun-2012

Date of Filing

18-Dec-2006

Name of Patentee

ABB SCHWEIZ AG

Applicant Address

BROWN BOVERI STRASSE 6 CH-500 BADEN SWITZERLAND

Inventors:

#	Inventor's Name	Inventor's Address
1	KNAPP GEROLD	KREUZSTRASSE 16 CH-5420 EHRENDINGEN SWITZERLAND
2	HOCHSTUHIL GERHARD	KIRSCHBAUMWEG 6 D-79761 WALDSHUT-TIENGEN GERMANY
3	WIESER RUDOLF	IM ERGEL 10 PF 8 CH-5404 BADEN-DATTWILL SWITZERLAND
4	MEYSENC LUC	14 RUE CHANCELIERE F-38120 LE FONTANILL FRANCE

PCT International Classification Number

H02H 7/122

PCT International Application Number

PCT/CH05/00203

PCT International Filing date

2005-04-11

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	04405373.4	2004-06-18	EUROPEAN UNION