Title of Invention  METHOD AND APPARATUS FOR BLOCKWISE DECISIONFEEDBACK EQUALIZATION FOR WIRELESS COMMUNICATION 

Abstract  Techniques for performing decision feedback equalization are described. A feedforward filter response and a feedback filter response are derived based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample. The reliability parameter is indicative of the reliability of the feedback used for equalization and may be frequency dependent or frequency invariant. Different feedforward and feedback filter responses may be derived with different constraints on the feedback filter and different assumptions for the reliability parameter. Equalization is performed with the feedforward and feedback filter responses. If equalization is performed for multiple iterations then, for each iteration, the reliability parameter may be updated, the feedforward and feedback filter responses may be derived based on the updated reliability parameter, and equalization may be performed with the filter responses for the iteration. 
Full Text  FORM 2 THE PATENTS ACT, 1970 (39 of 1970) & THE PATENTS RULES, 2003 COMPLETE SPECIFICATION (See section 10, rule 13) "METHOD AND APPARATUS FOR BLOCKWISE DECISIONFEEDBACK EQUALIZATION FOR WIRELESS COMMUNICATION" QUALCOMM INCORPORATED, an American Company of 5775 Morehouse Drive, San Diego, California 921211714, United States of America The following specification particularly describes the invention and the manner in which it is to be performed. WO 2006/105309 PCT/US2006/011670 METHOD AND APPARATUS FOR BLOCKWISE DECISIONFEEDBACK EQUALIZATION FOR WIRELESS COMMUNICATION I. Claim of Priority under 35 U.S.C. §119 [0001] The present Application for Patent claims priority to Provisional Application Serial No. 60/666,334, entitled "METHOD AND APPARATUS FOR DECISIONFEEDBACK EQUALIZATION IN WIRELESS COMMUNICATIONS," and Provisional Application Serial No. 60/666,416, entitled "METHOD AND APPARATUS FOR ADAPTIVE EQUALIZATION IN WIRELESS COMMUNICATIONS," both filed March 29, 2005, assigned to the assignee hereof, and expressly incorporated herein by reference. BACKGROUND I. Field [0002] The present disclosure relates generally to communication, and more specifically to techniques for performing equalization in a communication system. II. Background [0003] In a communication system, a transmitter typically processes (e.g., encodes, interleaves, symbol maps, spreads, and scrambles) traffic data to generate a sequence of chips. The transmitter then processes the chip sequence to generate a radio frequency (RF) signal and transmits the RF signal via a communication channel. The communication channel distorts the RF signal with a channel response and further degrades the RF signal with noise and interference from other transmitters. [0004] A receiver receives the transmitted RF signal and processes the received RF signal to obtain samples. The receiver may perform equalization on the samples to obtain estimates of the chips sent by the transmitter. The receiver then processes (e.g., descrambles, despreads, demodulates, deinterleaves, and decodes) the chip estimates to obtain decoded data. The equalization typically has a large impact on the quality of the chip estimates as well as the overall performance. [0005] There is therefore a need in the art for techniques to perform equalization in a manner to achieve good performance. WO 2006/105309 PCT/US2006/011670 SUMMARY [0006] According to an embodiment of the invention, an apparatus is described which includes at least one processor and a memory. The processor(s) derive a feedforward filter response and a feedback filter response based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample. The rehability parameter is indicative of the reliability of the feedback used for equalization and may be frequency dependent or frequency invariant. The processor(s) perform equalization with the feedforward and feedback filter responses. [0007] According to another embodiment, a method is provided in which a feed forward filter response and a feedback filter response are derived based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample. Equalization is performed with the feedforward and feedback filter responses. [0008] According to yet another embodiment, an apparatus is described which includes means for deriving a feedforward filter response and a feedback filter response based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample. The apparatus further includes means for performing equalization with the feedforward and feedback filter responses. [0009] According to yet another embodiment, an apparatus is described which includes at least one processor and a memory. The processor(s) derive multiple feedforward filter responses for multiple signal copies based on channel estimates for the multiple signal copies and a reliability parameter. The multiple signal copies may be obtained from oversampling and/or multiple receive antennas. The processor(s) also derive a feedback filter response based on the channel estimates and the reliability parameter. The processor(s) perform equalization on input symbols for the multiple signal copies with the multiple feedforward filter responses and the feedback filter response. [0010] According to yet another embodiment, a method is provided in which multiple feedforward filter responses for multiple signal copies are derived based on channel estimates for the multiple signal copies and a reliability parameter. A feedback filter response is derived based on the channel estimates and the reliability parameter. WO 2006/105309 PCT/US2006/011670 Equalization is performed on input symbols for the multiple signal copies with the multiple feedforward filter responses and the feedback filter response. [0011] According to yet another embodiment, an apparatus is described which includes means for deriving multiple feedforward filter responses for multiple signal copies based on channel estimates for the multiple signal copies and a reliability parameter, means for deriving a feedback filter response based on the channel estimates and the reliability parameter, and means for performing equalization on input symbols for the multiple signal copies with the multiple feedforward filter responses and the feedback filter response. [0012] According to yet another embodiment, an apparatus is described which includes at least one processor and a memory. The processor(s) estimate a reliability parameter based on a first data block that is decoded correctly, derive a feedforward filter response and a feedback filter response based on a channel estimate and the reliability parameter, and perform equalization for a second data block with the feedforward and feedback filter responses. [0013] According to yet another embodiment, a method is provided in which a reliability parameter is estimated based on a first data block that is decoded correctly. A feedforward filter response and a feedback filter response are derived based on a channel estimate and the reliability parameter. Equalization is performed for a second data block with the feedforward and feedback filter responses. [0014] According to yet another embodiment, an apparatus is described which includes means for estimating a reliability parameter based on a first data block that is decoded correctly, means for deriving a feedforward filter response and a feedback filter response based on a channel estimate and the reliability parameter, and means for performing equalization for a second data block with the feedforward and feedback filter responses. [0015] Various aspects and embodiments of the invention are described in further detail below. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1A shows a timedomain model of a communication channel. [0017] FIG. IB shows a frequencydomain model of a communication channel. [0018] FIG. 2A shows a chipspaced DFE with a timedomain feedback filter. WO 2006/105309 PCT/US2006/011670 [0019] FIG. 2B shows a chipspaced DFE with a frequencydomain feedback filter. [0020] FIG. 3 shows a frequencydomain model for a chipspace DFE. [0021] FIG. 4 shows a process to derive feedforward and feedback filter responses. [0022] FIG. 5 shows a process to perform decision feedback equalization. [0023] FIG. 6A shows a fractionallyspaced DFE with a timedomain feedback filter. [0024] FIG. 6B shows a fractionallyspaced DFE with a frequencydomain feedback filter. [0025] FIG. 7 shows a frequencydomain model for a fractionallyspaced DFE. [0026] FIG. 8 shows a process to derive feedforward and feedback filter responses. [0027] FIG. 9 shows a process to perform equalization for multiple signal copies. [0028] FIG. 10 shows a process to perform decision feedback equalization based on a reliability parameter derived from correctly decoded data blocks. [0029] FIG. 11 shows a block diagram of a transmitter and a receiver. DETAILED DESCRIPTION [0030] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. [0031] For clarity, the following nomenclature is used in much of the description below. Timedomain scalars are denoted by lower case text with index n for sample period, e.g., h(n). Frequencydomain scalars are denoted by upper case text with index k for frequency bin, e.g., H(k). Timedomain vectors are denoted by bolded lower case cursive text, e.g., /t. Timedomain matrices are denoted by bolded upper case cursive text, e.g., #. Frequencydomain vectors are denoted by bolded lower case regular text, e.g., h. Frequencydomain matrices are denoted by bolded upper case regular text, e.g., H. The terms "chips" and "samples" generally refer to timedomain quantities, and the term "symbols" generally refers to frequencydomain quantities. 1. ChipSpaced DFE [0032] FIG. 1A shows a timedomain model 100 of a communication system with a transmitter 110 and a receiver 150. Model 100 assumes that the received signal is sampled at chip rate so that the sample rate is equal to the chip rate. Transmitter 110 processes traffic data and generates transmit chips s(n), which are sent via a WO 2006/105309 PCT/US2006/011670 communication channel 120. Channel 120 is modeled with a timedomain impulse response of h(n) in block 124 and additive noise of n(n) via a summer 126. The channel impulse response h(n) includes the effects of the pulse shaping filter at transmitter 110, the propagation channel, the frontend filter at receiver 150, and so on. Receiver 150 obtains input samples r(n) via channel 120 and performs equalization on the input samples to obtain chip estimates s(n), which are estimates of the transmit chips s(n). [0033] FIG. IB shows a frequencydomain model 102 of the communication system in FIG. 1A. Frequencydomain model 102 is equivalent to timedomain model 100. The transmit chips s(n) from transmitter 110 are sent via a communication channel 130. For channel 130, the timedomain transmit chips s(n) are transformed to the frequency domain with a Kpoint fast Fourier transform (FFT) or a Kpoint discrete Fourier transform (DFT) by a unit 132 to obtain frequencydomain transmit symbols S(k). Channel 130 is modeled with a channel frequency response of H(k) in block 134 and additive noise of N(k) via a summer 136. A unit 138 performs a Kpoint FFT/DFT on the timedomain noise n(n) and provides the frequencydomain noise N(k). A unit 140 performs a Kpoint inverse FFT (IFFT) or a Kpoint inverse DFT (IDFT) on the frequencydomain input symbols R(k) from summer 136 and provides the timedomain input samples r(ri) to receiver 150. [0034] The timedomain input samples r(n) and the frequencydomain input symbols R(k) may be expressed as: where denotes a convolution. [0035] Receiver 150 may process the input samples on a blockbyblock basis. A data block may also be called a packet, a frame, and so on. In an embodiment, each data block contains K input samples. The input samples and input symbols may be expressed in matrix form for one data block, as follows: [0036] The noise may be assumed to be additive white Gaussian noise (AWGN) with zero mean and a covariance matrix of Nt I, where Nt is the variance of the noise and I is the identity matrix. [0037] The element in row k and column n of WK may be given as: In equation (6), the "1" is due to indices k and n starting with 1 instead of 0. [0038] Receiver 150 may perform decision feedback equalization on each block of input samples. A decision feedback equalizer (DFE) typically includes a feedforward filter and a feedback filter. In an embodiment, the feedforward filter is implemented in the frequency domain, and the feedback filter may be implemented in either the time domain or the frequency domain. [0039] FIG. 2A shows a block diagram of a model 200 with a DFE having a time domain feedback filter. A transmitter 210 generates transmit chips s(n), which are sent via a communication channel 220. Channel 220 is modeled with a channel impulse response of h(n) in block 224 and additive noise of n(n) via a summer 226. A receiver 250a obtains input samples r(n) via channel 220. Within receiver 250a, an FFT/DFT unit 252 transforms the input samples to the frequency domain and provides input symbols R(k). A feedforward filter 260 filters the input symbols and provides filtered WO 2006/105309 PCT/US2006/011670 symbols X(k). An IFFT/DDFT unit 264 transforms the filtered symbols to the time domain and provides filtered samples x{n). A summer 266 subtracts feedback samples y(n) from the filtered samples x(n) and provides equalized samples z(n). A slicer 270 slices or quantizes the equalized samples z(n) and provides chip estimates s(n). A feedback filter 272 filters the chip estimates and provides the feedback samples y{n). [0040] FIG. 2B shows a block diagram of a model 202 with a DFE having a frequency domain feedback filter. Transmitter 210 and communication channel 220 are as described above for FIG. 2A. A receiver 250b obtains input samples r(n) via channel 220. Within receiver 250b, FFT/DFT unit 252 and feedforward filter 260 operate on the input samples as described above for FIG. 2A and provide filtered symbols X{k). Summer 266 subtracts feedback symbols Y(k) from the filtered symbols X(k) and provides equalized symbols Z(k). An IFFT/IDFT unit 268 transforms the equalized symbols to the time domain and provides equalized samples z(n). Slicer 270 slices the equalized samples z(n) and provides chip estimates s(n) An FFT/DFT unit 274 transforms the chip estimates s(n) to the frequency domain and provides symbol estimates S(k). A feedback filter 280 filters the symbol estimates and provides the feedback symbols Y(k). [0041] If a transmitted block has either a cyclic prefix or zero padding, then a linear convolution of the input samples and the impulse response of a timedomain feedforward filter is equivalent to a cyclic convolution. In this case, the timedomain feedforward filter may be represented in the frequency domain by a blockwise feedforward filter having a frequency response denoted by a K x K diagonal matrix F. Matrix F contains K filter coefficients along the diagonal for the K frequency bins and zeros elsewhere. The circular matrix S contains elements of the impulse response vector f>. [0043] The timedomain feedback filter may be represented in the frequency domain by a blockwise feedback filter having a frequency response denoted by a K x K diagonal matrix B. Matrix B contains K filter coefficients along the diagonal for the K frequency bins and zeros elsewhere. Since S is a circular matrix, 2J may be diagonalized as follows: [0044] FIG. 3 shows a frequencydomain model 300 with a chipspace DFE. Model 300 is equivalent to model 200 in FIG. 2A and model 202 in FIG. 2B. A transmitter 310 generates timedomain transmit chips s(n), which are sent via a communication channel 330. Channel 330 is modeled with an FFT/DFT unit 332 that transforms the transmit chips to transmit symbols S(k), a block 334 for the channel frequency response H(k), an FFT/DFT unit 338 that transforms timedomain noise n(n) to frequencydomain noise N(k), and a summer 336 that sums the outputs of blocks 334 and 338 and provides input symbols R(k) to a receiver 350. [0045] Within receiver 350, a feedforward filter 360 filters the input symbols R(k) and provides filtered symbols X(k). A summer 366 subtracts feedback symbols Y(k) from the filtered symbols X(£) and provides equalized symbols Z(k). An IFFT/IDFT unit 368 transforms the equalized symbols Z(k) to the time domain and provides equalized samples z(n). A slicer 370 slices the equalized samples z(n) and provides chip estimates s(n). An FFT/DFT unit 374 transforms the chip estimates to the frequency domain and provides symbol estimates S(k). A feedback filter 380 filters the symbol estimates and provides the feedback symbols Y(k). [0046] The filtered symbols from feedforward filter 360 may be expressed as: where x = [X(l) X(2) ... X(K)]T is a Kxl vector of filtered symbols. [0047] The feedback symbols from feedback filter 3 80 may be expressed as: [0049] The feedforward filter frequency response F and the feedback filter frequency response B may be derived in various manners. In an embodiment, the filter responses F and B are derived based on a minimum mean square error (MMSE) criterion that minimizes the mean square error (MSE) between the transmit chips s and the equalized samples z. The MSE may be expressed as: [0051] Equation (13) indicates that the transmit chips s as well as the chip estimates are uncorrelated. Equation (14) describes the correlation between the transmit chips s and the chip estimates £. This correlation is related to the reliability of the decision feedback for the DFE. [0052] Equation (12) may be expanded and combined with equations (11), (13) and (14). The MSE may then be expressed as: where F(k), B(k) and R(k,k) are the kth diagonal elements of K x K matrices F, B, and R, respectively. F(k) is the feedforward filter coefficient for frequency bin k, B(k) is the feedback filter coefficient for bin k, and R(k,k) is a reliability value for bin k. [0053] In an embodiment, the feedforward and feedback filter responses are derived without any constraint on the feedback filter. For this embodiment, the feedback filter impulse response may be given by Lxl vector B = [b0 b1 b2 ... &L_,]r. Vector 5 contains L timedomain filter taps b0 through bL1. In equations (16) and (17), R(k,k) is indicative of the reliability of the feedback from the slicer. [0056] In another embodiment, the feedforward and feedback filter responses are derived with a constraint of b0 = 0 for the feedback filter. The feedback filter is typically used to compensate only for intersymbol interference and hence there is no feedback related to the ontime sample. Coefficient b0 determines the feedback for the ontime sample and may be set to zero. For this embodiment, the feedback filter impulse response may be given by an Lxl vector 5 = [0 b1 b2 ...bL1]r. [0057] The feedback filter response may be given as: where p(m), for m = 1,..., (L 1), is the mth element of p. [0060] Vector £ may be derived based on matrix Q and vector p, as shown in equation (18). Vector 6 may then be transformed with an FFT/DFT to obtain the feedback filter response B(k), as shown in equation (19). To reduce computation, L may be selected to be much less than K but large enough to cover significant ISI components. [0061] From equation (15) and with the constraint of b0 = 0, the feedforward filter response may be given as: Equation (22) indicates that the feedforward filter response F(k) is dependent on the feedback filter response B(k) for the embodiment with b0 = 0. [0062] In yet another embodiment, the feedforward and feedback filter responses are derived with a constraint of b0 = 0 for the feedback filter and with R(k,k) = p and L = K. p is a reliability factor for the feedback and is not dependent on frequency. [0063] For this embodiment, the feedforward filter response may be given as: [0065] Equation (24) indicates that the feedback filter response B(k) is dependent on the feedforward filter response F(k) for the embodiment with b0=0, R(k,k) = p, and L = K. [0066] In yet another embodiment, the feedforward and feedback filter responses are derived with a constraint of b0 = 0 for the feedback filter and with an assumption of no feedback errors so that s(n) = s(n) and R{k,k) = 1. For this embodiment, the feedback filter response may be given as shown in equations (18) and (19), where [0068] FIG. 4 shows an embodiment of a process 400 for deriving the feedforward and feedback filter responses and equalizing the input symbols. Initially, a channel impulse response h(n) is estimated and transformed with an FFT/DFT to obtain a channel frequency response H(k) (block 412). A feedback correlation matrix R or a reliability factor p is initialized, e.g., to zero for the first iteration (block 414). For some embodiments described above, matrix R may be equal to pi, in which case R(k,k) = p, or may be equal to I, in which case R(k,k) = 1. [0069] A feedforward filter response F(k) is derived based on the channel frequency response H(k) and the feedback correlation R(k,k) or the reliability factor p (block 422). A feedback filter response B(k) is also derived based on the channel frequency response H(k) and the feedback correlation R(k,k) or the reliability factor p (block 424). The feedforward and feedback filter responses may be derived without any constraint on the feedback filter, e.g., as shown in equations (16) and (17). The feedforward and feedback filter responses may also be derived with a constraint of b0 = 0 for the feedback filter, e.g., as shown in equations (18) through (22), or equations (23) and (24) for the case with R{k,k)~p and L = K, or equations (25) through (27) for the case with R(k,k) = 1. The chip estimates are not available for the first iteration. Hence, the derivation of the feedback filter response may be omitted for the first iteration. [0070] For some embodiments described above, matrix Q and vector p may be derived based on the channel frequency response H(k) and the feedback correlation R(k,k) or the reliability factor p, e.g., as shown in equations (20) and (21) or equations WO 2006/105309 PCT/US2006/011670 (25) and (26). The feedback filter response may then be derived based on matrix Q and vector p, e.g., as shown in equations (18) and (19). [0071] In some embodiments, the feedforward filter response and the feedback filter response may be derived independently of one another. In some other embodiments, the feedforward filter response may be derived first, and the feedback filter response may be derived with the feedforward filter response, e.g., as shown in equation (24). In yet some other embodiments, the feedback filter response may be derived first, and the feedforward filter response may be derived with the feedforward filter response e.g., as shown in equation (22) or (27). [0072] Equalization is performed on the input symbols R(k) based on the feedforward and feedback filter responses, e.g., as shown in equations (9) through (11) (block 426). The equalized symbols are transformed and sliced to obtain chip estimates s(n) (block 428). [0073] Equalization may be performed for one or multiple iterations. Each iteration may also be called a stage, a round, and so on. A determination is made whether to perform another iteration (block 430). If the answer is 'Yes', then the feedback correlation matrix R or the reliability factor p is updated as described below (block 432). Matrix R or reliability factor p should become larger for each iteration. The process then returns to block 422 to update the feedforward and feedback filter responses and to perform equalization with the updated filter responses. Otherwise, if all iterations are completed and the answer is 'No' for block 430, then the process terminates. [0074] FIG. 5 shows an embodiment of a process 500 for performing decision feedback equalization. A channel estimate is obtained for a communication channel (block 512). The channel estimate may be a channel impulse response estimate, a channel frequency response estimate, and so on. A reliability parameter indicative of the reliability of the feedback used for equalization is initialized (block 514). The reliability parameter may be a feedback correlation matrix R, a reliability factor p, and/or some other quantity. The reliability parameter may be a function of frequency or may be frequency invariant. [0075] A feedforward filter response is derived based on the channel estimate and the reliability parameter (block 522). A feedback filter response is derived based on the channel estimate and the reliability parameter (block 524). The feedforward and WO 2006/105309 PCT/US2006/011670 feedback filter responses may be derived (1) without any constraint on the feedback filter, (2) with a constraint of no feedback for an ontime sample, or (3) based on some other constraint or condition. The feedforward and feedback filter responses may be derived based on MMSE or some other criterion. The feedforward and feedback filter responses may be derived independently of one another, the feedback filter response may be derived based on the feedforward filter response, or the feedforward filter response may be derived based on the feedback filter response. The feedforward filter response may be in the frequency domain and comprise frequencydomain coefficients. The feedback filter response may be in (1) the frequency domain and comprise frequencydomain coefficients or (2) the time domain and comprise timedomain taps. In general, different feedforward and feedback filter responses may be derived for different filter constraints, assumptions on feedback reliability, design criteria, and so on. [0076] Equalization is performed with the feedforward and feedback filter responses (block 526). The equalization may be performed on a blockbyblock basis for each received data block. Equalization may also be performed for multiple iterations. If another iteration is to be performed, as determined in block 530, then the reliability parameter may be updated, and the feedforward and feedback filter responses for the next iteration may be derived based on the channel estimate and the updated reliability parameter. 2. FractionallySpaced DFE [0077] FIG. 6A shows a timedomain model 600 for a communication system with two times (2x) oversampling at a receiver 650a. A transmitter 610 processes traffic data and generates transmit chips s(n') at the chip rate, where n' is an index for chip period. In an actual system, transmitter 610 sends the transmit chips via a communication channel 620 to receiver 650a. For model 600, an upsampler 612 inserts a zero after each transmit chip and provides output samples s(n) at the sample rate. Channel 620 is modeled with a channel impulse response of h(n) in block 624 and additive noise of n(n) via a summer 626. [0078] FIG. 6A also shows a fractionallyspaced DFE with a timedomain feedback filter. The term "fractionallyspaced" refers to sampling at a higher rate than the chip rate, and it is usually higher than the rate required by Nyquist sampling theorem. WO 2006/105309 PCT/US2006/011670 Receiver 650a digitalizes the received signal at twice the chip rate and obtains input samples r(n) at a sample rate that is twice the chip rate. A unit 652 transforms the input samples to the frequency domain with a 2Kpoint FFT/DFT and provides input symbols R(k), for k = 1,..., 2K. The 2x oversampling of the received signal results in two copies of the signal spectrum being available. The two redundant signal copies are referred to as a lower copy (L) and an upper copy (U). The first K input symbols R(k), for k = l,...,K, are for the lower copy, are denoted as RL(K), for & = 1,...,K, and are provided to a feedforward filter 660a. The last K input symbols R(k), for k = K +1,..., 2K, are for the upper copy, are denoted as Rv(k), for k = 1,..., K, and are provided to a feedforward filter 660b. [0079] Feedforward filter 660a filters the input symbols Rh{k) and provides filtered symbols XL(k) for the lower copy. Feedforward filter 660b filters the input symbols Ru(k) and provides filtered symbols Xu(k) for the upper copy. A summer 662 sums the filtered symbols XiSk) and Xu(k) on a binbybin basis. A gain element 663 scales the output of summer 662 with a gain of 1/2 and provides filtered symbols X(k), for fc = l,...,K. A unit 664 performs a Kpoint IFFT/IDFT on the filtered symbols and provides filtered samples x(n) at the chip rate. The summing of Xh(k) and Xu(k) by summer 662, scaling by 1/2 with unit 663, and Kpoint IFFT/IDFT by unit 664 is equivalent to performing a 2Kpoint IFFT/IDFT on Xh(k) and Xv(k) followed by decimation by a factor of two to obtain the filtered samples x(n) at the chip rate. A summer 666 subtracts feedback samples y(n) from the filtered samples x(n) and provides equalized samples z(n). A slicer 670 slices the equalized samples z(n) and provides chip estimates s(n). A feedback filter 672 filters the chip estimates and provides the feedback samples v(n). [0080] FIG. 6B shows a block diagram of a model 602 with a fractionallyspaced DFE having a frequencydomain feedback filter. Transmitter 610 and channel 620 are as described above for FIG. 6A. A receiver 650b obtains input samples r(n) at the sample rate. Within receiver 650b, FFT/DFT unit 652, feedforward filters 660a and 660b, summer 662, and gain element 663 operate on the input samples as described above for FIG. 6A and provide filtered symbols X(k). Summer 666 subtracts feedback symbols Y(k) from the filtered symbols X(k) and provides equalized symbols Z(k). An IFFT/IDFT unit 668 transforms the equalized symbols to the time domain and provides equalized samples z(n). Slicer 670 slices the equalized samples z(n) and provides chip estimates S(n). An FFT/DFT unit 674 transforms the chip estimates to the frequency domain and provides symbol estimates S(k). A feedback filter 680 filters the symbol estimates and provides the feedback symbols Y(k). [0081] FIG. 7 shows a frequencydomain model 700 with a fractionallyspaced DFE. Model 700 is equivalent to model 600 in FIG. 6A and model 602 in FIG. 6B. A transmitter 710 generates timedomain transmit chips s(n') at the chip rate, which are sent via a communication channel 730. For channel 730, the timedomain transmit chips are transformed to the frequency domain with a Kpoint FFT/DFT by a unit 732 to obtain frequencydomain transmit symbols S(k), for fc = l,...,K. The channel for the lower signal copy is modeled by a frequency response of Ht(k) in block 734a and additive noise of Ni£k) via a summer 736a. The channel for the upper signal copy is modeled by a frequency response of H\j(k) in block 734b and additive noise of Nu(k) via a summer 736b. A unit 738 transforms the timedomain noise n(n) and provides the frequencydomain noise Nifk) and N\j(k) for the lower and upper copies, respectively. [0082] A receiver 750 obtains input symbols Rh(k) and Rv(k) for the lower and upper copies, respectively. Feedforward filters 760a and 760b filter the input symbols RUk) and R\j(k) and provide filtered symbols XL(k) and X\j(k), respectively. The filtered symbols Xi,(k) and Xu(k) are summed by a summer 762 and scaled with a gain of 1/2 by a gain element 763 to obtain filtered symbols X(k). A summer 766 subtracts feedback symbols Y(k) from the filtered symbols X(k) and provides equalized symbols Z(k). The equalized symbols Z(k) are transformed to the time domain by an IFFT/IDFT unit 768 and sliced by a slicer 770 to obtain chip estimates s(n). The chip estimates are transformed to the frequency domain by an FFT/DFT unit 774 and filtered by a feedback filter 780 to obtain the feedback symbols. [0083] The input symbols may be expressed in matrix form for one data block, as follows: matrices in equation (31) are KxK matrices, and all other vectors are K x 1 vectors. [0087] The feedforward filter frequency responses FL and Fu and the feedback filter frequency response B may be derived based on an MMSE criterion that minimizes the MSE shown in equation (12) with the assumptions shown in equations (13) and (14). Equation (12) may be expanded and combined with equations (13), (14) and (31). The MSE may then be expressed as: where Fi.(k), Fu(k), Hi(k), HL(k) are the fcth diagonal elements of K x K matrices FL, Fu, HL and Hu, respectively. [0088] In an embodiment, the feedforward and feedback filter responses are derived without any constraint on the feedback filter. For this embodiment, the feedback filter impulse response may be given by Lxl vector 6=[b0 b1 b2 ... &L_,]T. [0089] From equation (32), the feedforward filter response may be given as: where Hc(k), for c  L, U, is the channel gain for frequency bin k in copy c, and Fc(k), for c = L, U, is the feedforward filter coefficient for bin k in copy c. [0090] The feedback filter response may be given as: [0092] The feedback filter response may be given as shown in equations (18) and (19), where the elements of matrix Q, for m, / = 1,..., (L 1), may be given as: [0095] In yet another embodiment, the feedforward and feedback filter responses are derived with a constraint of b0 =0 for the feedback filter and with R(k,k)=p and L = K. For this embodiment, the feedforward filter response may be given as: [0097] In yet another embodiment, the feedforward and feedback filter responses are derived with a constraint of b0 = 0 for the feedback filter and with an assumption of no feedback errors so that s(n) = s(ii) and R(k,k) 1. For this embodiment, the feedback filter response may be given as shown in equations (18) and (19), where [0098] The feedforward filter responses may be given as: [0099] FIG. 8 shows an embodiment of a process 800 for deriving fractionallyspaced feedforward and feedback filter responses and equalizing the input symbols. Initially, a channel impulse response h{n) is estimated and transformed with an FFT/DFT to obtain channel frequency responses HiXk) and Hu(k) for the lower and upper signal copies, respectively (block 812). A feedback correlation matrix R or a reliability factor p is initialized, e.g., to zero(s) for the first iteration (block 814). [00100] Feedforward filter responses F\£k) and Fu(k) for the lower and upper copies are derived based on the channel frequency responses Hh(k) and Hu(k) and the feedback correlation R(k,k) or the reliability factor p, e.g., as shown in equation (33), (37), (38) or (42) (block 822). A feedback filter response B(k) is also derived based on the channel frequency responses Ht(k) and H\j(k) and the feedback correlation R(k,k) or the reliability factor p, e.g., as shown in equation (34), (35) and (36), (39), or (40) and (41) (block 824). Equalization is performed on the input symbols Rifle) and R\j(k) for the lower and upper copies based on the feedforward and feedback filter responses, e.g., as shown in equations (29) through (31) (block 826). The equalized symbols are transformed and sliced to obtain chip estimates s(n) (block 828). [00101] Equalization may be performed for one or multiple iterations. A determination is made whether to perform another iteration (block 830). If the answer is 'Yes', then the feedback correlation matrix R or the reliability factor p is updated (block 832). The process then returns to block 822 to update the feedforward and feedback filter [00103] For clarity, the chipspaced DFE and fractionallyspaced DFE have been described for a single receive antenna at the receiver. The DFEs described herein may also be used for a receiver with multiple (R) antennas, which may be employed for receive diversity or a multipleinput multipleoutput (MIMO) transmission. For chip rate sampling with receive diversity, the receiver obtains R signal copies and R channel frequency responses for the R receive antennas. The receiver may derive R feedforward filter responses for the R signal copies, e.g., based on the description above for the fractionallyspaced DFE, albeit with the signal copies being from different receive antennas instead of different parts of the signal spectrum. For oversampling with receive diversity, the receiver obtains RC signal copies and RC channel frequency responses for the R receive antennas and C times oversampling. The receiver may derive RC feedforward filter responses for the RC signal copies, e.g., based on the description above for the fractionallyspaced DFE, albeit with the signal copies being from different receive antennas as well as different parts of the signal spectrum. [00104] FIG. 9 shows an embodiment of a process 900 for performing decision feedback equalization for multiple signal copies, which may be obtained via multiple receive antennas and/or oversampling. Channel estimates are obtained for the multiple signal copies (block 912). The channel estimates may be channel impulse response estimates, channel frequency response estimates, and so on. A reliability parameter, which may be a feedback correlation matrix R, a reliability factor p, and/or some other quantity, is initialized (block 914). [00105] Feedforward filter responses for the multiple signal copies are derived based on the channel estimates and the reliability parameter (block 922). A feedback filter WO 2006/105309 PCT/US2006/011670 response is derived based on the channel estimates and the reliability parameter (block 924). The feedforward and feedback filter responses may be derived (1) without any constraint on the feedback filter, (2) with a constraint of no feedback for an ontime sample, or (3) based on some other constraint or condition. The feedforward and feedback filter responses may be derived based on MMSE or some other criterion. The feedforward and feedback filter responses may be derived independently, the feedback filter response may be derived based on the feedforward filter responses, or the feed forward filter responses may be derived based on the feedback filter response. In general, different feedforward and feedback filter responses may be derived for different filter constraints, assumptions on feedback reliability, design criteria, and so on. [00106] Equalization is performed with the feedforward and feedback filter responses (block 926). The equalization may be performed on a blockbyblock basis for each received data block. Equalization may also be performed for multiple iterations. If another iteration is to be performed, as determined in block 930, then the reliability parameter may be updated in block 932, and the feedforward and feedback filter responses for the next iteration may be derived based on the channel estimates and the updated reliability parameter. 3. Decision Feedback Reliability [00107] The feedforward and feedback filter responses may be derived based on R(k,k) or p, which is related to the reliability of the chip estimates s(n). The chip estimates are tentative decisions that are fed back for equalization. The amount of feedback is related to how reliable the chip estimates are statistically. The amount of feedback may be large if the chip estimates are very reliable and may be small if the chip estimates are not too reliable. In the extreme case, there may be no feedback if the chip estimates are completely unreliable. [00108] The reliability of the chip estimates may be estimated in various manners. In an embodiment, the reliability is estimated based on correctly decoded blocks. An error detection code, such as a cyclic redundancy check (CRC) code, may be used to determine whether a given block is decoded correctly. The transmitter may generate a CRC for a data block and append the CRC as part of the data block. The receiver may use the appended CRC for error detection. After decoding the block, the receiver may generate a CRC based on the decoded block and may compare the generated CRC against the appended CRC. If the two CRCs match, then the block is deemed to have been decoded correctly, and all of the chips in that block become known to the receiver. [00109] The receiver may use a correctly decoded block to compute the reliability of the chip estimates at various stages or iterations of equalization. The receiver may process the decoded block in the same manner performed by the transmitter and regenerate the transmit chips s(n) sent by the transmitter for the data block. In an embodiment, the receiver may correlate the transmit chips s(n) with the chip estimates s((n) for a given stage i to obtain a reliability factor /?, for that stage, as follows: where s, is a K x 1 vector of symbol estimates for stage i. [00111] Different chip estimates are obtained and fed back for equalization in different stages. Hence, the receiver may estimate the feedback reliability for different stages based on the chip estimates for these stages. [00112] The reliability of the decision feedback may be filtered across multiple correctly decoded blocks to reduce variation. The filtering may be performed based on a finite impulse response (FIR) filter, an infinite impulse response (IIR) filter, or some other type of filter. The time constant or bandwidth for the filter may be selected based on the expected rate of change in the channel conditions. A large time constant or small bandwidth may be used for a slowly varying channel. Conversely, a small time constant or large bandwidth may be used for a fast changing channel. The time constant of the filter may be adaptive based on Doppler for the receiver. [00113] Adjacent data blocks may be assumed to have appropriately similar decision feedback reliability for the same stage of equalization. In this case, the reliability WO 2006/105309 PCT/US2006/011670 estimated for different stages based on correctly decoded blocks may be used for decisionfeedback equalization of future blocks. [00114] The reliability of the decision feedback may be dependent on the modulation scheme used by the transmitter. In an embodiment, feedback reliability is estimated and maintained for different modulation schemes. For this embodiment, the reliability estimated for correctly decoded blocks sent with a given modulation scheme is used for equalization of future blocks sent with the same modulation scheme. In another embodiment, the feedback reliability is estimated in a manner to account for different modulation schemes used for the correctly decoded blocks. [00115] The reliability of the decision feedback may also be estimated based on other transmissions that are known a priori or ascertained by the receiver. For example, if a data block includes a known portion (e.g., a unique word, a preamble, and/or some other known information), then the feedback reliability may be estimated based on this known portion. [00116] The receiver may use the estimated feedback reliability to derive the feed forward and feedback filter responses. The receiver may also use the feedback reliability to determine whether to perform decision feedback equalization or linear equalization (without decision feedback). For example, the receiver may perform linear equalization if the feedback is too unreliable. [00117] FIG. 10 shows an embodiment of a process 1000 for performing decision feedback equalization based on a reliability parameter derived from correctly decoded blocks. The reliability parameter is estimated based on a first data block that is decoded correctly, which may be determined based on a CRC or some other error detection code (block 1012). The reliability parameter may be estimated based on (1) correlation of the transmit chips with the chip estimates, e.g., as shown in equation (43), or (2) an outer product of the transmit symbols and the symbol estimates, e.g., as shown in equation (44). The reliability parameter may be filtered across multiple correctly decoded blocks. The time constant for the filtering may be selected based on channel conditions and/or other factors. [00118] A feedforward filter response and a feedback filter response are derived based on a channel estimate and the reliability parameter (block 1014). Equalization is performed for a second data block with the feedforward and feedback filter responses (block 1016). If equalization is performed in multiple iterations or stages, then the WO 2006/105309 PCT/US2006/011670 reliability parameter may be estimated for each stage based on the first data block and the chip or symbol estimates for that stage. The feedforward and feedback filter responses for each iteration may be derived based on the reliability parameter for that iteration. [00119] FIG. 11 shows a block diagram of an embodiment of a transmitter 1110 and a receiver 1150 in a communication system 1100. For a downlink/forward link transmission, transmitter 1110 is part of a base station, and receiver 1150 is part of a wireless device. For an uplink/reverse link transmission, transmitter 1110 is part of a wireless device, and receiver 1150 is part of a base station. A base station is typically a fixed station that communicates with the wireless devices and may also be called a Node B, an access point, and so on. A wireless device may be fixed or mobile and may also be called a user equipment (UE), a mobile station, a user terminal, a subscriber unit, and so on. A wireless device may be a cellular phone, a personal digital assistant (PDA), a wireless modem card, or some other device or apparatus. [00120] At transmitter 1110, a transmit (TX) data processor 1120 processes (e.g., encodes, interleaves, and symbol maps) traffic data and generates data symbols. As used herein, a data symbol is a modulation symbol for data, a pilot symbol is a modulation symbol for pilot, a modulation symbol is a complex value for a point in a signal constellation (e.g., for MPSK or MQAM), and pilot is data that is known a priori by both the transmitter and receiver. A modulator 1130 process the data symbols and pilot symbols in a manner specified by the system and provides transmit chips s(n) to a transmitter unit (TMTR) 1132. Transmitter unit 1132 processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the transmit chips and generates an RF signal, which is transmitted from an antenna 1134. [00121] At receiver 1150, an antenna 1152 receives the transmitted RF signal via various signal paths and provides a received signal to a receiver unit (RCVR) 1154. Receiver unit 1154 conditions (e.g., filters, amplifies, and frequency downconverts) the received signal, digitizes the conditioned signal at a sample rate that may be equal to or higher than the chip rate, and provides timedomain input samples. An FFT/DFT unit 1156 transforms the input samples to the frequency domain and provides frequencydomain input symbols. [00122] A channel and noise estimator 1158 estimates the channel response and the noise based on the frequencydomain input symbols and/or the timedomain input samples. A WO 2006/105309 PCT/US2006/011670 decision feedback equalizer (DFE) 1160 derives the feedforward filter response(s) and the feedback filter response based on the channel and noise estimates and a reliability parameter. The reliability parameter may be estimated and updated by DFE 1160, a controller 1190, or some other unit based on correctly decoded blocks and/or other known transmissions. [00123] DFE 1160 filters the input symbols based on the feedforward and feedback filter responses and provides chip estimates to a demodulator (Demod) 1170. DFE 1160 may implement any of the DFE designs described above. Demodulator 1170 processes the chip estimates in a manner complementary to the processing by modulator 1130 and provides data symbol estimates. A receive (RX) data processor 1180 processes (e.g., symbol demaps, deinterleaves, and decodes) the data symbol estimates and provides decoded data. RX data processor 1180 may also check each data block based on the CRC. In general, the processing by demodulator 1170 and RX data processor 1180 is complementary to the processing by modulator 1130 and TX data processor 1120, respectively, at transmitter 1110. [00124] Controllers/processors 1140 and 1190 direct operation of various processing units at transmitter 1110 and receiver 1150, respectively. Memories 1142 and 1192 store data and program codes for transmitter 1110 and receiver 1150, respectively. [00125] The equalization techniques described herein may be used for various communication systems such as Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, SingleCarrier FDMA (SCFDMA) systems, and so on. A CDMA system may implement one or more radio technologies such as WidebandCDMA (WCDMA), cdma2000, and so on. cdma2000 covers IS2000, IS856, and IS95 standards. A TDMA system may implement a radio technology such as Global System for Mobile Communications (GSM). These various radio technologies and standards are known in the art. An OFDMA system transmits modulation symbols in the frequency domain on orthogonal subcarriers using orthogonal frequency division multiplexing (OFDM). An SCFDMA system transmits modulation symbols in the time domain on orthogonal subcarriers. [00126] Modulator 1130 at transmitter 1110 and demodulator 1170 at receiver 1150 perform processing as specified by the system. For example, modulator 1130 may WO 2006/105309 PCT/US2006/011670 perform processing for CDMA, OFDM, SCFDMA, and so on, or a combination thereof. [00127] Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. [00128] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. [00129] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A generalpurpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. [00130] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software WO 2006/105309 PCT/US2006/011670 module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CDROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal. [00131] Headings are included herein for reference and to aid in locating certain sections. These headings are not intended to limit the scope of the concepts described therein under, and these concepts may have applicability in other sections throughout the entire specification. [00132] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. WO 2006/105309 PCT/US2006/011670 1. An apparatus comprising: at least one processor to derive a feedforward filter response and a feedback filter response based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample, and to perform equalization with the feedforward and feedback filter responses; and a memory coupled to the at least one processor. 2. The apparatus of claim 1, wherein the reliability parameter is a function of frequency. 3. The apparatus of claim 1, wherein the reliability parameter is frequency invariant. 4. The apparatus of claim 1, wherein the at least one processor estimates the reliability parameter based on a data block that is decoded correctly. 5. The apparatus of claim 1, wherein the at least one processor derives frequencydomain coefficients for the feedforward filter response and filters input symbols with the frequencydomain coefficients. 6. The apparatus of claim 1, wherein the at least one processor derives frequencydomain coefficients for the feedback filter response and filters symbol estimates with the frequencydomain coefficients. 7. The apparatus of claim 1, wherein the at least one processor derives timedomain taps for the feedback filter response and filters chip estimates with the timedomain taps. 8. The apparatus of claim 1, wherein the at least one processor performs equalization for multiple iterations, updates the reliability parameter for each iteration, WO 2006/105309 PCT/US2006/011670 and derives the feedforward and feedback filter responses for each iteration based on the channel estimate and the reliability parameter for the iteration. 9. The apparatus of claim 1, wherein the at least one processor derives the feedforward and feedback filter responses based on minimum mean square error (MMSE) criterion. 10. The apparatus of claim 1, wherein the at least one processor derives the feedforward and feedback filter responses and performs equalization for each of at least one data block. 11. A method comprising: deriving a feedforward filter response and a feedback filter response based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample; and performing equalization with the feedforward and feedback filter responses. 12. The method of claim 11, further comprising: estimating the reliability parameter based on a data block that is decoded correctly. 13. The method of claim 11, wherein equalization is performed for multiple iterations, and wherein the deriving the feedforward and feedback filter responses comprises updating the reliability parameter for each iteration, and deriving the feedforward and feedback filter responses for each iteration based on the channel estimate and the reliability parameter for the iteration. 14. An apparatus comprising: means for deriving a feedforward filter response and a feedback filter response based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample; and WO 2006/105309 PCT/US2006/011670 means for performing equalization with the feedforward and feedback filter responses. 15. The apparatus of claim 14, further comprising: means for estimating the reliability parameter based on a data block that is decoded correctly. 16. The apparatus of claim 14, wherein equalization is performed for multiple iterations, and wherein the means for deriving the feedforward and feedback filter responses comprises means for updating the reliability parameter for each iteration, and means for deriving the feedforward and feedback filter responses for each iteration based on the channel estimate and the reliability parameter for the iteration. 17. An apparatus comprising: at least one processor to derive multiple feedforward filter responses for multiple signal copies based on channel estimates for the multiple signal copies and a reliability parameter, to derive a feedback filter response based on the channel estimates and the reliability parameter, and to perform equalization on input symbols for the multiple signal copies with the multiple feedforward filter responses and the feedback filter response; and a memory coupled to the at least one processor. 18. The apparatus of claim 17, wherein the at least one processor derives the feedforward and feedback filter responses without constraint on the feedback filter response. 19. The apparatus of claim 17, wherein the at least one processor derives the feedforward and feedback filter responses with a constraint of no feedback for an ontime sample. WO 2006/105309 PCT/US2006/011670 20. The apparatus of claim 17, wherein the multiple signal copies are obtained via oversampling of a received signal. 21. The apparatus of claim 17, wherein the multiple signal copies are obtained via multiple receive antennas. 22. The apparatus of claim 17, wherein the multiple signal copies are obtained via multiple receive antennas and oversampling of a received signal from each receive antenna. 23. A method comprising: deriving multiple feedforward filter responses for multiple signal copies based on channel estimates for the multiple signal copies and a reliability parameter; deriving a feedback filter response based on the channel estimates and the reliability parameter; and performing equalization on input symbols for the multiple signal copies with the multiple feedforward filter responses and the feedback filter response. 24. The method of claim 23, wherein the deriving the multiple feedforward filter responses comprises deriving the multiple feedforward filter responses without constraint on the feedback filter response, and wherein the deriving the feedback filter response comprises deriving the feedback filter response without constraint on the feedback filter response. 25. The method of claim 23, wherein the deriving the multiple feedforward filter responses comprises deriving the multiple feedforward filter responses with a constraint of no feedback for an ontime sample, and wherein the deriving the feedback filter response comprises deriving the feedback filter response with the constraint of no feedback for the ontime sample. WO 2006/105309 PCT/US2006/011670 26. An apparatus comprising: means for deriving multiple feedforward filter responses for multiple signal copies based on channel estimates for the multiple signal copies and a reliability parameter; means for deriving a feedback filter response based on the channel estimates and the reliability parameter; and means for performing equalization on input symbols for the multiple signal copies with the multiple feedforward filter responses and the feedback filter response. 27. The apparatus of claim 26, wherein the means for deriving the multiple feedforward filter responses comprises means for deriving the multiple feedforward filter responses without constraint on the feedback filter response, and wherein the means for deriving the feedback filter response comprises means for deriving the feedback filter response without constraint on the feedback filter response. 28. The apparatus of claim 26, wherein the means for deriving the multiple feedforward filter responses comprises means for deriving the multiple feedforward filter responses with a constraint of no feedback for an ontime sample, and wherein the means for deriving the feedback filter response comprises means for deriving the feedback filter response with the constraint of no feedback for the ontime sample. 29. An apparatus comprising: at least one processor to estimate a reliability parameter based on a first data block mat is decoded correctly, to derive a feedforward filter response and a feedback filter response based on a channel estimate and the reliability parameter, and to perform equalization for a second data block with the feedforward and feedback filter responses; and a memory operatively coupled to the at least one processor. 30. The apparatus of claim 29, wherein the at least one processor determines that the first data block is decoded correctly based on a cyclic redundancy check (CRC). WO 2006/105309 PCT/US2006/011670 31. The apparatus of claim 29, wherein the at least one processor generates transmit chips based on the first data block and estimates the reliability parameter based on correlation between the transmit chips and chip estimates from the equalization. 32. The apparatus of claim 29, wherein the at least one processor generates transmit symbols based on the first data block and estimates the reliability parameter based on an outer product of the transmit symbols and symbol estimates from the equalization. 33. The apparatus of claim 29, wherein the at least one processor estimates the reliability parameter for each of multiple iterations of equalization based on the first data block, derives the feedforward and feedback filter responses for each iteration based on the reliability parameter for the iteration, and performs each iteration of equalization for the second data block with the feedforward and feedback filter responses for the iteration. 34. The apparatus of claim 29, wherein the at least one processor filters the reliability parameter across multiple correctly decoded data blocks. 35. The apparatus of claim 29, wherein the at least one processor selects a time constant based on channel conditions and filters the reliability parameter across multiple correctly decoded data blocks in accordance with the selected time constant. 36. The apparatus of claim 29, wherein the at least one processor determines whether or not to derive and use the feedback filter response based on the reliability parameter. 37. A method comprising: estimating a reliability parameter based on a first data block that is decoded correctly; deriving a feedforward filter response and a feedback filter response based on a channel estimate and the reliability parameter; and WO 2006/105309 PCT/US2006/011670 performing equalization for a second data block with the feedforward and feedback filter responses. 38. The method of claim 37, wherein the estimating the reliability parameter comprises generating transmit chips based on the first data block, and estimating the reliability parameter based on correlation between the transmit chips and chip estimates from the equalization. 39. The method of claim 37, wherein the estimating the reliability parameter comprises estimating the reliability parameter for each of multiple iterations of equalization based on the first data block, wherein the deriving the feedforward and feedback filter responses comprises deriving the feedforward and feedback filter responses for each iteration based on the reliability parameter for the iteration, and wherein the performing equalization comprises performing each iteration of equalization for the second data block with the feedforward and feedback filter responses for the iteration. 40. An apparatus comprising: means for estimating a reliability parameter based on a first data block that is decoded correctly; means for deriving a feedforward filter response and a feedback filter response based on a channel estimate and the reliability parameter; and means for performing equalization for a second data block with the feedforward and feedback filter responses. 41. The apparatus of claim 40, wherein the means for estimating the reliability parameter comprises means for generating transmit chips based on the first data block, and means for estimating the reliability parameter based on correlation between the transmit chips and chip estimates from the equalization. WO 2006/105309 PCT/US2006/011670 42. The apparatus of claim 40, wherein the means for estimating the reliability parameter comprises means for estimating the reliability parameter for each of multiple iterations of equalization based on the first data block, wherein the means for deriving the feedforward and feedback filter responses comprises means for deriving the feedforward and feedback filter responses for each iteration based on the reliability parameter for the iteration, and wherein the means for performing equalization comprises means for performing each iteration of equalization for the second data block with the feedforward and feedback filter responses for the iteration. ABSTRACT "METHOD AND APPARATUS FOR BLOCKWISE DECISIONFEEDBACK EQUALIZATION FOR WIRELESS COMMUNICATION" Techniques for performing decision feedback equalization are described. A feedforward filter response and a feedback filter response are derived based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an ontime sample. The reliability parameter is indicative of the reliability of the feedback used for equalization and may be frequency dependent or frequency invariant. Different feedforward and feedback filter responses may be derived with different constraints on the feedback filter and different assumptions for the reliability parameter. Equalization is performed with the feedforward and feedback filter responses. If equalization is performed for multiple iterations then, for each iteration, the reliability parameter may be updated, the feedforward and feedback filter responses may be derived based on the updated reliability parameter, and equalization may be performed with the filter responses for the iteration. 

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Patent Number  250631  

Indian Patent Application Number  1698/MUMNP/2007  
PG Journal Number  03/2012  
Publication Date  20Jan2012  
Grant Date  13Jan2012  
Date of Filing  16Oct2007  
Name of Patentee  QUALCOMM INCORPORATED  
Applicant Address  5775 MOREHOUSE DRIVE, SAN DIEGO, CALIFORNIA 921211714.  
Inventors:


PCT International Classification Number  H04L25/03  
PCT International Application Number  PCT/US2006/011670  
PCT International Filing date  20060329  
PCT Conventions:
