Title of Invention

AN ELECTRONIC BALLAST FOR DRIVING A GAS DISCHARGE LAMP AND A METHOD FOR CONTROLLING A GAS DISCHARGE LAMP WITH A BALLAST

Abstract A multiple-input ballast having a processor for controlling a gas discharge lamp in accordance with the present invention includes a processor, such as a microprocessor or digital signal processor (DSP), for receiving multiple inputs and controlling a discharge lamp in response to the inputs. The lamps include compact and conventional gas discharge lamps. The multiple processor input terminals are all active concurrently. The ballast processor uses these inputs, along with feedback signals indicating internal ballast conditions, to determine the desired intensity level of the lamp. Input signals provided to the processor include analog voltage level signals (such as the conventional 0-10 V analog signal for example), though it is understood that other voltage ranges or an electrical current signal could be used as well, digital communications signals including but not limited to those conforming to the Digital Addressable Lighting Interface (DALI) standard, phase control signals, infrared sensor signals: optical sensor signals, temperature sensor signals, sense signals derived from wired and/or wireless external devices, and sense signals providing information pertaining to electrical parameters such as current and voltage of the AC power supply (e.g., line) and the lamp. The ballast can also receive commands from other ballasts or a master control on a digital communication link, such as a 'DALI protocol link. This communication link is preferably bi-directional, allowing for the ballast to send commands, information regarding the ballast's settings, and diagnostic feedback to other devices on the communication link. The multiple-input ballast does not need in external, dedicated controller to control the lamp. A system of multiple-input ballasts can be configured as a distributed system, not needing a controller, and thus not creating a single point failure as in controller centric systems. However, a system of multiple-input ballasts can be configured to include a controller if desired. Each ballast processor contains memory. The processor memory is used, among other things, to store and retrieve set point algorithms, or procedures, for controlling the lamps in accordance with priorities and sequence of commands received via the ballast input signals.
Full Text AN ELECTRONIC BALLAST FOR DRIVING A GAS DISCHARGE
LAMP AND A METHOD FOR CONTROLLING A GAS DISCHARGE
LAMP WITH A BALLAST
Cross Reference To Related Applications
[0001] The present application claims priority to U.S. Provisi onal Application No. 60/544,479,
filed February 13, 2004, entitled "Multiple-Input Electronic Ballast With Processor" which is
hereby incorporated by reference in its entkety.
Field Of The Invention
[0002] The present invention generally relates to electronic ballasts, and more paiticularly to
ballasts having processors therein for controlling a gas discharge laanp in response to a plurality of
inputs.
Background
[0003] A conventional ballast control system, such as a system conforming to the Digital
Addressable Lighting Interface (DALI) standard as defined in Ihe Intemational Electrotechnical
Commission Document, EC 60929, includes a hai'dware controller for controlling the ballasts in
the system. Typically, the controller is coupled to the ballasts in the system via a single digital
serial interface, wherein data is transferred in accordance with DALI protocol. A disadvantage of
this single interface is that the bandwidth of the mterface limits the amount of message traffic that
can reasonably flow between the controller and the ballasts. This can also create delays in
response tunes to commands. Further, a typical DALI compatible ballast control system is limited
to 64 ballasts on a communication link. This also creates a disadvantage in that additional


cont-ollers are required to accommodate systems having more than 64 ballasts. Yet another
disadvantage of a ballast control system having a single controller is that the controller is a single
point failure.
[0004] That is, if the controller fails, the entire system is down. This is especially burdensome in
ligliting systems mstalled at remote locations.
[0005] Typically, these systems are configured m a polled configuration requiring a ballast to first
receive a transmission from the controller before the ballast can transmit. This can cause response
time delays, especially in large S5'stems. Also, these systems do not allow ballasts to be addressed
by devices other than the DALI compatible interface, thus limiting the flexibility and size of the
conti'ol system.
[0006] Fuilher, many conventional ballast control systems, such as non-DALI systems, do not
allow separate control of individual ballasts or groups of ballasts witlm the system. Systems that
do provide tliis ability typically require separate control Imes for each zone, a dedicated computer,
and comphcated software to caixy out the initial set-up or future rezoning of the system.
[0007] Many conventional ballasts include significant analog circuitry to receive and interpret
control inputs, to manage the operation of the power circuit and to detect and respond to fault
conditions. This analog circuitiy requires a lai-ge number of paits which increases cost and reduces
reliability. In addition, the individual fimctions performed by thif; circuitry ai-e often interdependent.
Tliis interdependence makes the circuits difficult to design, analyze, modify and test. This fiorther
increases the development cost for each ballast design.
[0008] These prior art systems lack a simple solution or device; for controlling the ballasts and
lamps. Thus, an electronic ballast circuit that contains fewer parts to reduce cost and increase
reliability, provides flexibility and growth, and does not require a conti-oller dedicated to controlling
an entire system is desired.
Summary Of The Invention
[0009] A multiple-input ballast havmg a processor for controlling a gas dischai-ge lamp m
accordance with the present invention includes a processor, such as a microprocessor or digital
signal processor (DSP), for receiving multiple inputs and controlling a discharge lamp in response
to the inputs. The lamps include compact and conventional gas discharge lamps. The multiple
processor input terminals are all active concurrently. The ballast processor uses these inputs,
along with feedback signals indicating internal ballast conditions, to determine die desired
intensity level of the lamp. Input signals provided to the processor include analog voltage level


signals (such as Hie conventional 0-10 V analog signal for exainple), though it is understood tliat
other voltage ranges or an electrical current signal could be us(;d as well, digital communications
signals including but not limited to those conforming to the Di;jital Addressable Lighting Merface
(DALI) standard, phase control signals, uifrared sensor signalS: optical sensor signals, temperatm-e
sensor signals, sense signals derived fi"om wired and/or wheless external devices, and sense signals
providing urfoimation pertauiing to electrical parameters such as cuirent and voltage of the AC
power supply (e.g., line) and the lamp. The ballast can also receive commands &om other ballasts
or a master control on a digital communication lidc, such as a 'DALI protocol linlc. This
communication link is preferably bi-directional, allowing for tiie ballast to send conmiands,
information regarding the ballast's settings, and diagnostic feedback to other devices on the
communication link. The multiple-input ballast does not need iin extemal, dedicated controller to
control the lamp. A system of multiple-input ballasts can be configured as a distributed system,
not needing a controller, and thus not creating a single point failwe as in controller centric
systems. However, a system of multiple-input ballasts can be configured to include a controller if
desired. Each ballast processor contains merriory. The processcT memory is used, among other
things, to store and retrieve set point algorithms, or procedures, for controlling the lamps in
accordance with priorities and sequence of commands received via the ballast input signals.
[0010] The multiple-input ballast comprises an inverter cii'cuit that drives one or more output
switches, such as field effect transistors (FETs), tliat control the amount of current delivered to the
load (lamp). The ballast processor conti'ols the intensity of the lighting load by directly conti-oUing
the switch(es) in the inverter circuit.
Brief Description of the Accompanying Drawings
[0011] The features and advantages of the present invention v/ill be best understood when
considering the following description in conjunction widi tire accompanying drawings, it being
understood, however, tliat the invention is not limited to the specific metliods and instrumentality
disclosed. In the drawings:
[0012] Figure 1 is a block diagram of a multiple-input ballast i^aving a processor in accordance
widi an exemplary embodiment of the present invention;
[0013] Figure 2 is a block diagram showing various exemplary signals provided to the processor
via processor terminals in accordance with an exemplary embodiment of the present invention;
[0014] Figure 3 A is a simplified schematic of the inverter circ ait coupled to the processor in
accordance witli an exemplaiy embodiment of the present invention;


[0015] Figure 3B is a simplified schematic of the inverter cii-cuit coupled to the processor in
accordance with an alternative exemplary embodiment of the present invention;
[0016] Figui-e 4 is a diagram depicting various processor cont'Olled ballast states in accordaiice
with an exemplary embodiment of tlae present invention;
[0017] Figure 5 is a diagram of a distributed ballast system hi accordance with an exemplary
embodiment of the present invention;
[0018] Figure 6 is a flow diagram of a process for controlling a gas discharge lamp with a
processor controlled ballast utilizing selected set point algoritlims in accordance with an exemplary
embodiment of the present invention;
[0019] Figure 7 is a diagram of a processor controlled ballast system configm-ed for a two room
apphcation in accordance witli an exemplary embodiment of the present invention; and
[0020] Figure 8 is a flow diagram of a set point procedure in accordance with an exemplary
embodiment of the present invention.
[0021] Figure 9 is a timing diagram for an analog to digital sampling method in accordance with
an exemplary embodiment of the present invention.
[0022] Figures 1OA and 1 OB are a flow diagi-am of a process for conti-olling input sampling in
accordance with an exemplary embodiment of the present invention.
Detailed Description Of Illustrative Embodiments
[0023] Figure 1 is a block diagram of a multiple-input ballast 12 having a processor 30 in
accordance with an exemplary embodiment of the present invention. As shown in Figure 1, ballast
12 comprises rectifying circuit 14, valley fill circuit 16, inverter circuit 18, output circuit 20, cat ear
circuit 24, optional sense circuits 22, 26,28, 29, and processor 30. The ballast 12 controls the gas
discharge lamp 32 via ballast output signal 52 in accordance witli ballast input signals 34 and the
various sense signals 38, 42,46,47. Although depicted as a single lamp 32 m Figure 1, the ballast
12 is also capable of controlling a pluraUty of lamps. To better understand the ballast 12, an
overview of the ballast 12 is provided below witli reference to Figure 1. A more detailed
description of portions of the ballast is provided in published patent application. Pub. No. US
2003/0107332, Patent Application No. 10/006,036, filed December 5,2001, entitled "Shigle
Sv^dtch Electronic Dimming Ballast", assigned to the assignee oi'the present application, and
published patent apphcation, Pub. No. US 2003/0001516, Patent Application No. 09/887,848, filed
June 22,2001, entitled "Electronic Ballast", also assigned to the assignee of the present


application, both applications hereby incorporated by reference in their entirety as if presented
herein.
[0024] As shown in the exemplary embodiment depicted in l^igure 1, the rectifying circuit 14 of
ballast 12 is capable of being coupled to an AC (alternating current) power supply. Typically the
AC power supply provides an AC line voltage at a specific line frequency of 50 Hz or 60 Hz,
altliough applications of the ballast 12 are not limited thereto. The rectifying circuit 14 converts the
AC line voltage to a foil wave rectified voltage signal 54. The fall wave rectified voltage signal
54 is provided to the valley fill chcuit 16. It is to be imderstood that whenever a signal is
provided, connected, coupled, coupled in circuit relation, or connectable to another device, the
signal may be indirectly coupled, e.g., via wireless means (such as via an IR or RF linlc), directly
connected by a wire, or connected tlirough a device such as, but: not limited to, a resistor, diode,
and/or a controUably conductive device, configured in series and/or pai-allel. It is also to be
understood that a message (e.g., information embodied in a signal) can be in the form of a digital
command, analog level, a pwm (pulse width modulated) waveform, or the lUce.
[0025] The valley fill circuit 16 selectively charges and discharges an energy storage device to
create a valley filled voltage signal 56. The valley filled voltage signal 56 is provided to the
inverter circuit 18. the uiverter circuit 18 converts the valley filled voltage signal 56 to a liigh-
fi-equency AC voltage signal 58. As described in more detail below, the inverter circuit 18
perfomis this conversion in accordance witli information provided via processor output signal 62.
The high-frequency AC voltage signal 58 is provided to the out]DUt circuit 20. The output circuit 20
filters the liigh-frequency AC voltage signal 58, provides voltage gain, and increases output
impedance, resulting in ballast output signal 52. The ballast output signal 52 is capable of
providing an electrical cun-ent (e.g., lamp current) to a load such as a gas discharge lamp 32. The
cat ear circuit 24 is coupled to the full wave rectified voltage signal 54.
[0026] The cat ear circuit 24 provides auxiliary power to the piocessor 30 via cat ear signal 50 and
faciUtates shaping of the electrical current waveform di'awn from the input power signal 60
provided to the valley fill circuit 16 to reduce ballast input current total harmonic distortion.
Various sense circuits, 22,26,28,29, sense electrical parameters via sense circuit input signals 36,
40,44,45, respectively, such as current and/or voltage, and pro-\'ide signals indicative of the sensed
parameters to the processor 30. Other sense circuits not shown in Figure 1 are appKcable, for
example a temperature sense circuit for sensing the temperature of the ballast 12 and providing a
temperature sense signal indicative of the ballast temperature to the processor 30. The application
of specific sense circuits is optional, hi one embodiment: (1) sense circuit 22 is a current sense


circuit for sensing current values fi:om either the input signal 60 or the fiill wave rectified voltage
signal 54 and providing sense signal 38 indicative of the sensed current values to the processor 30;
(2) sense circuit 26 is a voltage sense circuit for sensing voltage values of the valley filled voltage
signal 56 and providing sense signal 42 indicative of the sensed voltage values to the processor 30;
and (3) sense circuit 28 is a current sense cncuit for sensing current values firom the ballast output
signal 52 and providing sense signal 46 indicative of the sensed current values to the processor 30;
(4) sense circuit 29 is a voltage sense circuit for sensing voltage values from the ballast output
signal 52 and providing sense signal 47 indicative of the sensed voltage values to the processor
30. It is to be understood that the specific configuration of senstj circuits depicted in Figure 1 and
described above is exemplary, and ballast 12 is not limited thenrto.
[0027] the processor 30 can comprise any appropriate processor such as a inicroprocessor, a
microcontroller, a digital signal processor (DSP), a general purpose processor, an application
specific integrated circuit (ASIC), a dedicated processor, specialized hardware, general software
routines, specialized software, or a combination thereof. An exemplary embodiment of a
microprocessor comprises an electronic circuit, such as a large scale, integrated semiconductor
integrated circuit capable of executing computations and/or logical algoritlims in accordance with
binary mstructions contained in a stored program that resides in either internal or external memory
devices. The microprocessor can be in the fonn of a general purpose microprocessor, a
microcontroller, a DSP (digital signal processor), a microprocessor or state machine that is
embedded in an ASIC or field programmable device, or other form of fixed or configurable
electronic logic and rhemory. Further, a program can be stored in memory residing within the
microprocessor, in external memory coupled to the microprocessor, or a combination thereof the
program can comprise a sequence of binary words or the like tliat are recognizable by the
microprocessor as instructions to perform specific logical operations.
[0028] In one embodiment, the processor 30 performs functions in response to |he status of the
ballast 12. the status of the ballast 12 refers to the current condition of the ballast 12, including
but not hmited to, on/ofif condition, running hours, running hours since last lamp change, dim
level, operating temperature, certain fault conditions including the time for which the fault
condition has persisted, power level, and failure conditions. The processor 30 comprises memory,
includuig nonvolatile storage, for storage and access of data and software utilized to control the
lamp 32 and facilitate operation of the ballast 12. The processor 30 receives ballast input signals
34 and various sense signals (e.g., sense signals 38, 42,46,47) via respective processor terminals
on the processor 30 (terminals not shown in Figure 1). The proc

signals, and provides processor output signal 62 to the invertei: circuit 18 for controlling the gas
discharge lamp 32. In one embodiment, the ballast input signals 34 and the sense signals are
always active, thus allowing the ballast input signals 34 and the sense signals to be received by the
processor 30 in real time. The processor 30 can use a combination of present and past values of
sense signals and computational results to detemiine the present operating condition of the ballast.
However, the processor 30 is configurable to allow only selectc;d processor terminals to be active.
[0029] Figure 2 is a block diagram showing various exemplajy signals provided to the processor
30 via processor temiinals in accordance with an exemplary embodiment of the present invention.
For the salce of clarity, some of the circuitry shown in Figure 1 is represented collectively as other
ballast circuitry 51 in Figure 2. Further for the salce of clarity, only a subset of the processor
temimals is labeled (34a, 34b, 34c, 34d) corresponding to the ballast input signals 34 shown in
Figui'e 1. The ballast input signals 34 can comprise any appropriate signals for controlling the
lamp 32. As shown in Figure 2, exemplary ballast input signals comprise a phase controlled input
signal coupled to processor terminal 34a, a commmiications signal coupled to processor terminal
34b, an analog voltage signal coupled-to processor terminal 34c, and an electrical signal from an
infra-red (IR) receiver coupled to processor terminal 34d. It is emphasized that the ballast input
signals shown in Figure 2 are exemplary. Other types and number of ballast input signals are
apphcable, for example, the processor can be coupled to multiple IR signals, multiple analog
voltage or cuirent signals, power line carrier signals, and two-state signals including, but not limited
to, a contact closm^e signal from an occupancy sensor.
[0030] The phase control signal can be provided, for example, by a dimmer for dimming the
output light level of the lamp 32. In an exemplary embodiment, the phase control signal interface
comprises a 3-wire phase control interface. the communications signal can include, for example,
a digital coramimications signal, an analog communications signal, a serial communications signal,
a pai-allel coimmmications signal, or a combination thereof In an exemplary embodiment, the
communications signal is provided by a bidirectional digital serial data interface. The
bidirectional interface allows the processor 30 to send and recei^'e messages, such as ballast
conh-ol information, system control information, status requests, and status reports, for example.
The analog signal processor terminal (e.g., 34c) is capable of recieiving an analog signal. This
analog signal can be derived from any of the sensors described above. Further, the analog terminal
can be coupled to various sensors or multiple analog terminals may be coupled to combinations of
sensors. For example, the analog terminal 34c can be coupled to the photosensor 68 for receivmg
the optical sense signal 70, and another analog terminal (not labeled in Figure 2) can be coupled to


the temperature sensor 64 for receiving the temperature sense signal 66, or combinations thereof.
The IR terminal (e.g. 34d) can be coupled to an infrai-ed detect(3r for receiving serially encoded
instnictions from an IR hand-held remote transmitter. The ballast 12 may contain means for
conducting the beam of infrared light transmitted by the hand-held remote ti-ansmitter to an
infi-ared detector within the ballast, and the infrared detector is coupled to the IR tenxunal 34d of
the p'-icessor 30. Alternatively, this means can be attached to the ballast, or incorporated into a
sepaiaie module tliat is connected by wires to the ballast 12. the data pattern represented by the
modulation of the IR beam is exti^acted by the infi-ared detector and provided thereby to the
processor 30. The processor 30 decodes the pattern to extract the information encoded in the data
stream, such as lamp light level commands, operating parameters, and address infomiation, for
example.
[0031] The processor 30 is capable of receiving sense signal;;. Sense signals may comprise any
appropriate signal for controlling the lamp 32 and/or facilitating operation of the ballast 12.
Examples of sense signals include sense signals indicative of electrical parjimeters of the ballast 12
(e.g., 38, 42,46, 47), temperature sense signals, such as temperature sense signal 66 provided by
temperature sensor 64, an optical sense signal 70 provided by photosensor 68, or a combination
thereof In an exemplary embodunent, interface circuitry (not shown in Figure 2) is utilized to
process signals provided to the processor 30. The interface circuitry may perform fLmctions
includmg voltage level shifting, attenuation, filtering, electrical isolation, signal conditioning,
buffering, or a combuiation thereof.
[0032] Figui-e 3 A is a simphfied schematic of tiie inverter ckcuit 18 coupled to the processor 30
in accordance with an exemplary embodiment of the present invention. The processor 30 receives
control and sense input signals and provides a processor output signal 62 for controlling conti^ollable
conductive device 74 (e.g., switch) in the uiverter circuit 18 for ultimately contolling at least one
gas discharge lamp. Exemplary embodiments of controllable conductive device 74 include, but
are not limited to, power MOSFETs, triacs, bipolar junction transistors, insulated gate bipolar
transistors, and other electrical devices in wliich the conductance between two current carrying
electrodes can be controlled by means of a signal on a third electrode. Electrical power is
provided to the inverter circuit 18 tlirough the rectifying circuit 14 and valley fill circuit 16. The
inverter circuit 18 converts the voltage provided by the valley fi U circuit 16 into a Mgli frequency
AC voltage. The inverter circuit 18 includes a transformer 76, switch 74, and diode 78. The
transformer 76 comprises at least two windings. For the salce of clarity, the transformer 18 is
depicted in Figure 3 A as having three windings 80, 82, 84, The depiction of windmg 86 in Figure


-) rv is an-uoji;- u jiiicigii\^tiiij.jig u^uu^^ltt^lv^l^ oiid not E physical Winding (described below). The
switch 74 enables the conversion of the valley filled voltage signal 56 to a high frequency AC
voltage signal 58. The high frequency AC voltage signal 58 is provided to the output circuit 20 to
drive a lamp current tlirough at least one gas discharge lamp.
[0033] In operation, the processor 30 provides control infomiation via processor output signal 62
to control the conductive states of the switch 74. With the switch 74 closed (in a conductive state),
the valley filled voltage signal 56 is provided to the winding 82 of the transformer 76. For the
salce of clarity, the magnetizing inductance of transfomier 76 is shown as a separate winding 86,
although it is not physically a separate winding. The voltage ai)phed to windmg 82 allows current
to flow toough winding 82 resultmg m charging of the magnetizing inductance 86. With tiie
switch 74 closed, the voltage apphed to winding 82 is induced in the winding 84 in accordance
witli the turns ratio of the windings 82 and 84. Tliis results in a voltage having a first polarity
being provided to the output circuit 20. Also, with the switch 74 being closed, a voltage is induced
in the winding 80. However, the diode 78 is reverse biased during this state due to the winding
convention of transformer 76 as mdicated by the dot convention in Figure 3A. Switch 74 remains
in a conductive state (closed) until the processor 30 via processor output signal 62 commands a
change of state of the switch 74.
[0034] In a second state, the switch 74 is commanded to be open (non-conductive) by the
processor 30 via processor output signal 62. When this occurs, c;urrent-flowtlicoughtIie winding
82 is disabled. However, cuiTent-flow toough the magnetizing inductance 86 cannot instantly,
stop flowhig, lather this current-flow is modified in accordance witli the rate of change of the
current flow through the winding 82 (i.e., V=L dl/dt). This forces the magnetizing inductance 86
to become a voltage source driving ti-ansformer 76 in a polarity opposite to that which existed
when switch 74 was closed (conductive). During tliis non-conductive state wliile switch 74 is
open, the polarity reversal of the voltage on the wuiding 82 by the magnetizing iriductance 86
drives a lilce reversal on the windings 80 and 84. With this polaiity reversal, the windmg 84
provides the output circuit 20 with the higli-frequency AC voltage signal 58 having a voltage of
opposite polaiity as compared to the conductive state (switch 74 closed). the polarity reversal of
the second state (switch 74 open) now drives the winding 80 widi a voltage of polarity capable of
forward biasing the diode 78. If the value of the voltage on the v/inding 80 is greater than the value
of the voltage of the valley filled voltage signal 56, then diode 78 is forward biased. With diode 78
forward biased, the voltage on winding 80 is limited to the value of the voltage of the valley filled
signal 56. The winding 80 therefore acts as a clamp winding for the transformer 76. The limiting


of voltage on winding 80 has a corresponding limiting effect on all the windings of transfonTier 76.
The limiting of voltage on the winding 82 of transformer 76 ha;; the advantageous effect of
losslessly limiting the voltage stress on switch 74 during this second state. The limiting of voltage
on the winding 84 has the advantageous effect of applying a well defined voltage to the output
circuit 20 during this second state. The inverter circuit 18 returns to the conductive state after
completing the non-conductive state, and the voltage applied to the output circuit 20 is consti'ained
and defined in both states.
[0035] An alternative embodiment of the inverter and its connection to the output circuit is
shown in Figure 3B, where the output of the inverter at common point between the switch 74 and
the winding 82 is connected directly to a teiininal of the inductor 85 wliich comprises an integral
part of the output circuit. The charging of the magnetizing inductance 86 when the switch 74 is
commanded, to be closed is fire same as described above. Also the clamping action of winding 80
and diode 78 proceeds in the same manner as described above.
[0036] In one embodiment of the invention, the processor 30 directly controls the inverter 18 by
providing a digital signal that controls the instantaneous on/off estate of the inverter switch(es). The
duty cycle and frequency of tliis signal are substantially the same as the resulting duty cycle and
fi:equency of the inverter. It is to be understood, however, that this does not imply tliat the
controlling device dii-ectly drives the switch(es) in the uiverter. It is common to have a buffer or
driver between the controlling device and the switches. A purpose of the driver is to provide
amplification and/or level sWfting. In an exemplary embodiment, the driver does not significantly
alter duty cycle or fi-equency.
[0037] Wlien the inverter switch 74 is closed and the magneti/dng current begins to linearly
increase, it is desired to open the switch 74 and interrupt the flo'w of current theretlirough when the
current reaches a specified tlireshold level. However, because there are components of current
thi-ough the inverter switch 74 other than the one to be measured, it is not always possible to
measure the magnetizing cuirent by directly measuring the current tlirough the switch 74. In an
embodiment of the present invention, the processor 30 modulates the pulse widtli of the processor
control signal 62 to control the opening and closing of the inverter switch 74 utilizing a
computational model of tiie magnetizing inductance to determine! when the desired threshold level is
obtained. The value of magnetizing current is computed and the estimated time at which the
computed magnetizing current will reach the tlireshold value is })redicted. The processor 30
receives an indication of the instantaneous voltage value of the full wave rectified voltage signal 54
(or alternatively the input power signal 60) via sense signal 38. The processor 30 utilizes this


mstantaneous voltage value (or a value proportional to the actual instantaneous voltage value) in
conjunction witli the computational model described above to compute the time at which the cuirent
tlirough the switch 74 will reach the desired tlireshold value.
[0038] hi an exemplary embodiment of the invention, this computation is implemented as folloM's.
Each time the processor computes a con'ection term, y(n), in the lamp current control loop, it will
compute another term in accordance witli the equation


where PW(n) is proportional to the pulse width or duty ratio of Ihe inverter switch, K'lsa. scaluig
constant, WFis tire sampled value of the valley-fill bus voltage, ;md n is^an mteger index indicating
one of many sequential values of y and the associated value of ?W.
The switch 74 is controlled by the processor 30 at a frequency derived from the processor's 30
clock oscillator frequency and by a duty ratio as set by the ballast control loop.
[0039] The processor 30 performs several ftmctions in additioji to controllmg the inverter switch
74 to control the output hglit level of at least one gas discharge lamp. Some of these ftmctions
include: sampling input signals, filtering input signals, supervising ballast operations and
facilitating state fransitions of the ballast, detecting ballast fault conditions, responding to fault
conditions, receivuig and decoding data provided via the bidirectional communications interface,
and encoding and transmitting data via the bidirectional communications interface. The processor
30 also determuies lamp current levels m accordance with respective commanded levels on each of
the ballast input signals provided to the control input terminals, the relative priority of die ballast
input signals , and sequence of activation of the ballast input signals.
[0040] Input signals, such as the ballast input signals 34, are sampled and filtered as needed to
achieve a desired transient response of the ballast control circuitr>' via a digital filter(s) implemented
on the processor 30. Each digital filter approximates the performance of analog filters that have
been demonstrated to provide stable operation of gas discharge lamps over required operating
conditions. Utilization of digital filters provides the capability to tailor the performance of the
ballast control loop for different operating conditions and loads. Ivey filter parameters are
controlled by numerical coefficients that are stored in memory in the processor 30. These filter
coefficients are alterable, allowing modification of filter cliai'acteristics. For example, in one
embodiment the analog phase control ballast input signal is sampled to provide a digital signal.
This digital signal representation of the analog phase control signal is digitally filtered usuig a
second order digital filter having performance characteristics similar to analog filters utilized to


perform comparable functions.
[0041] In an embodiment of the present invention, the processor 30 receives data from the IR
signal in the fonn of a digital bit stream. The bit streams are conditioned by interface circuits
and/or the processor 30 to liave voltage amplitudes and levels that are compatible with the
processor's 30 input requirements. The processor 30 processes data encoded in the IR ballast
input signal. The encoded data uicludes commands such as: tuni the lamp on, turn die lamp off,
lower the output light level of the lamp, and select a preset output light level. Examples of systems
emploj'mg ballasts receiving IR signals ai-e disclosed in U.S. Patent Nos. 5,637,964, 5,987,205,
6,037,721, 6,310,440, and 6,667,578, the entireties ofwliich are hereby incorporated by reference,
and all of which are assigned to the assignee of the present application.
[0042] The processor 30 receives and ti'ansmits data via the communications interface in the
form of digital bit sti'eams, which in an exemplary embodiment conform to the Digital Addressable
Lightmg Interface (DALI) standard. The DALI standard is an industry standard digital interface
system using a digital 8 bit code to communicate dimming and operational instructions. It is to be
understood that non-standard extensions of the DALI protocol and/or other serial digital formats
can be used as well.
[0043] Figure 4 is a diagram depicting various processor controlled ballast states in accordance
with an exemplary embodiment of the present invention. Ballast: supervisory functions are
performed by the processor 30 by running a portion of processor resident software referred to as the
"ballast state machine". The ballast state machine program controls the start-up sequence of
heating the gas discharge lamp filaments (pre-heat state), increasing the voltage applied to the
lamps over a programmed interval (ramp state) to strilce an arc (strike state). The processor 30
running the ballast state machine program determines if the lamp has started via sense signal 46
from the current sense circuit 28. After properly strildng an arc, Ihe ballast is in the nonnal run
state. During the normal run state, die ballast state macliine progiam of processor 30 determines if
the lamps and control circuits are operating properly or if a fault c;ondition exists via sense signals
from the various implemented sensors (e.g., sense signals 38,42,46, 47). If it is determined that a
fault condition exists, the ballast state machine program deteraiines an appropriate action
dependent upon the type of fault. Example fault conditions monitored by the processor 30 include:
lamp voltage too high, lamp voltage too low, DC component of die lamp current too large, lamp
return current too low for the applied voltage, supply voltage too liigh, supply voltage too low, and
internal temperature of the ballast too high.
[0044] Figure 5 is a diagram of a distributed ballast system 500 in accordance with an exemplary


embodiment of the present invention. The system 500 include,'? at least two ballasts 12 having
respective processors 30 therein. For the salce of clarity, only ballast #1 is labeled with
identification numbers. Each ballast 12 and each processor 30 iire as described above. the plurality
of processors 30 are coupled via the communications interface also as described above. In one
embodiment of the present invention, the communications interface is a serial digital
communications link capable of transferring data in accordance; with the DALI standard.
[0045] the serial digital communications interface (linlc) is bi-directional, and an incoming
signal can comprise a command for a ballast to transmit data via the serial digital communications
interface about the current state or liistory of the ballast's operation. the ballast can also use the
serial digital communications interface to transmit information or commands to other ballasts tliat
are connected to that ballast. By utilizing the ballast's ability to initiate commands to other
ballasts, multiple ballasts can be coupled in a distributed configuration. For example, ballast #1 can
receive a command from an IR transmitter 33 via ballast #rs IR. interface to turn off all lamps of
the system 500. This command is transmitted to other ballasts in the system 500 via the
communications interface, hi another embodiment the ballasts of the system 500 can be coupled
in a master-slave configuration, wherein the master ballast receives one or more signals from a
central conti'oUer or from a local control device, and sends a command or commands to other
Ughting loads to conti'ol the operation of the other lighting loads, or synchronize the operation of
the other lighting loads witli itself The master ballast may also send commands and/or
information pertaining to its configuration to other control devicies, such as central controllers or
local controllers. For example, a master ballast may send a message containing its configuration to
other conti^ollers and/or ballasts indicating that it reduced its liglit output power by 50%, The
I
recipients of this message (e.g., slave devices, local controllers, central controllers) could
mdependentiy decide to also reduce their respective light output power by 50%. The phrase
lightuig loads includes ballasts, other conti-ollable Ught sources, ;ffld conti-ollable window
treatments such as motorized window shades. Ballasts and other controllable light sowces conti'ol
the amount of artificial light in a space while controllable window treatments control the amount
of natui-al fight in a space. The central confroUer may be a dedicated ligliting control or may also
comprise a building management system, AA^ controller, HVAC system, pealc demand confroUer
and energy controller.
[0046] ha an exemplary embodiment of the system 500, each ballast is assigned a unique address,
wliich enables other ballasts and/or a confroUer to issue commands to specific ballasts. The
infrared capable terminals on each processor of each ballast can be utilized to receive a numerical


address which is dii-ectly-loaded into the ballast, or can serve a:? a means to "notify" a ballast that
it should acquire and retain an address tliat is being received on a digital port. Generally, a port
comprises interface hardware that allows an external device to "connect" to the processor. A port
can comprise, but is not hmited to, digital line drivers, opto-electronic couplers, DR.
receivers/transmitters, RF receivers/transmitters. As Icnown in ihe ait, an IR receiver is a device
capable of receiving infrared radiation (typically in the form of a modulated beam of light),
detecting the impinging infrared radiation, extractrng a signal from the impinging ihfi-ai-ed radiation,
and ti-ansmitting tliat signal to another device. Also, as loiown in the art, an RF receiver can include
an electi-onic device such tliat when it is exposed to a modulated radio frequency signal of at least a
certaui energy level, it can respond to that received signal by extracting the modulating infomiation
or signal and transmit it via an electrical connection to another device or circuit.
[0047] As described above, each of the multiple controMnputs of each processor 30 is capable of
independently controlling operating parameters for the ballast 12 in which the processor 30 is
contained, and for other ballasts m the system 500. In one embodiment, the processor 30
implements a software routine, referred to as a set point algoritbn, to utilize the information
received via each of the input termiaals, their respective priorities, and the sequence in which the
commands are received. Various set point algorithms are envisioned.
[0048] Figure 6 is a flow diagram of a process for controlling a gas discharge lamp with a
processor controlled ballast utilizing selected set point algorithms in accordance with an
exemplary embodiment of the present invention. Ballast input signals are received by the
processor of the ballast at step 612. The received signals are processed in a Icnown maimer (e.g.,
sampled, quantized, digitized) at step 614. If a set point procedure (algorithm) has not been
previously selected, one is selected at step 616. If a set point procedure has been selected, then
step 616 directs the process to the selected set point procedure. The selected set point procedm-e is
adhered to at step 618 and the ballast and lamp are controlled in accordance with the selected set
point procedure at step 620. Example set point algorithms include;: (1) Multiply the commanded
levels received via each ballast input signal together to obtain the target level (desired lamp light
level); (2) Choose the lowest of the commanded levels received via the ballast input signals as the
target level; (3) Choose the most recently changed ballast input sij^nal as having liighest priority to
set the target level; and (4) Assign a specific processor terminal the highest priority, such as signals
received via the communications interface, and process the remaining inputs in accordance with
one of the above described set point algoritlims. The processor 30 can be progranmied vnih other
combinations of priority and sequence. In an embodunent of the present invention, multiple set


point algoritlims ai'e stored in processor 30
memory. One of the multiple set point algorithms is selected at the time of manufacture, sale,
mstallation, and/or during operation.
[0049] Figure 7 is a diagram of a processor controlled ballast system 700 configured for a two
room application iii accordance with an exemplary embodiment of the present iavention. The
system 700 depicts two rooms for clarity; however the system 700 is applicable to any niunber of
rooms. the system 700 comprises eight ballasts, each ballast comprising a processor. The ballasts
and the rooms are coupled to each other via communications interface 712. Optional controller 714
also is coupled to the ballasts viathe communications interface 712. As described above, each
ballast can respond to local commands (command for the specific ballast), global commands
(conunands for all baUasts), group commands (conmiands for all ballasts in a group), or a
combination thereof. Each room has a wall dimmer 718 and photosensor 722. Each ballast has an
infrared detector 720. Individual ballasts are controllable by the IR remote transmitter 716 via the
IR detector 720.
[0050] The ballasts and thus the lamps can be controlled by the optional contioUer, by the
mdividual ballast input signals, or a corabmation thereof In an tixemplaiy embodiment, each room
is individually controlled by its respective wall dimmer 718, and when the rooms are coupled
together, controlled by the optional contoller. hi another embodiment, the optional controller is
representative of a building management system coupled to the processor controlled ballast system
via a DALLcompatible commuuications interface 712 for controllhig all rooms in a building. For
example, the building management system can issue commands related to load shedding and/or
after-hours scenes.
[0051] An installation of several ballasts and other Ugliting loads can be made on a common
digital linlc without a dedicated central controller on that linlc. Any ballast receiving a sensor or
control mput can temporarily become a "master" of the digital bus and issue command(s) which
control (e.g., synchronize) the states of all of the ballasts and other hghting loads on the link. To
insui'e reHable conmiunications, well laiown data colhsion detection and re-try techniques can be
used.
[0052] Figui'e 8 is a flow diagram of a set point procedure in accordance with an exemplary
embodiment of the present invention. As described above, lamps are controlled in accordance with
selected procedures (referred to as set point algorithms) tliat incorporate the priorities and sequence
of the information on the ballast input signals. At step 812, the processor determines if the


command indicated by the communications input signal has clianged. If the indicated change is
from lamp on to lamp off, then at st^p S14, the ballasts go into the sleep state and the lamp is off
until a change in command is indicated by the IR input signal or the phase control input signal at
step 816. However, if commands via the IR input signal or the phase control input signal indicate
the lamp is to be tmned off (step 818), this change is ignored at step 820, because at this point, the
lamp is already off. Returning to step 812, if the indicated command change is from lamp off to
lamp on, then at step 822, the lamp level is set to the level indicated by tire analog input signal times
the level indicated by the most recent command change mdicatcd by the IR input signal or the phase
control input signal.
[0053] In an exemplary scenario, the system 700 is placed in tm after hours mode during portions
of a day (e.g., between 6:00 P.M. and 6:00 A.M.). When in the after hours mode, the processors of
the ballasts can receive conmiands via the communications interface to tum the lamps off
Subsequently the lamps can be turned on and adjusted with the IR remote transmitter via the IR
input signal or with the wall dimmer via the phase control input signal even if the command
provided via the communications signal indicate tliat the lamps are to be off The lamps remain at
the level set b}' the most recently changed of the phase control or IR input signals until one or the
other changes, or until the a command issued via the communic;ations signal is other than turn the
lamps off.
[0054] In an exemplary operating mode (other than the after hours mode), the most recently
received command level, via the communications interface, sets the upper limit of the lamp arc
current. Changes in the communications interface commanded level scale the light level
accordingly. If the IR input signal has been used to set lamps at different levels, tliose lamps
maintain their relative differences as the levels are scaled by the; communications interface
commands. An individual ballast/lamp(s) combination, i.e., fixture, can be dimmed up or down
witli the IR input. A subsequent change in the phase control in]™t signal overrides the IR input
signal commanded level, and aU fixtures in tliat room go to the level commanded by the phase
control input signal scaled by Hie communications signal indicated upper limit and the analog input.
A photo sensor (e.g., 722) coupled to the analog input signal processor terminal controls Hie light
level at the set point of the photo sensor unless the communications interface commanded level in
combmation witli the phase control input signal or the IR input signal set the light at a level such
that the analog input signal can not bring it up to the photosensor set point. In that case, the analog
input signal is pegged at its upper limit, and the level is be conti-oUed by the other inputs signals.
[0055] The multiple-input ballast having a processor therein for conti-oUing a gas discharge lamp


in accordance with the present invention combines system level control and personal level control
witliin the ballast. This enables lamp fixture installations to be designed such that global control
and local, personal control, of lighting is combined in the ballast. This reduces response latency
and provides tailored control inputs and increased system design flexibility. The processor of the
multiple-input ballast utilizes software/fmnware routines for setting the lamp arc cuiTent level as a
fimction of multiple and varying command provided by the multiple input signals. The routines
determine a conunanded set {Joint of the. lamp arc current by combining the signals on each of the
processor terminal inputs. This programmable approach allows for flexibility in designing set point
algorithms and implemented complexity. Tliis programmable approach also allows for growfli to
include larger sets of set point algorithms. Also, program can be designed to dynamically react to
faults and to perform built in tests and diagnostic checks.
[0056] Fui-ther, set point algorithms can be altered and/or selected in the field. Different set point
algoritlims may be optimal for different applications. For exami)Ie, a given control input in one
appUcation can be used for local or personal control, and the same control input in a different
application can be used for building-wide or large area control. By means of unique commands on
one of the inputs, parameters or flags can be set in^the processor's memory to select the proper set
point algoritlmi. Alternatively, the digital serial interface can be used to load the required program
for each application.
[0057] In a typical prior art ballast of the type containing an active power factor correction front
end, the voltage applied to the inverter circuit is substantially D(^ As a result, the control circuit
that controls the inverter can be relatively slow as it only needs to compensate for variation in
components and changes in lamp dynamics.due to factors such as temperature and age.
[0058] In an exemplary embodiment of the present invention, the valley fill circuit 16 provides a
valley filled voltage signal 56 to the inverter circuit 18. It is not imcommon for the valley filled
voltage signal 56 to have significant AC ripple. To control the inverter 18 the processor 30 varies
the conduction time of the controllably conductive switch 74 to compensate for the significant
ripple on the valley filled voltage signal 56. To compensate for the ripple, the processor samples
the valley filled voltage signal via the sense circuit 26 sufficiently fast such that the error between
the sample being used and the actual voltage is relatively small, hi an exemplary embodiment, a
sampling rate of approximately 1 OkHz is utilized.
[0059] In one exemplary embodiment of the ballast 12, the processor 30 comprises a single analog
to digital converter (ADC). An example of such a processor is the; PICl 8F1320 microcontroller
manufactured by Microchip Technology Inc. of Chandler, AZ. The PICl 8F1320 has a built in


ADC that is used to sample analog inputs. In accordance with laiown theory, to sample a signal,
such as the valley fdled voltage signal 56 for example, at a lOldiz sample rate, preferably one
sample is talcen every 100 s. In addition to sampling the valley filled bus voltage 56 via the sense
circuit 26 and the sense signal 42, also sampled ai'e various other sense signals (e.g., sense signals
38,46, 47) and the ballast mput signals 34. Some of these signals are digital and can be applied to
the general purpose ports of the PIC 18F1320, however several of the signals are analog and utilize
an ADC. the PIC 18F1320 has multiple digital inputs, but only one analog to digital converter that
is shared by all of the inputs. As a result, only one analog input can be sampled at a time. As
laiown in the art, analog to digital converters requires a finite amount of time to sample an analog
voltage and provide a digital representation of that voltage. The PIC 18F1320 requires
approximately 32 s to perform a conversion. At most the PIC 18F1320 can sample 3 analog uiputs
in approximately 100 s. This means that it is not possible to sample all of the desired analog
signals within the sampling period of 100 s.
[0060] Figure 9 is a timing diagram depicting alternate sampling of signals in accordance with an
exemplary embodiment of the present invention. The sampling period of the timing diagram shown
in Figure 9 is 104 s. As shown, both the lamp current sense signal 46 and the valley filled voltage
signal 56 via the sense signal 42 are sampled during one sampling period. This leaves one
samplmg point to be shared between the other analog signals. In an exemplary embodiment, this
third sampling pomt alternates between sampling the lamp voltage sense signal 47 and the analog
ballast input signal 34c. In this embodiment, the valley filled voltage signal 56 via the sense signal
42 and the lamp current sense signal 46 are sampled at approximately 1 OlcHz and the lamp voltage
sense signal 47 and the analog input signal 34c are sampled at approximately 5kHz. Of course it
would be possible to add additional signals into the rotation at the third sampling point. If all of
the rotated signals appear just once in the rotation, the sampling rate for these signals would be
lOlcHz divided by the number of rotated signals. Of course Hiere is no reason that a rotated signal
must appear only once in the rotation. For example, given three signals A, B and C, the rotation
could be ABAC such that signal A is sampled at twice the rate of signals B or C.
[0061] hi the embodiment shown in Figure 9 the actual sampling period is 104 s. This period is
sufficient to allow three analog to digital samples per period. In addition, tliis sampling period is
convenient for receiving DALI commands since the half-bit period of the DALI protocol is 416 s.
Sampling the DALI port once per 104 s samphng period gives a total of 4 samples per half-bit and
thus 8 samples per bit. Multiple samples per bit are advantageous because the DALI
communication link and the ballast control loop are not synchro] lized.


[0062] In an exemplary embodiment, the desired sampling period for the IR ballast input signal
(e.g., signal 34d) is 572 s. However, 572 s is not an integer multiple of the control loop sampling
period of 104 s. One approach is to sample the IR ballast input signal alternately every 5^' or 6"^
pass tlrough the control loop sampling time. Tliis results in an average sampling time of 572 s.
[0063] Figure lOA and Figure lOB are a flowchart of an inten-upt service routuie in accordance
with an exemplaiy embodiment of the present invention. A tuner in the PIC18F1320 is setup to
trigger an interrupt every 104 s. When this inten-upt occurs, an interrupt service routine is called.
Figure lOA and Figure lOB show a flowchart for tliis mteiTupt service routine. In an exemplary
embodiment, tliis service routine controls the sampling shown in Figure 9 and also handles sending
and receiving DALI bits via the communications signal (port 34b) and the IR signal (port 34d).
[0064] The entry point for the routine is at step 210. At step 212, the processor fetches and stores
the last sample from the analog to digital converter (ADC). Tliis sample is a sample of the current
sense signal 46. After fetching this signal, the processor configures and starts the ADC to read the
valley filled voltage signal via sense signal 42. As previously di^scribed, this sample will not be
available for approximately 32 s so the processor has time for other tasks. In the next step 214, the
processor updates the lamp cixrrent feedback loop using the latest samples of current sense signal 46
and the valley filled voltage sense signal 42. This control loop is implemented using well known
digital control methods. In step 216, the processor updates the pJiase control input filter. This filter
is implemented as a digital low pass filter. The output of tliis filter represents the duty cycle of the
phase conti"ol input. The input to the phase control input filter is determined as follows. Every
time the 104 s interrupt routine reads an ADC value it also reads the state of the phase control input
34a. This input will be either a 1 or a 0. The first time this mput is sampled during the 104 s
interrupt it is given a weight of 47 while the following two samples receive a weight of 40. these
weights are based on how much time has passed since the port v^as last read. At the end of a first
pass through the 104 s interrupt, the sum of these weighted samples is between 0 and 127. At the
end of a second pass tlirough the 104 s interrupt the sum of all of the weighted samples from
current and previous 104 s interrupt will be between 0 and 254. It is this sum that is provided to
the phase control input filter.
[0065] At step 218 the processor checks to see if a DALI message is in the process of being sent.
If so, the processor goes to step 220 where it determines the proper state of the DALI output port.
At step 224 the processor checks to see if the latest ADC sample is ready. If the sample is not yet
ready, the processor proceeds to step 222 where it executes one of a sequence of low priority tasks.
After completing a low priority task it goes back to step 224 to recheck the status of the ADC. As


long as the ADC is not ready, the processor continues the loop of executing one of a sequence of
low priority tasks at step 222 and then recheclcing the ADC at step 224. Once it is determined that a
new ADC sample is ready, the processor moves to step 226 where it fetches fliis new sample and
saves it as the latest sample of the valley filled voltage signal 42. The processor then sets up and
starts then next ADC sample. As previously described this nex-t sample may be one of a rotation
of inputs. In an exemplaiy embodiment, tliis sample pomt alternates between a sample of the lamp
voltage sense signal 47 and tire analog input signal 34c. After starting tliis conversion, the
processor proceeds to step 228 whereat checks for faults on the DALI port. Next at step 230 the
processor reads and stores the ciuTent state of the DALI mput port. It then uses this sample along
with previous samples to recognize incoming messages. At ste]) 232 the processor checks to see if
it is time to sample the IR input signal 34d. As previously desaibed, the IR port is not read on
every pass througli the 104 s sample period, but is instead read alternately every 5^ or 6* time it
reaches this step. If it is time to sample the input, a sample is taken and saved in memory. At step
236 the processor checks to see if the latest ADC sample is ready. If the sample is ready it moves
on to step 238. If the sample is not ready it proceeds to step 234 and the system operates in the
same type of sequence as described for steps 224 and 222 where low priority tasks are executed
between checks of the status of the ADC sample. At step 238 the latest ADC sample is fetched
and stored in a memory location corresponding to the current input m the rotation. The ADC is
then setup and started to sample the cuixent sense signal 46. the resulting sample will be fetched in
step 212 on the next pass through the interrupt service route At step 240 tins latest rotation sample
fetched in step 238 is processed and then the processor exits the interrupt service routine at step
242.
[0066] The multiple-input ballast having a processor therein provides bidirectional
communication between the ballast and other devices, such as ballasts, other lighting loads, and
conti'ollers. Tliis allows the ballast to initiate unsolicited transmissions to the other devices.
Further, the ballast processor via the communications terminal is compatible with existing systems
utilizmg the DALI communications protocol, allowing the ballast to assume the role of master or
slave. Also, the multiple-input ballast is addressable via the IR, or other, processor input terminal.
[0067] Altliough illustrated and described herein with reference to certarnspecific embodiments,
tliC^esent invention is nevertheless not intended to be limited to the details sho^^Rather,
various modifications may be made in the details witliin the scope and range of equivalents of the
claims and witliout departing from the invention.

WE CLAIM :
1. An electronic ballast for driving a gas discharge lamp, comprising: an
inverter for producing a high frequency drive voltage for driving a lamp current in
said gas discharge lamp, said drive voltage having an operating frequency and an
operating duty cycle; a microprocessor electrically connected to said inverter for
directly controlling said inverter to control said lamp current, said microprocessor
operable to provide an output signal to said inverter, such that said operating
frequency and said operating duty cycle of said drive voltage are substantially the
same as a frequency and a duty cycle of said output signal; and a port in electrical
communication with said microprocessor for sending a first message from said
microprocessor comprising at least one command and for sending a second
message from said microprocessor comprising at least one ballast configuration
onto a communication link operable to connect said electronic ballast to at least
one other electronic ballast connected to said communication link, wherein: said
microprocessor is operable to send the first message to said at least one other
electronic ballast to control the operation of said at least one other electronic
ballast, and to send the second message to said at least one other electronic
ballast to inform said at least one other electronic ballast of its configuration to
enable said at least one other electronic ballast to use said ballast configuration
message to adjust its operation.
2. An electronic ballast for driving at least one gas discharge lamp, comprising:
an inverter circuit producing a high frequency drive voltage for driving a lamp
current in said at least one gas discharge lamp, said drive voltage having an
operating frequency and an operating duty cycle; a microprocessor connected to
said inverter, said microprocessor directly controlling said inverter to control said
lamp current to a desired level, said microprocessor operable to provide an output
signal to said inverter, such that said operating frequency and said operating duty
cycle of said drive voltage are substantially the same as a frequency and a duty
cycle of said output signal; and at least two ports connected to said
microprocessor, each of said ports being capable of at least one of sending and
receiving messages comprising at least one of a command and a ballast
configuration, at least two ports connected to said microprocessor, wherein: a first
one of said at least two ports is adapted to be coupled to a digital communication
link, said digital communication link operable to connect said electronic ballast to at
least one other electronic ballast, said first port transmitting on to said digital
communication link a ballast configuration message to inform said at least one
other electronic ballast of the ballast configuration of said electronic ballast to
enable said at least one other electronic ballast to adjust its operation based on
said ballast configuration; a second one of said at least two ports is adapted to
receive a ballast control signal from a remote transmitter or a sensor to control
operation of said electronic ballast, said microprocessor receiving said ballast
control signal; and said microprocessor is operable to send a command over said
digital communication link to said at least one other electronic ballast to control the
operation of said at least one other electronic ballast in response to receiving said
ballast control signal.
3. The electronic ballast as claimed in claim 1, wherein said inverter comprises
a controllably conductive device, said microprocessor operable to control said
controllably conductive device between conductive and non-conductive states to
produce said drive voltage.
4. The electronic ballast as claimed in claim 3, wherein said microprocessor
controls said controllably conductive device to said non-conductive state when a
current through said controllably conductive device reaches a threshold level.
5. The electronic ballast as claimed in claim 4, wherein said inverter comprises
a transformer characterized by a magnetizing inductance, said microprocessor
operable to use a computational model of said magnetizing inductance to
determine when said current through said controllably conductive device reaches
said threshold level.
6. The electronic ballast as claimed in claim 5, composing: a rectifier for
receiving an AC line voltage and producing a rectified voltage; wherein said
microprocessor receives a control signal representative of an instantaneous
magnitude of said rectified voltage.
7. The electronic ballast as claimed in claim 6, vi/herein said microprocessor
uses said control signal to compute the time at which said current through said
controllably conductive device reaches said threshold level as part of said
computational model.
8. The electronic ballast as claimed in claim 6, wherein said microprocessor
computes said duty cycle of said output signal using said instantaneous magnitude
of said rectified voltage.
9. The electronic ballast as claimed in claim 1, wherein said microprocessor is
operable to receive a plurality of ballast sense signals.
10. The electronic ballast as claimed in claim 9, wherein said microprocessor is
operable to determine if said gas discharge lamp has started in response to a
ballast sense signal representative of the magnitude of said current through said
gas discharge lamp.
11. The electronic ballast as claimed in claim 9, wherein said microprocessor is
operable to determine, in response to said ballast sense signals, if said lamp is
operating properly or if a fault condition exists.
12. The electronic ballast as claimed in claim 1, wherein said microprocessor
controls pre-heating and striking said lamp.
13. The electronic ballast as claimed in claim 12, wherein pre-heating said lamp
comprises heating filaments of said lamp, and striking said lamp comprises
Increasing a magnitude of said drive voltage over a programmed interval to strike
an arc in said lamp.
14. The electronic ballast as claimed in claim 1, wherein said microprocessor is
operable to transmit messages to a second ballast via said port.
15. The electronic ballast as claimed in claim 14, wherein said command
comprises a command for said second ballast to control the operation of a second
gas discharge lamp connected to said second ballast.
16. The electronic ballast as claimed in claim 1, wherein said ballast
configuration comprises a light output level of said ballast.
17. The electronic ballast as claimed in claim 1, wherein said port is adapted to
be coupled to a digital communication link.
18. The electronic ballast as claimed in claim 17, wherein said digital
communication link comprises a DALI protocol link.
19. The electronic ballast as claimed in claim 1, wherein said port comprises an
infrared transmitter.
20. The electronic ballast as claimed in claim 1, wherein said port comprises a
radio frequency transmitter.
21. The electronic ballast as claimed in claim 1, wherein said microprocessor
modulates the pulse width of said control signal to control said inverter.
22. The electronic ballast as claimed in claim 2, wherein a first one of said ports
is adapted to be coupled to a digital communication link.
23. The electronic ballast as claimed in claim 22, wherein a second one of said
ports comprises an infrared receiver for receiving infrared signals.
24. The electronic ballast as claimed in claim 23, wherein said digital
communication link comprises a DALI protocol link.
25. The electronic ballast as claimed In claim 23, wherein said digital
communication link comprises a radio frequency communication link.
26. The electronic ballast as claimed in claim 2, wherein the ballast input signal
comprises an infrared electrical signal from an infrared transmitter.
27. The electronic ballast as claimed in claim 26, wherein the infrared electrical
signal comprises a command to turn said gas discharge lamp on or off.
28. The electronic ballast as claimed in claim 2, wherein the ballast input signal
comprises a radio frequency signal from a radio frequency transmitter.
29. The electronic ballast as claimed in claim 2, wherein the ballast input signal
comprises a sense signal from a photosensor.
30. The electronic ballast as claimed in claim 2, wherein the ballast input signal
comprises a signal from an occupancy sensor.

Documents:

02323-kolnp-06 abstract.pdf

02323-kolnp-06 claims.pdf

02323-kolnp-06 correspondence others.pdf

02323-kolnp-06 description(complete).pdf

02323-kolnp-06 drawings.pdf

02323-kolnp-06 form-1.pdf

02323-kolnp-06 form-3.pdf

02323-kolnp-06 form-5.pdf

02323-kolnp-06 international publication.pdf

02323-kolnp-06 international search authority report.pdf

02323-kolnp-06 pct form.pdf

02323-kolnp-06 priority document.pdf

02323-kolnp-2006 correspondence.pdf

02323-kolnp-2006 form-18.pdf

02323-kolnp-2006-correspondence others-1.1.pdf

02323-kolnp-2006-gpa.pdf

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Patent Number 248591
Indian Patent Application Number 2323/KOLNP/2006
PG Journal Number 30/2011
Publication Date 29-Jul-2011
Grant Date 27-Jul-2011
Date of Filing 16-Aug-2006
Name of Patentee LUTRON ELECTRONICS CO., INC.
Applicant Address 7200 SUTER ROAD, COOPERSBURG, PENNSYLVANIA
Inventors:
# Inventor's Name Inventor's Address
1 VESKOVIC, DRAGAN 1702 REDWOOD COURT, ALLENTOWN, PENNSYLVANIA 18104
2 TAIPALE, MARK 260 BRENTON CIRCLE, HARLEYSVILLE PENNSYLVANIA 19438
3 SKVORETZ, MATTHEW 913 CREST WAY, EMMAUS, PENNSYLVANIA 18049
4 SPIRA, JOEL, S. 1506 PLEASANT VIEW ROAD, COOPERSBURG, PENNSYLVANIA 18036
5 ANSELMO, ROBERT, A. 1164 CLEARWOOD DRIVE, ALLENTOWN, PENNSYLVANIA 18103
PCT International Classification Number H05B 41/282
PCT International Application Number PCT/US2005/004721
PCT International Filing date 2005-02-09
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 10/824,248 2004-04-14 U.S.A.
2 60/544,479 2004-02-13 U.S.A.