Title of Invention

'A SYSTEM FOR RAPID CONFIGURATION OF A PROGRAMMABLE LOGIC DEVICE'

Abstract The present invention relates to a system for rapid configuration of reconflgurable devices with a plurality of latches. The number of clock cycles for loading the configuration data are reduced by a substantial amount and the fidelity of data loaded into the configuration latches is high. The invention also incorporates procedures for configuring multiple reconflgurable devices, which are similar to the prevalent "Daisy chain" technique. (Reference - Figure 2)
Full Text The. present invention relates to a system for rapid configuration of a programmable Logic Device.
Background of the invention:
Programmable logic device, in particular FPGAs and CPLDs consist of a plurality of memory elements/reconfigurable elements with the primary purpose of storing circuit information and controlling the programmable logic circuit behaviour. The reconfigurable elements in FPGAs / CPLDs are usually CMOS latches. These latches store information/data bits that decide the lookup table logic, the routing information, and other details which are solely dependent on the circuit being implemented in the given device. As the number of these latches is large, it takes quite some time to configure the FPGA/CPLD for a given circuit implementation. The configuration data is generated by the software tools that map, place and route the input circuit netlist.
The known schemes use the straightforward concept as illustrated in figure 1 of the accompanying drawings. The configuration latches are connected as arrays of latches[ll] with the write signal of the latches in rows tied together [5]. A shift register structurefl] exists beside the latch array which enables the write signal of the latches in rows, one row at a time. The write activation bit[4] shifts across the array to activate the write signals in rows. Another shift register[3] exists whose length is equal to the number of columns in the latch array. The purpose of this register is to serially accept a data frame that is to be loaded into a particular row of the latch array. The length of this register may vary depending on any error correction or parity cheek circuits that might have been incorporated. A data frame is fully loaded into the shift register[3] in "n" clock cycles, where "n" is the length of the shift register [3]. A few more clock cycles are consumed in advancing the write control bit in the shift register [1]. There may exist another write signal WR that activates only after the data frame to he
loaded into [3] and the write control bit in the write control shift register[l] are in place. The data frame load and the write signal increment[4] continue until all the configuration bits are loaded into the device. The control circuitry for executing and synchronizing the data frame load and the write increment operation is not shown and is well known to those skilled in the art. Thus, in the prior art, the total number of clock cycles needed to configure an FPGA/CPLD is greater than the total number of configuration latches in the given FPGA/CPLD.
In US patent no. 5,995,988 serial loading of bits in groups has been described which takes longer time for loading.
The object and summary of the invention:
The object of this invention is to reduce the clock cycles by presetting all the configuration latches to a predetermined state and then selectively change states of specific configuration latches in the latch array.
To achieve the said objective this invention provides a system for rapid configuration of a programmable logic device characterized in that:
first means for selecting a logically continuous array of bits out of
the total configuration map,
a second means for selecting one or more of said bits in said
selected arrays that require to be toggled, and
a third means for changing said selected bits.
The said first means is a write control shift register for selecting a row of the configuration memory of said programmable logic device.
The said selecting one or more of second means is a decoder for selecting one column at a time of the configuration memory of said programmable logic device.
The said third means is a pass transistor for connecting the input of memory latch storing said bit to a logic '0' or logic '1' level.
Means is provided to generate the shift signal for the write control shift register (WCSR), by a combination of a defined output of said second means and a clock signal.
The said means is an AND Gate. The said decoder is a binary decoder.
Multiple programmable logic devices are enabled sequentially by means of a sequencing mechanism.
A counter is provided with said programmable logic device for selecting the programmable logic device location and is stopped by signal generated by said programmable logic device.
The input to said decoder is from a memory containing the addresses of the locations of bits / bit clusters that are to be changed.
The said memory contains the values of only those locations that are differing in the present configuration from the desired values in the new configuration, so as to minimize memorv size and configuration time.

The said configuration memory is programmed in multiple bits at a time, using a plurality of selection means and toggling means.
The said selection means are decoders.
The said sequencing mechanism is a Daisy Chain mechanism.
Brief Description of the drawings:
The invention will now be described with reference to the accompanying drawings.
Fig 1 shows prior art for loading of configuration data in a programmable logic device consisting of reconfigurable elements.
Fig 2 shows a system for configuring a programmable logic device, according to this invention.
Fig. 3 shows the arrangement for selective programming of '0' values in one row of the configuration 'memory.
Fig. 4 shows the arrangement for selective programming of '0' values in a multiplicity of rows of the configuration memory.
Fig. 5 shows the basic arrangement for programming a '0' or T value in a single latch of the configuration memory.
Fig. 6 shows the latch structure of the configuration memory of the FPGA/CPLD.
Fi'i. 7 shows the arrangement for controlling the selective programming of the configuration memory using a counter and a memory device, according to this invention.
Fig. 8 shows the configuration of more than one FPGA/CPLD device connected in a Daisy Chain.
Fig 9 shows a sample memory content.
Fig. 10 shows an arrangement for programming multiple values simultaneously using a plurality of decoders and/or shift registers.
Detailed Description of the invention:
Referring to the embodiment in figure 2, [11] represents the array of latches arranged in an identical fashion as in the prior art. The decoder [8] has 'n' inputs [9] and 2n outputs [10, 10b]. WCSR is a control signal generated by the decoder and a clock signal for the write control bit in the shift register [1] and is explained later. Assuming 8 inputs [9] to the decoder [8] in the present embodiment there will bz 256 outputs, i.e. K=255. This also implies that mere will be 255(explained later) columns in the latch array of the present embodiment. Figures 3 and 4 illustrate details of figure 2. The gates of write pass transistors [2b] in each row of the latch array are tied together and connected to the write control shift register [1]. It can also be seen that one end of the pass transistors [2b] in a column are tied together and connected to a pull down n-channel pass transistor [lOa] whose gates are controlled by the decoder output. The write control shift register [1 ] shifts the write signal bit in order to activate one row of the latch array at a time. The 8 lines entering the decoder [8] receive signals from the memory software-hardware interface that contains configuration data.
The following sequence of events best explain the configuration for the present embodiment:-
1. A global signal resets all the latches in the array such that all nodes Z in
figure 5 are preset to logic 1. Figures 6 illustrates the basic latch structure
used in the present embodiment of the proposed invention and are well
known to those skilled in the art.
2. If an on board memory is used to store the configuration bits, the data is
organized such that the memory contains locations of those latches in the
configuration latch array whose data is required to be toggled to logic 0.
It is apparent that the memory output will correspond to the decoder
input, and as such will be 8 bits wide.
3. Referring to figures 2 and 3, a data frame may be 255 bits wide, in order
to eliminate the WR signal in the prior art (figure 1) altogether. One of
the 256 possible outputs from the decoder is wired as a WCSR.
preferably the zero output, which of course corresponds to the zeroth
output or X0. This output comes into picture during the transition interval
of the write control shift register signal (WCSR) to an adjacent row in the
latch array. The WCSR signal acts as a clock to the write control shift
register [1] that shifts a logic 1 across the shift register[l]. the rest of
which is all set to logic zero. It is similar in operation to a ring counter
and is well known to those skilled in the art. In other words once a row in
the latch array is configured, the decoder input is made zero and only then
does the WCSR signal shift the activation bit[logic 1] to an adjacent
register cell in the shift registerf 1 ] in order to enable the adjacent row in
the latch array for configuration. The zeroth output of the decoder X0 [5]
is ANDed with a clock fclk] to synchronize the operation. This clock is
preferably the clock driving the counter [15].
It is clear by now that the latch array is configured one row at a time. The first cell (bottom-most cell in figure 2) of the shift register[l] is initialized to logic 1 to initiate ring counter operation. A configuration clock drives a counter which begins the configuration process by addressing the memory contents as it advances count. The memory address bus[14] is connected to the counter output. The 8 bit wide memory output[9] addresses the decoder[8] inputs which in turn pulls down the latch array cells in that order, in the enabled row. Once the desired latch cells in the row have been pulled down, a zero output from the memory to the decoder pulls up the WCSR, which in turn advances the shift register[l] at the arrival of the synchronizing clock [elk]. Now the row adjacent to the previous one is enabled in the latch array. The process continues till the device is fully/partially configured, depending on the design. An important point to note is that the individual row data stored in the memory is separated by a zero, so as to generate the WCSR signal properly. Figure 9 shows a sample memory's content. Shaded regions are logic ones[13a] and non-shaded regions are logic zeros[13b]. It can be seen that 'a' 'b' and V point out the zero data which demarcate configuration information to be addressed to different rows. Other than synchronizing the WCSR signal the synchronizing clock [elk] becomes very important when the memory [13] contains consecutive zeros. These zeroes indicate row skip operations which would not have been carried out if decoder output Xo [5] would directly drive the WCSR line.
Once the configuration is complete, the counter may be halted by a signal generated by the FPGA/CPLD. Referring to figure 7 which shows a top level of the device, the configuration memory[13] and the counter[15], configuration is enabled by a START signal & inhibited by a DONE signal. These signals can be generated in many known ways.
More than one device can be configured by a technique illustrated in figure 8. This scheme is similar to the Daisy chain technique used for configuring multiple FPGAs in current day devices. START and DONE signals are sequentially connected to enable configuration for devices 1,2 and 3; in that order. The memory output bus is common to the decoder inputs of the three devices. Counter operation and memory organization remain the same as for a single device, the only difference being in counter and memory size for accommodating data for the three devices.
The aforementioned methodologies for the configuration of FPGAs/CPLDs is last compared to the previous techniques. But at the same time the proposed technique has a major memory overhead, which can be minimized by clever design and configuration data manipulation. Some possible embodiments of the present invention, which minimize the memory overhead are now described.
In one embodiment of the present invention the latches may be pulled up instead of being pulled down by the decoder arrangement. It can be decided whether to incorporate pull up or pull down transistors by assessing the configuration bit stream for logic zeros & ones. The FPGA/CPLD can be designed so as to maximize logic zeros or logic ones for its configuration latches during circuit implementation in the device. Another advanced embodiment is possible which has the flexibility of both pulling up & pulling down of configuration latches. Such an FPGA'CPLD could be reconfigured from some present configuration without presetting all the latches to logic zero or logic one. The memory driving the decoder is loaded with only the contents of those configuration memory location that are different in the new configuration map with respect to the present contents.
The schemes described till now talk only about changing/toggling single bits in the configuration latch array. Other interesting embodiments of the present invention are possible which address the issue of granularity. A decoder hierarchy, in which a plurality of decoders in different hierarchies selects variable chunks of configuration latches in the array, is possible and thus, extending the invention to a coarser latch array. Referring to figure 10, a decoder [16a] can select latches in groups of four [17]. These latches[17a] can further be loaded with the desired data through a secondary decoder or a serial-in parallel-out shift register [16b].
Thus, an in-circuit, rapid reconfiguration is attainable by the proposed configuration architecture and its embodiments. The decoders used in various embodiments of the present invention can also be reused as FPGA/CPLD logic resources once the configuration process is complete. This resource sharing may not be possible in some embodiments.






We claim:
1. A system for rapid configuration of a programmable logic device
including a configurable memory (13), said system characterized in
that,
first means (1) for selecting a logically continuous array of bits out
of the total configuration map,
a second means (8) for selecting at least one of said bits in said
selected arrays that require to be toggled, and
a third means for changing said at least one selected bits.
2. The system as claimed in claim 1, wherein said first means is a write
control shift register for selecting a row of the configuration memory of
said programmable logic device.
3. The system as claimed in claim 1, wherein said second means is a
decoder for selecting one column at a time of said configuration memory
of the programmable logic device.
4. The system as claimed in claim 1 wherein said system includes a memory
latch for storing at least one bit and wherein said third means comprises a
pass transistor for connecting the input of memory latch to a
predetermined logic value.
5. The system as claimed in claim 2 wherein means is provided to generate
the shift signal for the write control shift register (WCSR), by a
combination of a defined output of said second means and a clock signal.
6. The system as claimed in claim 5, wherein said means is an AND Gate.
7. The system as claimed in claim 3, wherein said decoder is a binary
decoder.
8. The system as claimed in claim 1 wherein said system comprises a
sequencer for allowing the system to sequentially configure a plurality of
programmable logic devices.
9. The system as claimed in claim 1 wherein said programmable logic
device comprises a counter (15) for selecting the programmable logic
device location and is stopped by signal generated by said programmable
logic device.
10. The system as claimed in claim 8 wherein said sequencer is a Daisy
Chain sequencer.
11. The system as claimed in claim 1 wherein said configuration memory is
configured in multiple bits at a time, using a plurality of selection means
and toggling means.
12. A system for rapid configuration of a programmable logic device
including a configurable memory substantially as herein described with
reference to and as illustrated in the accompanying drawings.

Documents:

138-del-2001-abstract.pdf

138-del-2001-claims cancelled].pdf

138-del-2001-claims.pdf

138-del-2001-complete specification (granted).pdf

138-del-2001-correspondence-others.pdf

138-del-2001-correspondence-po.pdf

138-del-2001-description (complete).pdf

138-del-2001-drawings.pdf

138-del-2001-form-1.pdf

138-del-2001-form-13.pdf

138-del-2001-form-18.pdf

138-del-2001-form-2.pdf

138-del-2001-form-3.pdf

138-del-2001-pa.pdf

abstract.jpg


Patent Number 248371
Indian Patent Application Number 138/DEL/2001
PG Journal Number 28/2011
Publication Date 15-Jul-2011
Grant Date 07-Jul-2011
Date of Filing 09-Feb-2001
Name of Patentee STMICROELECTRONICS LTD.,
Applicant Address PLOT NO. 2 & 3, SECTOR 16A, INSTITUTIONAL AREA, NOIDA-201 3001, UTTAR PRADESH
Inventors:
# Inventor's Name Inventor's Address
1 ANKUR BAL KF-56 KAVI NAGAR, GHAZIABAD-201 002, U.P., INDIA.
PCT International Classification Number G11C 7/00
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA