Title of Invention

"AN INSULATED GATE DEVICE"

Abstract An insulated gate semiconductor device (30) includes a gate (34), a source terminal, a drain terminal and a variable input capacitance at the gate. A ratio between the input capacitance (CfiSS) when the device is on and the input capacitance Cfiss when the device is off is less than two and preferably substantially equal to one. This is achieved in one embodiment of the invention by an insulation layer (32) at the gate having an effective thickness dins than a minimum thickness.
Full Text FAST SWITCHING POWER INSULATED GATE SEMICONDUCTOR DEVICE
TECHNICAL FIELD
THIS invention relates to insulated gate semiconductor devices such as metal oxide silicon field effect transistors (MOSFET's), more particularly to such devices for use in power switching applications and to a method of driving such devices.
BACKGROUND ART
In known MOSFET structures, it is presently preferred to minimize the gate voltage VGS required for switching of the device and which then implies a relatively large input gate capacitance. •
Capacitance inherent in the gate structures of insulated gate devices limits the switching speeds of these devices. It is also well known that the Miller effect has an influence on the input capacitance at the gate of devices of the aforementioned kind in that the input capacitance of a typical commercially available MOSFET varies during switching of the device. The input capacitance has a first value C,,M when the device is off and a second value Cfies when the device is on. The ratio of the second and first values for a known and commercially available IRF 740

power MOSFET is in the order of 2.5. It has been found that such a ratio impairs the switching speed of these devices.
The total switching time TB of the IRF 740 MOSFET to switch on is made up by the sum of a turn-on delay time Tdon of about 14ns and a drain source voltage fall time Tf of about 24ns and is equal to about 38ns. The corresponding time to switch off is about 77ns. These times are too long for some applications.
OBJECT OF THE INVENTION
Accordingly, it is an object of the present invention to provide an insulated gate device and method and circuit of driving such a device with which the applicant believes the aforementioned disadvantages may at least be alleviated.
SUMMARY OF THE INVENTION
According to the invention an insulated gate device comprises a gate connected to a gate terminal and having a variable input capacitance at the gate terminal as the device is switched between an off state and an on state, a ratio between a final value of the capacitance when the device is on and an initial value of the capacitance when the device is off is smaller than 2.0.

The aforementioned ratio is preferably less than 1.5, more preferably less than 1.4, even more preferably less than 1.3, still more preferably less than 1.2 and most preferably substantially equal to 1.
The device may comprise a semiconductor device, preferably a field effect transistor (FET) more preferably a power metal oxide silicon field effect transistor {MOSFET) such as a V-MOS, D-MOS and U-MOS.
The MOSFET may have a vertical structure in that the gate and a source of the device are provided on one face of a chip body of the device and a drain of the MOSFET is provided on an opposite face of the body.
The device may comprise a capacitor connected between the gate terminal and the gate of the device.
The capacitor may be integrated on the chip body and in one embodiment may be superimposed on the gate of the device.
Alternatively, the capacitor is a discrete component connected in

series between the gate and the gate terminal and packaged in the same package.
The gate may be connected directly to a fourth terminal of the device.
In this specification the invariant device parameter (p) is used to denote the effective dielectricum thickness of a conduction channel of the device in the off state, which is defined as the product of an effective gate capacitance area (A) and the difference between an inverse of a first value of a gate capacitance of the insulated gate device, that is when the device is off and an inverse of a second value of the gate capacitance, that is when the device is on. That is:
According to one aspect of the invention there is provided an insulated gate device comprising a gate and an insulation layer at the gate, the layer having an effective thickness (d) of at least a quotient of the device parameter as defined and a ratio of maximum charge accommodatable on the gate and a minimum charge required on the gate for complete switching, minus one (1). That is:

where Oclaimed is the maximum allowable steady state charge for safe operation and OCLAIMED, is the minimum charge required for complete switching.
According to another aspect of the invention there is provided an insulated gate device comprising a gate, the device having a capacitance at the gate which is a function of the effective thickness of an insulation layer at the gate, the effective thickness of the layer being selected to ensure that a first ratio between a final value of the capacitance when the device is on and an initial value of the capacitance when the device is off is smaller or equal to a second ratio of a maximum charge receivable on the gate and a charge required to reach a threshold voltage of the gate of the device.
According to yet another aspect of the invention there is provided an insulated gate device comprising a gate, the device having a capacitance at the gate which is a function of the effective thickness of an insulation layer at the gate, the effective thickness of the layer being selected to ensure that a first ratio between a final value of the capacitance when the device is on and an initial value of the capacitance when the device is off is smaller or equal to a second

ratio of a maximum voltage applyable to the gate and a threshold voltage required on the gate to switch the device on.
According to yet another aspect of the invention there is provided a method of driving an insulated gate semiconductor device, the device comprising an insulation layer at a gate thereof providing a capacitance which varies between an initial value when the device is off and a final value when the device is on, the method comprising the step of depositing at least a Miller charge on the gate while the capacitance has said initial value.
The method preferably comprises the step of depositing substantially sufficient charge for a desired steady state switched on state of the device on the gate while the capacitance has said initial value.
The invention also extends to a drive circuit for a device as herein defined and/or described.
BRIEF DESCRIPTION OF THE ACCOMPANYING DIAGRAMS
The invention will now further be described, by way of example only, with reference to the accompanying diagrams wherein:

figure 1 is a schematic representation of a known insulated gate
semiconductor device in the form of a power MOSFET; figure 2{a) is a diagrammatic representation of a gate structure of
the MOSFET while it is off; figure 2(b) is a diagrammatic representation of a gate structure of
the MOSFET when ft is partially on; figure 2(c) is a diagrammatic representation of a gate structure of
the MOSFET when it is fully switched on; figure 3 is a schematic representation of a first embodiment of a
power MOSFET according to the invention; figure 4 is a typical graph for the steady state of gate-to-source
voltage against total gate charge marked A of a
conventional MOSFET as well as various similar graphs
marked B for MOSFET's according to the invention; figure 5 is a graph of total switching time against a ratio of initial
charge transferred to the gate and the Miller charge of a
variety of MOSFET's; figured is a graph of drain-source rise time against turn-on delay
time of a variety of MOSFET's; figure 7 is a graph of minimum and maximum gate source
voltages required on a MOSFET according to the
invention against total switching time;

figure 8{a) are oscillographs of VGS and VDS against time for a
MOSFET with a ratio C^/C^.* 2.16; figure 8{b) are similar graphs for a MOSFET with a ratio C^/C^ «
1.63; figure 8(c) are similar graphs for a MOSFET with a ratio CnJCraa *
1.34; figure 8(d) are similar graphs for a MOSFET with the ratio C^IC^ «
1.17; figure 9 is a schematic representation of a second embodiment of
the MOSFET according to the invention; figure 10 is a schematic representation of a third embodiment of the
MOSFET according to the invention; figure 11 is a block diagram of another embodiment of the device
according to the invention; and figure 12 is a basic diagram of drive circuit for a device according to
the invention.
DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
A known insulated gate device in the form of a known power metal oxide silicon field effect transistor (MOSFET) is generally designated by the reference numeral 10 in figure 1.

The MOSFET 10 comprises a gate 12, a drain 14 and a source 16. The device 10 has a gate capacitance CQ between the gate and the source.
It is well known that when a voltage VQS is applied to the gate as shown at 80 in figure 8(a), charge is deposited on the gate causing the device to switch on and a voltage VDS to switch from a maximum value shown at 82 to a minimum value shown at 84. Similarly, when the charge is removed from the gate, the device is switched off and the voltage V^ switches to the maximum value.
The total switching time T8 (illustrated in figure 8(a}) is constituted by the sum of a turn-on delay time T^ and a rise time Tr. The turn-on delay time is defined to be the time between rise of the gate-to-source voltage VGS above 10% of its maximum value and the onset of drain-to-source conduction, that is when the voltage V^ has decreased by 10%. The rise time is defined as the time interval corresponding to a decrease in VDS from 90% to 10% of its maximum value when the device is switched on.
Referring to figures 2(a) to 2(c), in the known devices, the gate capacitance CG may be modelled as effectively comprising two capacitors Ca and Cc in series. As shown in figures 2(a) to 2(c) the first

ID
capacitor Cg is an invariable capacitor and its value scales to 11d, being the effective thickness (d) of an insulation layer 18 at the gate of the device. The second capacitor Cc is a variable capacitor having a value of oo when the device is switched on as shown in figure 2(c), a value of A/ocmax when the device is off as shown in figure 2(a) and a value of A/a (with 0 CG= 1/[1/Ca(d) + 1/C0(«c)]
= A/(d+oc)
where A is an effective area, which includes proper normalization constants. Thus, oc is a maximum (°cmax) when the device is switched off as shown in figure 2(a) and oc = 0 when the device is switched on as shown in figure 2(c).
Hence, the device has a gate or input capacitance with a first value CflM when the device is off and a second value Cte when the device is on. The capacitance retains the first value until the Miller effect takes effect.
An effective maximum conduction channel dielectricum thickness (p) = ocmgx is defined, which is proportional to a difference in the inverse of the gate capacitance when the device is off CBM and when the device is on CfiM, that is:

pSA{1/CliM-1/CfJ= ocmax.
fl *^* CC mnv
The ratio C^ / CBM may be written as
As shown in figure 3, according to the invention by increasing the effective thickness dins of the insulation layer 32 at the gate 34 and hence by decreasing the gate capacitance CQ/ the total switching time Ts of a MOSFET 30 may be decreased. A minimum value for the effective thickness dins is given by:
wherein Q3linin) is the minimum charge required for complete switching and wherein QQ|inax| is the maximum allowable gate charge on the device which includes a safety margin. Destruction will occur when
Defining VGS(minl as the minimum gate voltage for complete switching and Vosimoo as the maximum allowable gate voltage on the device, before damage to the device, it is known that OG^ / O^, > VGS(milx) / VQS(mW. This inequality implies a slightly larger limit than that calculated from the charge ratios QQ,^ / QG(mW :

With this minimum effective thickness for dIns the switching time of the device is mainly limited by the gate source inductance and capacitance. By increasing dint beyond this minimum, allows for reducing the rise or fall time by compensating for the source inductance L, voltage ES during switching and which is: ES = L,di/dt + iR.
t* (max)K U lostmaxl / Ts + l[3s|max) Re-
in Table 1 there are provided relevant details of four differently modified MOSFET's with progressively decreasing gate capacitance, CG.
(Table Removed)



For a conventional 1RF 740 MOSFET:
e.in»x)« 7.4 nH (40 A/27 ns) + 4 volt = 15 volt
VG(Inwnal)*VGSlmaxl- ss(mjlX)= 20. volt - 15 volt = 5 volt For the device in row iv of Table 1
es(m»o* 7.4 nH (40 A/2.5 ns) + 5 volt = 123 volt VQ.M « VQS(max) - eslmax)» 200 volt - 123 volt = 77 volt
From this example it is clear that VBpntiina0 is still larger than the modified threshold gate voltage VGSTM = VGS(mbl, = 73 volt, shown in figure 4, and the slow rise time due to the Miller effect is thus effectively counteracted. It follows that minimization of the product LgCaM minimizes the switching time Ts of the device, assuming the combined gate and source serves resistance is negligible.
If a gate voltage, VQS, substantially larger than the threshold gate voltage, VGST, is supplied in a time much shorter than the turn-on delay time, the latter may be approximated as: Tdon*(2/3)(L8CiiJIt can be shown that:

which indicates that the total switching time is reduced by increasing the effective thickness dIns of layer 32.
Another important feature of the invention is that at least a minimum required charge OCLAIM or Miller charge (see figure 4) must be transferred to the gate while the gate capacitance assumes its lower initial value of CjiM rather when the larger input capacitance CfiS8 determines the final switched state of the MOSFET. Hence the charge to be transferred is
Thus, the following minimum source to gate voltage must be applied. VGS£VGS(min) =
Also,
OG = VggC,,.. This could also be written as:
CfiM / Cfc, or
CfiM ' C&M ^ VGsfrnBx) / VGS(m(n(

Oscillograms illustrating VQS and VDS against time during switching on for each of the devices referenced i to iv in Table 1 are shown in figures 8 (a) to 8(d) respectively. The decrease in gate capacitance is clear from the second column in the Table, and the larger required input VGS and decreasing switching times are clear from both the Table and the oscillograms.
The last two devices iii and iv in Table 1 with minimized gate capacitance and wherein the ratio Cfi,./ Ca88 £ 1,34, represent MOSFET's -close to optimum, since the initial gate charge is already more than the minimum gate charge QClaims, (shown in figure 4 and which for a typical MOSFET is in the order of 30nC) required for complete switching. The increased gate to source input voltage VGS and spectacular drop in total switching times T, are noticeable.
In figure 4, comparative graphs for a known MOSFET is shown at A_and for MOSFET's according to the invention at B. The ratio CflesICfles for the known IRF 740 MOSFET is in the order of 2.5 whereas the same ratio for the last device according to the invention in Table 1 is 1.17. The device according to the invention has a total switching time of
In figure 5 there is shown a graph of total switching time as a function of the initial gate charge relative to the minimum gate charge QQ^,,,. The circle at 40 represents standard operation of an IRF 740 MOSFET. However, the circles at 42 and 44 illustrate the improved operation of the MOSFET's referenced iii and iv in Table 1.
In figure 6 there is shown a graph of rise time Tr against turn-on delay time Tdon for a plurality of different devices. The mark at 50 indicates standard operation of an IRF 740 MOSFET and the circles 52 and 54 indicate the improvement in total switching time Ts of the devices referenced iii and iv in Table 1 to a point where the rise time becomes negligible and the total switching time Ts approximates the turn-on delay time Tdon.
It can further be shown that the product of VGS and the square of the total switching time Ts is band limited as follows:
(2jc/3)2 QQ|mln, LS which means that the operating voltage V^ of the device according to the invention (which is much higher than the corresponding voltage for prior art devices) is limited as follows:
(27t/3)2 0^, LS / Ts2
and as illustrated in figure 7. The internal source resistance Rs has a negligible effect on these expressions and is therefore omitted for better clarity.
Hence, by minimizing the product of Miller charge or QClaims and LS, reduced total switching times Ts and required operating voltages VQS may be achieved.
In figure 9 there is shown a further embodiment of the device according to the invention and designated 90. The device comprises a gate 92, connected to a gate terminal 94. The insulation layer with increased effective thickness d^ is shown at 96. Conventional source and drain terminals are shown at 98 and 99 respectively. A further and so-called floating gate 95 is connected to a fourth and user accessible terminal 97.
In figure 10, yet another embodiment of the device according to the invention is shown at 100. In this case, the further gate 95 is not connected to a user accessible terminal, similar to terminal 97, but biasing resistors 102 and 104 may be provided as discrete components or integral with the chip body 106.

In figure 11, still a further embodiment of the device is shown at 110. The device 110 comprises a conventional MOSFET 112 having a gate 114. A capacitor 116 is connected in series between the gate and a gate terminal 118 of the device. The drain and source of the MOSFET are connected to a drain terminal 120 and source terminal 122 respectively. The device is packaged in a single package 124 providing the aforementioned terminals. An optional fourth terminal 124 connected to the gate 114 may also be provided. The capacitor 116 may be integrated with the MOSFET on a single chip. In other embodiments, the capacitor may be a discrete capacitor, but packaged in the same package 124. In still other embodiments, the optional fourth terminal may be omitted and biasing resistors between the gate terminal and the gate and between the gate and the source may be provided in the same package.
In figure 12 there is shown a diagram of a drive circuit 130 for the device 30, 90, 100 and 110 according to the invention. The drive circuit comprises a voltage source 132 (typically 50V - 600V and which may even exceed VDD) and a fast switching device 134 connected in a circuit and in close proximity to the gate terminal of the device according to the invention to reduce unwanted Inductance in the gate source circuit.

In use, the fast switching device 134 is controlled to apply a voltage which is sufficiently larger than the threshold voltage of the device to the gate of the device. As is clear from table 1, this voltage is larger than the voltage required in conventional devices. Due to the reduced LCR parameters in the gate source circuit, charge transfer to the gate of the device will be faster than with conventional devices which results in the faster switching times in the drain source circuit as shown in table 1.








We claim
1. An insulated gate device comprising a gate connected to a gate terminal and having a variable input capacitance means adjacent to the gate terminal, said means comprising a variable capacitance such that as the device is switched between an off state and an. on state, a ratio (CfiSS/Cfiss) between a final value of the capacitance (CfiSS) when the device is on and an initial value of the capacitance (ciss) when the device is off is 1 2. A device as claimed in claim 1 comprising a power metal oxide silicon field effect transistor (MOSFET).
3. A device as claimed in claim I or claim 2 wherein said variable capacitance means provides a capacitance such that the ratio (CfiSS/CiiSs) is 1 4. A device as claimed in claim 3 wherein said variable input capacitance means provides a capacitance such that the ratio is 1 5. A device as claimed in claim 1 wherein the input capacitance means comprises a capacitor connected between the gate terminal and the gate of the device.
6. A device as claimed in claim 2 wherein the MOSFET has a vertical structure in that the gate and a source of the device are provided on one face of a chip body of the device and a drain of the MOSFET is provided on an opposite face of the body, wherein said variable input capacitance means comprises a capacitor between the gate terminal and the gate of the devices.
7. A device as claimed in claim 6 wherein the capacitor is integrated on the chip body.
8. A device as claimed in claim 7 wherein the capacitor is superimposed on the gate of the MOSFET.

9. A device as claimed in claimed in claim 6 wherein the capacitor is a discrete
component connected in series between the gate and the gate terminal and
packaged in a common package.
10. A device as claimed in any one of claims 5 and 6 wherein the gate is connected directly to a fourth terminal of the device.
11. A device as claimed in claim 9 wherein biasing resistors connected to the gate are included in the package.

Documents:

3237-DELNP-2005-Abstract-(04-12-2008).pdf

3237-DELNP-2005-Abstract-(07-08-2008).pdf

3237-delnp-2005-abstract.pdf

3237-DELNP-2005-Claims-(04-12-2008).pdf

3237-DELNP-2005-Claims-(07-08-2008).pdf

3237-DELNP-2005-Claims-(18-08-2008).pdf

3237-delnp-2005-claims.pdf

3237-DELNP-2005-Correpsondence-Others-(18-08-2008).pdf

3237-DELNP-2005-Correspondence-Otehrs-(14-02-2011).pdf

3237-DELNP-2005-Correspondence-Others-(04-12-2008).pdf

3237-DELNP-2005-Correspondence-Others-(06-06-2008).pdf

3237-DELNP-2005-Correspondence-Others-(07-08-2008).pdf

3237-DELNP-2005-Correspondence-Others-(16-07-2008).pdf

3237-delnp-2005-correspondence-others.pdf

3237-DELNP-2005-Description (Complete)-(07-08-2008).pdf

3237-DELNP-2005-Description (Complete)-(18-08-2008).pdf

3237-delnp-2005-description (complete).pdf

3237-DELNP-2005-Drawings-(04-12-2008).pdf

3237-delnp-2005-drawings.pdf

3237-DELNP-2005-Form-1-(07-08-2008).pdf

3237-delnp-2005-form-1.pdf

3237-delnp-2005-form-13-(18-08-2008).pdf

3237-delnp-2005-form-13.pdf

3237-delnp-2005-form-18.pdf

3237-DELNP-2005-Form-2-(04-12-2008).pdf

3237-DELNP-2005-Form-2-(07-08-2008).pdf

3237-delnp-2005-form-2.pdf

3237-delnp-2005-form-26.pdf

3237-DELNP-2005-Form-3-(04-12-2008).pdf

3237-DELNP-2005-Form-3-(07-08-2008).pdf

3237-DELNP-2005-Form-3-(14-02-2011).pdf

3237-delnp-2005-form-3.pdf

3237-DELNP-2005-Form-5-(07-08-2008).pdf

3237-delnp-2005-form-5.pdf

3237-delnp-2005-gpa.pdf

3237-DELNP-2005-Others-Document-(07-08-2008).pdf

3237-delnp-2005-pct-210.pdf

3237-delnp-2005-pct-409.pdf

3237-DELNP-2005-Petetion-137-(14-02-2011).pdf


Patent Number 247442
Indian Patent Application Number 3237/DELNP/2005
PG Journal Number 15/2011
Publication Date 15-Apr-2011
Grant Date 07-Apr-2011
Date of Filing 21-Jul-2005
Name of Patentee NORTH WEST UNIVERSITY, a South African company
Applicant Address 1 HOFFMAN STREET, JOON VAN ROOY BUILDING 2531 POTCHEFSTROON, SOUTH AFRICA.
Inventors:
# Inventor's Name Inventor's Address
1 VISSER, BAREND 64 REITZ STREET, 2531 POTCHEFSTROOM, SOUTH AFRICA.
2 DEJAGER, OCKER, CORNELIS 48 TOM STREET, 2531 POTCHEFSTROOM, SOUTH AFRICA.
PCT International Classification Number H01 L 29/78
PCT International Application Number PCT/ZA2004/000005
PCT International Filing date 2004-01-21
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 2003/0552 2003-01-21 South Africa